diff --git a/arch/arm/src/imx6/chip/imx_gpio.h b/arch/arm/src/imx6/chip/imx_gpio.h index df1968ce99..b9d0e2755c 100644 --- a/arch/arm/src/imx6/chip/imx_gpio.h +++ b/arch/arm/src/imx6/chip/imx_gpio.h @@ -40,10 +40,8 @@ * Included Files ************************************************************************************/ -#ifndef __ASSEMBLY__ -# include -#endif -#include "up_arch.h" /* getreg32(), putreg32() */ +#include +#include /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/imx6/chip/imx_iomuxc.h b/arch/arm/src/imx6/chip/imx_iomuxc.h new file mode 100644 index 0000000000..d16d5dd4b1 --- /dev/null +++ b/arch/arm/src/imx6/chip/imx_iomuxc.h @@ -0,0 +1,1265 @@ +/************************************************************************************ + * arch/arm/src/imx6/imx_iomuxc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_IOMUXC_H +#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_IOMUXC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* IOMUXC Register Offsets **********************************************************/ +/* General Purpose Registers */ + +#define IMX_IOMUXC_GPR0_OFFSET 0x0000 +#define IMX_IOMUXC_GPR1_OFFSET 0x0004 +#define IMX_IOMUXC_GPR2_OFFSET 0x0008 +#define IMX_IOMUXC_GPR3_OFFSET 0x000c +#define IMX_IOMUXC_GPR4_OFFSET 0x0010 +#define IMX_IOMUXC_GPR5_OFFSET 0x0014 +#define IMX_IOMUXC_GPR6_OFFSET 0x0018 +#define IMX_IOMUXC_GPR7_OFFSET 0x001c +#define IMX_IOMUXC_GPR8_OFFSET 0x0020 +#define IMX_IOMUXC_GPR9_OFFSET 0x0024 +#define IMX_IOMUXC_GPR10_OFFSET 0x0028 +#define IMX_IOMUXC_GPR11_OFFSET 0x002c +#define IMX_IOMUXC_GPR12_OFFSET 0x0030 +#define IMX_IOMUXC_GPR13_OFFSET 0x0034 + +/* Pad Mux Registers */ + +#define IMX_PADMUX_SD2_DATA1_OFFSET 0x004c +#define IMX_PADMUX_SD2_DATA2_OFFSET 0x0050 +#define IMX_PADMUX_SD2_DATA0_OFFSET 0x0054 +#define IMX_PADMUX_RGMII_TXC_OFFSET 0x0058 +#define IMX_PADMUX_RGMII_TD0_OFFSET 0x005c +#define IMX_PADMUX_RGMII_TD1_OFFSET 0x0060 +#define IMX_PADMUX_RGMII_TD2_OFFSET 0x0064 +#define IMX_PADMUX_RGMII_TD3_OFFSET 0x0068 +#define IMX_PADMUX_RGMII_RX_CTL_OFFSET 0x006c +#define IMX_PADMUX_RGMII_RD0_OFFSET 0x0070 +#define IMX_PADMUX_RGMII_TX_CTL_OFFSET 0x0074 +#define IMX_PADMUX_RGMII_RD1_OFFSET 0x0078 +#define IMX_PADMUX_RGMII_RD2_OFFSET 0x007c +#define IMX_PADMUX_RGMII_RD3_OFFSET 0x0080 +#define IMX_PADMUX_RGMII_RXC_OFFSET 0x0084 +#define IMX_PADMUX_EIM_ADDR25_OFFSET 0x0088 +#define IMX_PADMUX_EIM_EB2_B_OFFSET 0x008c +#define IMX_PADMUX_EIM_DATA16_OFFSET 0x0090 +#define IMX_PADMUX_EIM_DATA17_OFFSET 0x0094 +#define IMX_PADMUX_EIM_DATA18_OFFSET 0x0098 +#define IMX_PADMUX_EIM_DATA19_OFFSET 0x009c +#define IMX_PADMUX_EIM_DATA20_OFFSET 0x00a0 +#define IMX_PADMUX_EIM_DATA21_OFFSET 0x00a4 +#define IMX_PADMUX_EIM_DATA22_OFFSET 0x00a8 +#define IMX_PADMUX_EIM_DATA23_OFFSET 0x00ac +#define IMX_PADMUX_EIM_EB3_B_OFFSET 0x00b0 +#define IMX_PADMUX_EIM_DATA24_OFFSET 0x00b4 +#define IMX_PADMUX_EIM_DATA25_OFFSET 0x00b8 +#define IMX_PADMUX_EIM_DATA26_OFFSET 0x00bc +#define IMX_PADMUX_EIM_DATA27_OFFSET 0x00c0 +#define IMX_PADMUX_EIM_DATA28_OFFSET 0x00c4 +#define IMX_PADMUX_EIM_DATA29_OFFSET 0x00c8 +#define IMX_PADMUX_EIM_DATA30_OFFSET 0x00cc +#define IMX_PADMUX_EIM_DATA31_OFFSET 0x00d0 +#define IMX_PADMUX_EIM_ADDR24_OFFSET 0x00d4 +#define IMX_PADMUX_EIM_ADDR23_OFFSET 0x00d8 +#define IMX_PADMUX_EIM_ADDR22_OFFSET 0x00dc +#define IMX_PADMUX_EIM_ADDR21_OFFSET 0x00e0 +#define IMX_PADMUX_EIM_ADDR20_OFFSET 0x00e4 +#define IMX_PADMUX_EIM_ADDR19_OFFSET 0x00e8 +#define IMX_PADMUX_EIM_ADDR18_OFFSET 0x00ec +#define IMX_PADMUX_EIM_ADDR17_OFFSET 0x00f0 +#define IMX_PADMUX_EIM_ADDR16_OFFSET 0x00f4 +#define IMX_PADMUX_EIM_CS0_B_OFFSET 0x00f8 +#define IMX_PADMUX_EIM_CS1_B_OFFSET 0x00fc +#define IMX_PADMUX_EIM_OE_B_OFFSET 0x0100 +#define IMX_PADMUX_EIM_RW_OFFSET 0x0104 +#define IMX_PADMUX_EIM_LBA_B_OFFSET 0x0108 +#define IMX_PADMUX_EIM_EB0_B_OFFSET 0x010c +#define IMX_PADMUX_EIM_EB1_B_OFFSET 0x0110 +#define IMX_PADMUX_EIM_AD00_OFFSET 0x0114 +#define IMX_PADMUX_EIM_AD01_OFFSET 0x0118 +#define IMX_PADMUX_EIM_AD02_OFFSET 0x011c +#define IMX_PADMUX_EIM_AD03_OFFSET 0x0120 +#define IMX_PADMUX_EIM_AD04_OFFSET 0x0124 +#define IMX_PADMUX_EIM_AD05_OFFSET 0x0128 +#define IMX_PADMUX_EIM_AD06_OFFSET 0x012c +#define IMX_PADMUX_EIM_AD07_OFFSET 0x0130 +#define IMX_PADMUX_EIM_AD08_OFFSET 0x0134 +#define IMX_PADMUX_EIM_AD09_OFFSET 0x0138 +#define IMX_PADMUX_EIM_AD10_OFFSET 0x013c +#define IMX_PADMUX_EIM_AD11_OFFSET 0x0140 +#define IMX_PADMUX_EIM_AD12_OFFSET 0x0144 +#define IMX_PADMUX_EIM_AD13_OFFSET 0x0148 +#define IMX_PADMUX_EIM_AD14_OFFSET 0x014c +#define IMX_PADMUX_EIM_AD15_OFFSET 0x0150 +#define IMX_PADMUX_EIM_WAIT_B_OFFSET 0x0154 +#define IMX_PADMUX_EIM_BCLK_OFFSET 0x0158 +#define IMX_PADMUX_DI0_DISP_CLK_OFFSET 0x015c +#define IMX_PADMUX_DI0_PIN15_OFFSET 0x0160 +#define IMX_PADMUX_DI0_PIN02_OFFSET 0x0164 +#define IMX_PADMUX_DI0_PIN03_OFFSET 0x0168 +#define IMX_PADMUX_DI0_PIN04_OFFSET 0x016c +#define IMX_PADMUX_DISP0_DATA00_OFFSET 0x0170 +#define IMX_PADMUX_DISP0_DATA01_OFFSET 0x0174 +#define IMX_PADMUX_DISP0_DATA02_OFFSET 0x0178 +#define IMX_PADMUX_DISP0_DATA03_OFFSET 0x017c +#define IMX_PADMUX_DISP0_DATA04_OFFSET 0x0180 +#define IMX_PADMUX_DISP0_DATA05_OFFSET 0x0184 +#define IMX_PADMUX_DISP0_DATA06_OFFSET 0x0188 +#define IMX_PADMUX_DISP0_DATA07_OFFSET 0x018c +#define IMX_PADMUX_DISP0_DATA08_OFFSET 0x0190 +#define IMX_PADMUX_DISP0_DATA09_OFFSET 0x0194 +#define IMX_PADMUX_DISP0_DATA10_OFFSET 0x0198 +#define IMX_PADMUX_DISP0_DATA11_OFFSET 0x019c +#define IMX_PADMUX_DISP0_DATA12_OFFSET 0x01a0 +#define IMX_PADMUX_DISP0_DATA13_OFFSET 0x01a4 +#define IMX_PADMUX_DISP0_DATA14_OFFSET 0x01a8 +#define IMX_PADMUX_DISP0_DATA15_OFFSET 0x01ac +#define IMX_PADMUX_DISP0_DATA16_OFFSET 0x01b0 +#define IMX_PADMUX_DISP0_DATA17_OFFSET 0x01b4 +#define IMX_PADMUX_DISP0_DATA18_OFFSET 0x01b8 +#define IMX_PADMUX_DISP0_DATA19_OFFSET 0x01bc +#define IMX_PADMUX_DISP0_DATA20_OFFSET 0x01c0 +#define IMX_PADMUX_DISP0_DATA21_OFFSET 0x01c4 +#define IMX_PADMUX_DISP0_DATA22_OFFSET 0x01c8 +#define IMX_PADMUX_DISP0_DATA23_OFFSET 0x01cc +#define IMX_PADMUX_ENET_MDIO_OFFSET 0x01d0 +#define IMX_PADMUX_ENET_REF_CLK_OFFSET 0x01d4 +#define IMX_PADMUX_ENET_RX_ER_OFFSET 0x01d8 +#define IMX_PADMUX_ENET_CRS_DV_OFFSET 0x01dc +#define IMX_PADMUX_ENET_RX_DATA1_OFFSET 0x01e0 +#define IMX_PADMUX_ENET_RX_DATA0_OFFSET 0x01e4 +#define IMX_PADMUX_ENET_TX_EN_OFFSET 0x01e8 +#define IMX_PADMUX_ENET_TX_DATA1_OFFSET 0x01ec +#define IMX_PADMUX_ENET_TX_DATA0_OFFSET 0x01f0 +#define IMX_PADMUX_ENET_MDC_OFFSET 0x01f4 +#define IMX_PADMUX_KEY_COL0_OFFSET 0x01f8 +#define IMX_PADMUX_KEY_ROW0_OFFSET 0x01fc +#define IMX_PADMUX_KEY_COL1_OFFSET 0x0200 +#define IMX_PADMUX_KEY_ROW1_OFFSET 0x0204 +#define IMX_PADMUX_KEY_COL2_OFFSET 0x0208 +#define IMX_PADMUX_KEY_ROW2_OFFSET 0x020c +#define IMX_PADMUX_KEY_COL3_OFFSET 0x0210 +#define IMX_PADMUX_KEY_ROW3_OFFSET 0x0214 +#define IMX_PADMUX_KEY_COL4_OFFSET 0x0218 +#define IMX_PADMUX_KEY_ROW4_OFFSET 0x021c +#define IMX_PADMUX_GPIO00_OFFSET 0x0220 +#define IMX_PADMUX_GPIO01_OFFSET 0x0224 +#define IMX_PADMUX_GPIO09_OFFSET 0x0228 +#define IMX_PADMUX_GPIO03_OFFSET 0x022c +#define IMX_PADMUX_GPIO06_OFFSET 0x0230 +#define IMX_PADMUX_GPIO02_OFFSET 0x0234 +#define IMX_PADMUX_GPIO04_OFFSET 0x0238 +#define IMX_PADMUX_GPIO05_OFFSET 0x023c +#define IMX_PADMUX_GPIO07_OFFSET 0x0240 +#define IMX_PADMUX_GPIO08_OFFSET 0x0244 +#define IMX_PADMUX_GPIO16_OFFSET 0x0248 +#define IMX_PADMUX_GPIO17_OFFSET 0x024c +#define IMX_PADMUX_GPIO18_OFFSET 0x0250 +#define IMX_PADMUX_GPIO19_OFFSET 0x0254 +#define IMX_PADMUX_CSI0_PIXCLK_OFFSET 0x0258 +#define IMX_PADMUX_CSI0_HSYNC_OFFSET 0x025c +#define IMX_PADMUX_CSI0_DATA_EN_OFFSET 0x0260 +#define IMX_PADMUX_CSI0_VSYNC_OFFSET 0x0264 +#define IMX_PADMUX_CSI0_DATA04_OFFSET 0x0268 +#define IMX_PADMUX_CSI0_DATA05_OFFSET 0x026c +#define IMX_PADMUX_CSI0_DATA06_OFFSET 0x0270 +#define IMX_PADMUX_CSI0_DATA07_OFFSET 0x0274 +#define IMX_PADMUX_CSI0_DATA08_OFFSET 0x0278 +#define IMX_PADMUX_CSI0_DATA09_OFFSET 0x027c +#define IMX_PADMUX_CSI0_DATA10_OFFSET 0x0280 +#define IMX_PADMUX_CSI0_DATA11_OFFSET 0x0284 +#define IMX_PADMUX_CSI0_DATA12_OFFSET 0x0288 +#define IMX_PADMUX_CSI0_DATA13_OFFSET 0x028c +#define IMX_PADMUX_CSI0_DATA14_OFFSET 0x0290 +#define IMX_PADMUX_CSI0_DATA15_OFFSET 0x0294 +#define IMX_PADMUX_CSI0_DATA16_OFFSET 0x0298 +#define IMX_PADMUX_CSI0_DATA17_OFFSET 0x029c +#define IMX_PADMUX_CSI0_DATA18_OFFSET 0x02a0 +#define IMX_PADMUX_CSI0_DATA19_OFFSET 0x02a4 +#define IMX_PADMUX_SD3_DATA7_OFFSET 0x02a8 +#define IMX_PADMUX_SD3_DATA6_OFFSET 0x02ac +#define IMX_PADMUX_SD3_DATA5_OFFSET 0x02b0 +#define IMX_PADMUX_SD3_DATA4_OFFSET 0x02b4 +#define IMX_PADMUX_SD3_CMD_OFFSET 0x02b8 +#define IMX_PADMUX_SD3_CLK_OFFSET 0x02bc +#define IMX_PADMUX_SD3_DATA0_OFFSET 0x02c0 +#define IMX_PADMUX_SD3_DATA1_OFFSET 0x02c4 +#define IMX_PADMUX_SD3_DATA2_OFFSET 0x02c8 +#define IMX_PADMUX_SD3_DATA3_OFFSET 0x02cc +#define IMX_PADMUX_SD3_RESET_OFFSET 0x02d0 +#define IMX_PADMUX_NAND_CLE_OFFSET 0x02d4 +#define IMX_PADMUX_NAND_ALE_OFFSET 0x02d8 +#define IMX_PADMUX_NAND_WP_B_OFFSET 0x02dc +#define IMX_PADMUX_NAND_READY_B_OFFSET 0x02e0 +#define IMX_PADMUX_NAND_CS0_B_OFFSET 0x02e4 +#define IMX_PADMUX_NAND_CS1_B_OFFSET 0x02e8 +#define IMX_PADMUX_NAND_CS2_B_OFFSET 0x02ec +#define IMX_PADMUX_NAND_CS3_B_OFFSET 0x02f0 +#define IMX_PADMUX_SD4_CMD_OFFSET 0x02f4 +#define IMX_PADMUX_SD4_CLK_OFFSET 0x02f8 +#define IMX_PADMUX_NAND_DATA00_OFFSET 0x02fc +#define IMX_PADMUX_NAND_DATA01_OFFSET 0x0300 +#define IMX_PADMUX_NAND_DATA02_OFFSET 0x0304 +#define IMX_PADMUX_NAND_DATA03_OFFSET 0x0308 +#define IMX_PADMUX_NAND_DATA04_OFFSET 0x030c +#define IMX_PADMUX_NAND_DATA05_OFFSET 0x0310 +#define IMX_PADMUX_NAND_DATA06_OFFSET 0x0314 +#define IMX_PADMUX_NAND_DATA07_OFFSET 0x0318 +#define IMX_PADMUX_SD4_DATA0_OFFSET 0x031c +#define IMX_PADMUX_SD4_DATA1_OFFSET 0x0320 +#define IMX_PADMUX_SD4_DATA2_OFFSET 0x0324 +#define IMX_PADMUX_SD4_DATA3_OFFSET 0x0328 +#define IMX_PADMUX_SD4_DATA4_OFFSET 0x032c +#define IMX_PADMUX_SD4_DATA5_OFFSET 0x0330 +#define IMX_PADMUX_SD4_DATA6_OFFSET 0x0334 +#define IMX_PADMUX_SD4_DATA7_OFFSET 0x0338 +#define IMX_PADMUX_SD1_DATA1_OFFSET 0x033c +#define IMX_PADMUX_SD1_DATA0_OFFSET 0x0340 +#define IMX_PADMUX_SD1_DATA3_OFFSET 0x0344 +#define IMX_PADMUX_SD1_CMD_OFFSET 0x0348 +#define IMX_PADMUX_SD1_DATA2_OFFSET 0x034c +#define IMX_PADMUX_SD1_CLK_OFFSET 0x0350 +#define IMX_PADMUX_SD2_CLK_OFFSET 0x0354 +#define IMX_PADMUX_SD2_CMD_OFFSET 0x0358 +#define IMX_PADMUX_SD2_DATA3_OFFSET 0x035c + +/* Pad Control Registers */ + +#define IMX_PADCTL_SD2_DATA1_OFFSET 0x0360 +#define IMX_PADCTL_SD2_DATA2_OFFSET 0x0364 +#define IMX_PADCTL_SD2_DATA0_OFFSET 0x0368 +#define IMX_PADCTL_RGMII_TXC_OFFSET 0x036c +#define IMX_PADCTL_RGMII_TD0_OFFSET 0x0370 +#define IMX_PADCTL_RGMII_TD1_OFFSET 0x0374 +#define IMX_PADCTL_RGMII_TD2_OFFSET 0x0378 +#define IMX_PADCTL_RGMII_TD3_OFFSET 0x037c +#define IMX_PADCTL_RGMII_RX_CTL_OFFSET 0x0380 +#define IMX_PADCTL_RGMII_RD0_OFFSET 0x0384 +#define IMX_PADCTL_RGMII_TX_CTL_OFFSET 0x0388 +#define IMX_PADCTL_RGMII_RD1_OFFSET 0x038c +#define IMX_PADCTL_RGMII_RD2_OFFSET 0x0390 +#define IMX_PADCTL_RGMII_RD3_OFFSET 0x0394 +#define IMX_PADCTL_RGMII_RXC_OFFSET 0x0398 +#define IMX_PADCTL_EIM_ADDR25_OFFSET 0x039c +#define IMX_PADCTL_EIM_EB2_B_OFFSET 0x03a0 +#define IMX_PADCTL_EIM_DATA16_OFFSET 0x03a4 +#define IMX_PADCTL_EIM_DATA17_OFFSET 0x03a8 +#define IMX_PADCTL_EIM_DATA18_OFFSET 0x03ac +#define IMX_PADCTL_EIM_DATA19_OFFSET 0x03b0 +#define IMX_PADCTL_EIM_DATA20_OFFSET 0x03b4 +#define IMX_PADCTL_EIM_DATA21_OFFSET 0x03b8 +#define IMX_PADCTL_EIM_DATA22_OFFSET 0x03bc +#define IMX_PADCTL_EIM_DATA23_OFFSET 0x03c0 +#define IMX_PADCTL_EIM_EB3_B_OFFSET 0x03c4 +#define IMX_PADCTL_EIM_DATA24_OFFSET 0x03c8 +#define IMX_PADCTL_EIM_DATA25_OFFSET 0x03cc +#define IMX_PADCTL_EIM_DATA26_OFFSET 0x03d0 +#define IMX_PADCTL_EIM_DATA27_OFFSET 0x03d4 +#define IMX_PADCTL_EIM_DATA28_OFFSET 0x03d8 +#define IMX_PADCTL_EIM_DATA29_OFFSET 0x03dc +#define IMX_PADCTL_EIM_DATA30_OFFSET 0x03e0 +#define IMX_PADCTL_EIM_DATA31_OFFSET 0x03e4 +#define IMX_PADCTL_EIM_ADDR24_OFFSET 0x03e8 +#define IMX_PADCTL_EIM_ADDR23_OFFSET 0x03ec +#define IMX_PADCTL_EIM_ADDR22_OFFSET 0x03f0 +#define IMX_PADCTL_EIM_ADDR21_OFFSET 0x03f4 +#define IMX_PADCTL_EIM_ADDR20_OFFSET 0x03f8 +#define IMX_PADCTL_EIM_ADDR19_OFFSET 0x03fc +#define IMX_PADCTL_EIM_ADDR18_OFFSET 0x0400 +#define IMX_PADCTL_EIM_ADDR17_OFFSET 0x0404 +#define IMX_PADCTL_EIM_ADDR16_OFFSET 0x0408 +#define IMX_PADCTL_EIM_CS0_B_OFFSET 0x040c +#define IMX_PADCTL_EIM_CS1_B_OFFSET 0x0410 +#define IMX_PADCTL_EIM_OE_B_OFFSET 0x0414 +#define IMX_PADCTL_EIM_RW_OFFSET 0x0418 +#define IMX_PADCTL_EIM_LBA_B_OFFSET 0x041c +#define IMX_PADCTL_EIM_EB0_B_OFFSET 0x0420 +#define IMX_PADCTL_EIM_EB1_B_OFFSET 0x0424 +#define IMX_PADCTL_EIM_AD00_OFFSET 0x0428 +#define IMX_PADCTL_EIM_AD01_OFFSET 0x042c +#define IMX_PADCTL_EIM_AD02_OFFSET 0x0430 +#define IMX_PADCTL_EIM_AD03_OFFSET 0x0434 +#define IMX_PADCTL_EIM_AD04_OFFSET 0x0438 +#define IMX_PADCTL_EIM_AD05_OFFSET 0x043c +#define IMX_PADCTL_EIM_AD06_OFFSET 0x0440 +#define IMX_PADCTL_EIM_AD07_OFFSET 0x0444 +#define IMX_PADCTL_EIM_AD08_OFFSET 0x0448 +#define IMX_PADCTL_EIM_AD09_OFFSET 0x044c +#define IMX_PADCTL_EIM_AD10_OFFSET 0x0450 +#define IMX_PADCTL_EIM_AD11_OFFSET 0x0454 +#define IMX_PADCTL_EIM_AD12_OFFSET 0x0458 +#define IMX_PADCTL_EIM_AD13_OFFSET 0x045c +#define IMX_PADCTL_EIM_AD14_OFFSET 0x0460 +#define IMX_PADCTL_EIM_AD15_OFFSET 0x0464 +#define IMX_PADCTL_EIM_WAIT_B_OFFSET 0x0468 +#define IMX_PADCTL_EIM_BCLK_OFFSET 0x046c +#define IMX_PADCTL_DI0_DISP_CLK_OFFSET 0x0470 +#define IMX_PADCTL_DI0_PIN15_OFFSET 0x0474 +#define IMX_PADCTL_DI0_PIN02_OFFSET 0x0478 +#define IMX_PADCTL_DI0_PIN03_OFFSET 0x047c +#define IMX_PADCTL_DI0_PIN04_OFFSET 0x0480 +#define IMX_PADCTL_DISP0_DATA00_OFFSET 0x0484 +#define IMX_PADCTL_DISP0_DATA01_OFFSET 0x0488 +#define IMX_PADCTL_DISP0_DATA02_OFFSET 0x048c +#define IMX_PADCTL_DISP0_DATA03_OFFSET 0x0490 +#define IMX_PADCTL_DISP0_DATA04_OFFSET 0x0494 +#define IMX_PADCTL_DISP0_DATA05_OFFSET 0x0498 +#define IMX_PADCTL_DISP0_DATA06_OFFSET 0x049c +#define IMX_PADCTL_DISP0_DATA07_OFFSET 0x04a0 +#define IMX_PADCTL_DISP0_DATA08_OFFSET 0x04a4 +#define IMX_PADCTL_DISP0_DATA09_OFFSET 0x04a8 +#define IMX_PADCTL_DISP0_DATA10_OFFSET 0x04ac +#define IMX_PADCTL_DISP0_DATA11_OFFSET 0x04b0 +#define IMX_PADCTL_DISP0_DATA12_OFFSET 0x04b4 +#define IMX_PADCTL_DISP0_DATA13_OFFSET 0x04b8 +#define IMX_PADCTL_DISP0_DATA14_OFFSET 0x04bc +#define IMX_PADCTL_DISP0_DATA15_OFFSET 0x04c0 +#define IMX_PADCTL_DISP0_DATA16_OFFSET 0x04c4 +#define IMX_PADCTL_DISP0_DATA17_OFFSET 0x04c8 +#define IMX_PADCTL_DISP0_DATA18_OFFSET 0x04cc +#define IMX_PADCTL_DISP0_DATA19_OFFSET 0x04d0 +#define IMX_PADCTL_DISP0_DATA20_OFFSET 0x04d4 +#define IMX_PADCTL_DISP0_DATA21_OFFSET 0x04d8 +#define IMX_PADCTL_DISP0_DATA22_OFFSET 0x04dc +#define IMX_PADCTL_DISP0_DATA23_OFFSET 0x04e0 +#define IMX_PADCTL_ENET_MDIO_OFFSET 0x04e4 +#define IMX_PADCTL_ENET_REF_CLK_OFFSET 0x04e8 +#define IMX_PADCTL_ENET_RX_ER_OFFSET 0x04ec +#define IMX_PADCTL_ENET_CRS_DV_OFFSET 0x04f0 +#define IMX_PADCTL_ENET_RX_DATA1_OFFSET 0x04f4 +#define IMX_PADCTL_ENET_RX_DATA0_OFFSET 0x04f8 +#define IMX_PADCTL_ENET_TX_EN_OFFSET 0x04fc +#define IMX_PADCTL_ENET_TX_DATA1_OFFSET 0x0500 +#define IMX_PADCTL_ENET_TX_DATA0_OFFSET 0x0504 +#define IMX_PADCTL_ENET_MDC_OFFSET 0x0508 +#define IMX_PADCTL_DRAM_SDQS5_P_OFFSET 0x050c +#define IMX_PADCTL_DRAM_DQM5_OFFSET 0x0510 +#define IMX_PADCTL_DRAM_DQM4_OFFSET 0x0514 +#define IMX_PADCTL_DRAM_SDQS4_P_OFFSET 0x0518 +#define IMX_PADCTL_DRAM_SDQS3_P_OFFSET 0x051c +#define IMX_PADCTL_DRAM_DQM3_OFFSET 0x0520 +#define IMX_PADCTL_DRAM_SDQS2_P_OFFSET 0x0524 +#define IMX_PADCTL_DRAM_DQM2_OFFSET 0x0528 +#define IMX_PADCTL_DRAM_ADDR00_OFFSET 0x052c +#define IMX_PADCTL_DRAM_ADDR01_OFFSET 0x0530 +#define IMX_PADCTL_DRAM_ADDR02_OFFSET 0x0534 +#define IMX_PADCTL_DRAM_ADDR03_OFFSET 0x0538 +#define IMX_PADCTL_DRAM_ADDR04_OFFSET 0x053c +#define IMX_PADCTL_DRAM_ADDR05_OFFSET 0x0540 +#define IMX_PADCTL_DRAM_ADDR06_OFFSET 0x0544 +#define IMX_PADCTL_DRAM_ADDR07_OFFSET 0x0548 +#define IMX_PADCTL_DRAM_ADDR08_OFFSET 0x054c +#define IMX_PADCTL_DRAM_ADDR09_OFFSET 0x0550 +#define IMX_PADCTL_DRAM_ADDR10_OFFSET 0x0554 +#define IMX_PADCTL_DRAM_ADDR11_OFFSET 0x0558 +#define IMX_PADCTL_DRAM_ADDR12_OFFSET 0x055c +#define IMX_PADCTL_DRAM_ADDR13_OFFSET 0x0560 +#define IMX_PADCTL_DRAM_ADDR14_OFFSET 0x0564 +#define IMX_PADCTL_DRAM_ADDR15_OFFSET 0x0568 +#define IMX_PADCTL_DRAM_CAS_B_OFFSET 0x056c +#define IMX_PADCTL_DRAM_CS0_B_OFFSET 0x0570 +#define IMX_PADCTL_DRAM_CS1_B_OFFSET 0x0574 +#define IMX_PADCTL_DRAM_RAS_B_OFFSET 0x0578 +#define IMX_PADCTL_DRAM_RESET_OFFSET 0x057c +#define IMX_PADCTL_DRAM_SDBA0_OFFSET 0x0580 +#define IMX_PADCTL_DRAM_SDBA1_OFFSET 0x0584 +#define IMX_PADCTL_DRAM_SDCLK0_P_OFFSET 0x0588 +#define IMX_PADCTL_DRAM_SDBA2_OFFSET 0x058c +#define IMX_PADCTL_DRAM_SDCKE0_OFFSET 0x0590 +#define IMX_PADCTL_DRAM_SDCLK1_P_OFFSET 0x0594 +#define IMX_PADCTL_DRAM_SDCKE1_OFFSET 0x0598 +#define IMX_PADCTL_DRAM_ODT0_OFFSET 0x059c +#define IMX_PADCTL_DRAM_ODT1_OFFSET 0x05a0 +#define IMX_PADCTL_DRAM_SDWE_B_OFFSET 0x05a4 +#define IMX_PADCTL_DRAM_SDQS0_P_OFFSET 0x05a8 +#define IMX_PADCTL_DRAM_DQM0_OFFSET 0x05ac +#define IMX_PADCTL_DRAM_SDQS1_P_OFFSET 0x05b0 +#define IMX_PADCTL_DRAM_DQM1_OFFSET 0x05b4 +#define IMX_PADCTL_DRAM_SDQS6_P_OFFSET 0x05b8 +#define IMX_PADCTL_DRAM_DQM6_OFFSET 0x05bc +#define IMX_PADCTL_DRAM_SDQS7_P_OFFSET 0x05c0 +#define IMX_PADCTL_DRAM_DQM7_OFFSET 0x05c4 +#define IMX_PADCTL_KEY_COL0_OFFSET 0x05c8 +#define IMX_PADCTL_KEY_ROW0_OFFSET 0x05cc +#define IMX_PADCTL_KEY_COL1_OFFSET 0x05d0 +#define IMX_PADCTL_KEY_ROW1_OFFSET 0x05d4 +#define IMX_PADCTL_KEY_COL2_OFFSET 0x05d8 +#define IMX_PADCTL_KEY_ROW2_OFFSET 0x05dc +#define IMX_PADCTL_KEY_COL3_OFFSET 0x05e0 +#define IMX_PADCTL_KEY_ROW3_OFFSET 0x05e4 +#define IMX_PADCTL_KEY_COL4_OFFSET 0x05e8 +#define IMX_PADCTL_KEY_ROW4_OFFSET 0x05ec +#define IMX_PADCTL_GPIO00_OFFSET 0x05f0 +#define IMX_PADCTL_GPIO01_OFFSET 0x05f4 +#define IMX_PADCTL_GPIO09_OFFSET 0x05f8 +#define IMX_PADCTL_GPIO03_OFFSET 0x05fc +#define IMX_PADCTL_GPIO06_OFFSET 0x0600 +#define IMX_PADCTL_GPIO02_OFFSET 0x0604 +#define IMX_PADCTL_GPIO04_OFFSET 0x0608 +#define IMX_PADCTL_GPIO05_OFFSET 0x060c +#define IMX_PADCTL_GPIO07_OFFSET 0x0610 +#define IMX_PADCTL_GPIO08_OFFSET 0x0614 +#define IMX_PADCTL_GPIO16_OFFSET 0x0618 +#define IMX_PADCTL_GPIO17_OFFSET 0x061c +#define IMX_PADCTL_GPIO18_OFFSET 0x0620 +#define IMX_PADCTL_GPIO19_OFFSET 0x0624 +#define IMX_PADCTL_CSI0_PIXCLK_OFFSET 0x0628 +#define IMX_PADCTL_CSI0_HSYNC_OFFSET 0x062c +#define IMX_PADCTL_CSI0_DATA_EN_OFFSET 0x0630 +#define IMX_PADCTL_CSI0_VSYNC_OFFSET 0x0634 +#define IMX_PADCTL_CSI0_DATA04_OFFSET 0x0638 +#define IMX_PADCTL_CSI0_DATA05_OFFSET 0x063c +#define IMX_PADCTL_CSI0_DATA06_OFFSET 0x0640 +#define IMX_PADCTL_CSI0_DATA07_OFFSET 0x0644 +#define IMX_PADCTL_CSI0_DATA08_OFFSET 0x0648 +#define IMX_PADCTL_CSI0_DATA09_OFFSET 0x064c +#define IMX_PADCTL_CSI0_DATA10_OFFSET 0x0650 +#define IMX_PADCTL_CSI0_DATA11_OFFSET 0x0654 +#define IMX_PADCTL_CSI0_DATA12_OFFSET 0x0658 +#define IMX_PADCTL_CSI0_DATA13_OFFSET 0x065c +#define IMX_PADCTL_CSI0_DATA14_OFFSET 0x0660 +#define IMX_PADCTL_CSI0_DATA15_OFFSET 0x0664 +#define IMX_PADCTL_CSI0_DATA16_OFFSET 0x0668 +#define IMX_PADCTL_CSI0_DATA17_OFFSET 0x066c +#define IMX_PADCTL_CSI0_DATA18_OFFSET 0x0670 +#define IMX_PADCTL_CSI0_DATA19_OFFSET 0x0674 +#define IMX_PADCTL_JTAG_TMS_OFFSET 0x0678 +#define IMX_PADCTL_JTAG_MOD_OFFSET 0x067c +#define IMX_PADCTL_JTAG_TRSTB_OFFSET 0x0680 +#define IMX_PADCTL_JTAG_TDI_OFFSET 0x0684 +#define IMX_PADCTL_JTAG_TCK_OFFSET 0x0688 +#define IMX_PADCTL_JTAG_TDO_OFFSET 0x068c +#define IMX_PADCTL_SD3_DATA7_OFFSET 0x0690 +#define IMX_PADCTL_SD3_DATA6_OFFSET 0x0694 +#define IMX_PADCTL_SD3_DATA5_OFFSET 0x0698 +#define IMX_PADCTL_SD3_DATA4_OFFSET 0x069c +#define IMX_PADCTL_SD3_CMD_OFFSET 0x06a0 +#define IMX_PADCTL_SD3_CLK_OFFSET 0x06a4 +#define IMX_PADCTL_SD3_DATA0_OFFSET 0x06a8 +#define IMX_PADCTL_SD3_DATA1_OFFSET 0x06ac +#define IMX_PADCTL_SD3_DATA2_OFFSET 0x06b0 +#define IMX_PADCTL_SD3_DATA3_OFFSET 0x06b4 +#define IMX_PADCTL_SD3_RESET_OFFSET 0x06b8 +#define IMX_PADCTL_NAND_CLE_OFFSET 0x06bc +#define IMX_PADCTL_NAND_ALE_OFFSET 0x06c0 +#define IMX_PADCTL_NAND_WP_B_OFFSET 0x06c4 +#define IMX_PADCTL_NAND_READY_B_OFFSET 0x06c8 +#define IMX_PADCTL_NAND_CS0_B_OFFSET 0x06cc +#define IMX_PADCTL_NAND_CS1_B_OFFSET 0x06d0 +#define IMX_PADCTL_NAND_CS2_B_OFFSET 0x06d4 +#define IMX_PADCTL_NAND_CS3_B_OFFSET 0x06d8 +#define IMX_PADCTL_SD4_CMD_OFFSET 0x06dc +#define IMX_PADCTL_SD4_CLK_OFFSET 0x06e0 +#define IMX_PADCTL_NAND_DATA00_OFFSET 0x06e4 +#define IMX_PADCTL_NAND_DATA01_OFFSET 0x06e8 +#define IMX_PADCTL_NAND_DATA02_OFFSET 0x06ec +#define IMX_PADCTL_NAND_DATA03_OFFSET 0x06f0 +#define IMX_PADCTL_NAND_DATA04_OFFSET 0x06f4 +#define IMX_PADCTL_NAND_DATA05_OFFSET 0x06f8 +#define IMX_PADCTL_NAND_DATA06_OFFSET 0x06fc +#define IMX_PADCTL_NAND_DATA07_OFFSET 0x0700 +#define IMX_PADCTL_SD4_DATA0_OFFSET 0x0704 +#define IMX_PADCTL_SD4_DATA1_OFFSET 0x0708 +#define IMX_PADCTL_SD4_DATA2_OFFSET 0x070c +#define IMX_PADCTL_SD4_DATA3_OFFSET 0x0710 +#define IMX_PADCTL_SD4_DATA4_OFFSET 0x0714 +#define IMX_PADCTL_SD4_DATA5_OFFSET 0x0718 +#define IMX_PADCTL_SD4_DATA6_OFFSET 0x071c +#define IMX_PADCTL_SD4_DATA7_OFFSET 0x0720 +#define IMX_PADCTL_SD1_DATA1_OFFSET 0x0724 +#define IMX_PADCTL_SD1_DATA0_OFFSET 0x0728 +#define IMX_PADCTL_SD1_DATA3_OFFSET 0x072c +#define IMX_PADCTL_SD1_CMD_OFFSET 0x0730 +#define IMX_PADCTL_SD1_DATA2_OFFSET 0x0734 +#define IMX_PADCTL_SD1_CLK_OFFSET 0x0738 +#define IMX_PADCTL_SD2_CLK_OFFSET 0x073c +#define IMX_PADCTL_SD2_CMD_OFFSET 0x0740 +#define IMX_PADCTL_SD2_DATA3_OFFSET 0x0744 + +/* Pad Group Control Registers */ + +#define IMX_PADGROUP_B7DS_OFFSET 0x0748 +#define IMX_PADGROUP_ADDDS_OFFSET 0x074c +#define IMX_PADGROUP_DDRMODE_CTL_OFFSET 0x0750 +#define IMX_PADGROUP_TERM_CTL0_OFFSET 0x0754 +#define IMX_PADGROUP_DDRPKE_OFFSET 0x0758 +#define IMX_PADGROUP_TERM_CTL1_OFFSET 0x075c +#define IMX_PADGROUP_TERM_CTL2_OFFSET 0x0760 +#define IMX_PADGROUP_TERM_CTL3_OFFSET 0x0764 +#define IMX_PADGROUP_DDRPK_OFFSET 0x0768 +#define IMX_PADGROUP_TERM_CTL4_OFFSET 0x076c +#define IMX_PADGROUP_DDRHYS_OFFSET 0x0770 +#define IMX_PADGROUP_DDRMODE_OFFSET 0x0774 +#define IMX_PADGROUP_TERM_CTL5_OFFSET 0x0778 +#define IMX_PADGROUP_TERM_CTL6_OFFSET 0x077c +#define IMX_PADGROUP_TERM_CTL7_OFFSET 0x0780 +#define IMX_PADGROUP_B0DS_OFFSET 0x0784 +#define IMX_PADGROUP_B1DS_OFFSET 0x0788 +#define IMX_PADGROUP_CTLDS_OFFSET 0x078c +#define IMX_PADGROUP_DDR_TYPE_RGMII_OFFSET 0x0790 +#define IMX_PADGROUP_B2DS_OFFSET 0x0794 +#define IMX_PADGROUP_DDR_TYPE_OFFSET 0x0798 +#define IMX_PADGROUP_B3DS_OFFSET 0x079c +#define IMX_PADGROUP_B4DS_OFFSET 0x07a0 +#define IMX_PADGROUP_B5DS_OFFSET 0x07a4 +#define IMX_PADGROUP_B6DS_OFFSET 0x07a8 +#define IMX_PADGROUP_RGMII_TERM_OFFSET 0x07ac + +/* Select Input Registers */ + +#define IMX_INPUT_ASRC_ASRCK_CLOCK_6_OFFSET 0x07b0 +#define IMX_INPUT_AUD4_INPUT_DA_AMX_OFFSET 0x07b4 +#define IMX_INPUT_AUD4_INPUT_DB_AMX_OFFSET 0x07b8 +#define IMX_INPUT_AUD4_INPUT_RXCLK_AMX_OFFSET 0x07bc +#define IMX_INPUT_AUD4_INPUT_RXFS_AMX_OFFSET 0x07c0 +#define IMX_INPUT_AUD4_INPUT_TXCLK_AMX_OFFSET 0x07c4 +#define IMX_INPUT_AUD4_INPUT_TXFS_AMX_OFFSET 0x07c8 +#define IMX_INPUT_AUD5_INPUT_DA_AMX_OFFSET 0x07cc +#define IMX_INPUT_AUD5_INPUT_DB_AMX_OFFSET 0x07d0 +#define IMX_INPUT_AUD5_INPUT_RXCLK_AMX_OFFSET 0x07d4 +#define IMX_INPUT_AUD5_INPUT_RXFS_AMX_OFFSET 0x07d8 +#define IMX_INPUT_AUD5_INPUT_TXCLK_AMX_OFFSET 0x07dc +#define IMX_INPUT_AUD5_INPUT_TXFS_AMX_OFFSET 0x07e0 +#define IMX_INPUT_FLEXCAN1_RX_OFFSET 0x07e4 +#define IMX_INPUT_FLEXCAN2_RX_OFFSET 0x07e8 +#define IMX_INPUT_CCM_PMIC_READY_OFFSET 0x07e0 +#define IMX_INPUT_ECSPI1_CSPI_CLK_IN_OFFSET 0x07f4 +#define IMX_INPUT_ECSPI1_MISO_OFFSET 0x07f8 +#define IMX_INPUT_ECSPI1_MOSI_OFFSET 0x07fc +#define IMX_INPUT_ECSPI1_SS0_OFFSET 0x0800 +#define IMX_INPUT_ECSPI1_SS1_OFFSET 0x0804 +#define IMX_INPUT_ECSPI1_SS2_OFFSET 0x0808 +#define IMX_INPUT_ECSPI1_SS3_OFFSET 0x080c +#define IMX_INPUT_ECSPI2_CSPI_CLK_IN_OFFSET 0x0810 +#define IMX_INPUT_ECSPI2_MISO_OFFSET 0x0814 +#define IMX_INPUT_ECSPI2_MOSI_OFFSET 0x0818 +#define IMX_INPUT_ECSPI2_SS0_OFFSET 0x081c +#define IMX_INPUT_ECSPI2_SS1_OFFSET 0x0820 +#define IMX_INPUT_ECSPI4_SS0_OFFSET 0x0824 +#define IMX_INPUT_ECSPI5_CSPI_CLK_IN_OFFSET 0x0828 +#define IMX_INPUT_ECSPI5_MISO_OFFSET 0x082c +#define IMX_INPUT_ECSPI5_MOSI_OFFSET 0x0830 +#define IMX_INPUT_ECSPI5_SS0_OFFSET 0x0834 +#define IMX_INPUT_ECSPI5_SS1_OFFSET 0x0838 +#define IMX_INPUT_ENET_REF_CLK_OFFSET 0x083c +#define IMX_INPUT_ENET_MAC0_MDIO_OFFSET 0x0840 +#define IMX_INPUT_ENET_MAC0_RX_CLK_OFFSET 0x0844 +#define IMX_INPUT_ENET_MAC0_RX_DATA0_OFFSET 0x0848 +#define IMX_INPUT_ENET_MAC0_RX_DATA1_OFFSET 0x084c +#define IMX_INPUT_ENET_MAC0_RX_DATA2_OFFSET 0x0850 +#define IMX_INPUT_ENET_MAC0_RX_DATA3_OFFSET 0x0854 +#define IMX_INPUT_ENET_MAC0_RX_EN_OFFSET 0x0858 +#define IMX_INPUT_ESAI_RX_FS_OFFSET 0x085c +#define IMX_INPUT_ESAI_TX_FS_OFFSET 0x0860 +#define IMX_INPUT_ESAI_RX_HF_CLK_OFFSET 0x0864 +#define IMX_INPUT_ESAI_TX_HF_CLK_OFFSET 0x0868 +#define IMX_INPUT_ESAI_RX_CLK_OFFSET 0x086c +#define IMX_INPUT_ESAI_TX_CLK_OFFSET 0x0870 +#define IMX_INPUT_ESAI_SDO0_OFFSET 0x0874 +#define IMX_INPUT_ESAI_SDO1_OFFSET 0x0878 +#define IMX_INPUT_ESAI_SDO2_SDI3_OFFSET 0x087c +#define IMX_INPUT_ESAI_SDO3_SDI2_OFFSET 0x0880 +#define IMX_INPUT_ESAI_SDO4_SDI1_OFFSET 0x0884 +#define IMX_INPUT_ESAI_SDO5_SDI0_OFFSET 0x0888 +#define IMX_INPUT_HDMI_ICECIN_OFFSET 0x088c +#define IMX_INPUT_HDMI_II2C_CLKIN_OFFSET 0x0890 +#define IMX_INPUT_HDMI_II2C_DATAIN_OFFSET 0x0894 +#define IMX_INPUT_I2C1_SCL_IN_OFFSET 0x0898 +#define IMX_INPUT_I2C1_SDA_IN_OFFSET 0x089c +#define IMX_INPUT_I2C2_SCL_IN_OFFSET 0x08a0 +#define IMX_INPUT_I2C2_SDA_IN_OFFSET 0x08a4 +#define IMX_INPUT_I2C3_SCL_IN_OFFSET 0x08a8 +#define IMX_INPUT_I2C3_SDA_IN_OFFSET 0x08ac +#define IMX_INPUT_IPU2_SENS1_DATA10_OFFSET 0x08b0 +#define IMX_INPUT_IPU2_SENS1_DATA11_OFFSET 0x08b4 +#define IMX_INPUT_IPU2_SENS1_DATA12_OFFSET 0x08b8 +#define IMX_INPUT_IPU2_SENS1_DATA13_OFFSET 0x08bc +#define IMX_INPUT_IPU2_SENS1_DATA14_OFFSET 0x08c0 +#define IMX_INPUT_IPU2_SENS1_DATA15_OFFSET 0x08c4 +#define IMX_INPUT_IPU2_SENS1_DATA16_OFFSET 0x08c8 +#define IMX_INPUT_IPU2_SENS1_DATA17_OFFSET 0x08cc +#define IMX_INPUT_IPU2_SENS1_DATA18_OFFSET 0x08d0 +#define IMX_INPUT_IPU2_SENS1_DATA19_OFFSET 0x08d4 +#define IMX_INPUT_IPU2_SENS1_DATA_EN_OFFSET 0x08d8 +#define IMX_INPUT_IPU2_SENS1_HSYNC_OFFSET 0x08dc +#define IMX_INPUT_IPU2_SENS1_PIX_CLK_OFFSET 0x08e0 +#define IMX_INPUT_IPU2_SENS1_VSYNC_OFFSET 0x08e4 +#define IMX_INPUT_KEY_COL5_OFFSET 0x08e8 +#define IMX_INPUT_KEY_COL6_OFFSET 0x08ec +#define IMX_INPUT_KEY_COL7_OFFSET 0x08f0 +#define IMX_INPUT_KEY_ROW5_OFFSET 0x08f4 +#define IMX_INPUT_KEY_ROW6_OFFSET 0x08f8 +#define IMX_INPUT_KEY_ROW7_OFFSET 0x08fc +#define IMX_INPUT_MLB_MLB_CLK_IN_OFFSET 0x0900 +#define IMX_INPUT_MLB_MLB_DATA_IN_OFFSET 0x0904 +#define IMX_INPUT_MLB_MLB_SIG_IN_OFFSET 0x0908 +#define IMX_INPUT_SDMA_EVENTS14_OFFSET 0x090c +#define IMX_INPUT_SDMA_EVENTS47_OFFSET 0x0910 +#define IMX_INPUT_SPDIF_SPDIF_IN1_OFFSET 0x0914 +#define IMX_INPUT_SPDIF_TX_CLK2_OFFSET 0x0918 +#define IMX_INPUT_UART1_UART_RTS_B_OFFSET 0x091c +#define IMX_INPUT_UART1_UART_RX_DATA_OFFSET 0x0920 +#define IMX_INPUT_UART2_UART_RTS_B_OFFSET 0x0924 +#define IMX_INPUT_UART2_UART_RX_DATA_OFFSET 0x0928 +#define IMX_INPUT_UART3_UART_RTS_B_OFFSET 0x092c +#define IMX_INPUT_UART3_UART_RX_DATA_OFFSET 0x0930 +#define IMX_INPUT_UART4_UART_RTS_B_OFFSET 0x0934 +#define IMX_INPUT_UART4_UART_RX_DATA_OFFSET 0x0938 +#define IMX_INPUT_UART5_UART_RTS_B_OFFSET 0x093c +#define IMX_INPUT_UART5_UART_RX_DATA_OFFSET 0x0940 +#define IMX_INPUT_USB_OTG_OC_OFFSET 0x0944 +#define IMX_INPUT_USB_H1_OC_OFFSET 0x0948 +#define IMX_INPUT_USDHC1_WP_ON_OFFSET 0x094c + +/* IOMUXC Register Addresses ********************************************************/ +/* General Purpose Registers */ + +#define IMX_IOMUXC_GPR0 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR0_OFFSET) +#define IMX_IOMUXC_GPR1 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR1_OFFSET) +#define IMX_IOMUXC_GPR2 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR2_OFFSET) +#define IMX_IOMUXC_GPR3 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR3_OFFSET) +#define IMX_IOMUXC_GPR4 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR4_OFFSET) +#define IMX_IOMUXC_GPR5 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR5_OFFSET) +#define IMX_IOMUXC_GPR6 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR6_OFFSET) +#define IMX_IOMUXC_GPR7 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR7_OFFSET) +#define IMX_IOMUXC_GPR8 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR8_OFFSET) +#define IMX_IOMUXC_GPR9 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR9_OFFSET) +#define IMX_IOMUXC_GPR10 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR10_OFFSET) +#define IMX_IOMUXC_GPR11 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR11_OFFSET) +#define IMX_IOMUXC_GPR12 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR12_OFFSET) +#define IMX_IOMUXC_GPR13 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR13_OFFSET) + +/* Pad Mux Registers */ + +#define IMX_PADMUX_SD2_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA1_OFFSET) +#define IMX_PADMUX_SD2_DATA2 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA2_OFFSET) +#define IMX_PADMUX_SD2_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA0_OFFSET) +#define IMX_PADMUX_RGMII_TXC (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_TXC_OFFSET) +#define IMX_PADMUX_RGMII_TD0 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_TD0_OFFSET) +#define IMX_PADMUX_RGMII_TD1 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_TD1_OFFSET) +#define IMX_PADMUX_RGMII_TD2 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_TD2_OFFSET) +#define IMX_PADMUX_RGMII_TD3 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_TD3_OFFSET) +#define IMX_PADMUX_RGMII_RX_CTL (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_RX_CTL_OFFSET) +#define IMX_PADMUX_RGMII_RD0 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_RD0_OFFSET) +#define IMX_PADMUX_RGMII_TX_CTL (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_TX_CTL_OFFSET) +#define IMX_PADMUX_RGMII_RD1 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_RD1_OFFSET) +#define IMX_PADMUX_RGMII_RD2 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_RD2_OFFSET) +#define IMX_PADMUX_RGMII_RD3 (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_RD3_OFFSET) +#define IMX_PADMUX_RGMII_RXC (IMX_IOMUXC_VBASE+IMX_PADMUX_RGMII_RXC_OFFSET) +#define IMX_PADMUX_EIM_ADDR25 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR25_OFFSET) +#define IMX_PADMUX_EIM_EB2_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_EB2_B_OFFSET) +#define IMX_PADMUX_EIM_DATA16 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA16_OFFSET) +#define IMX_PADMUX_EIM_DATA17 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA17_OFFSET) +#define IMX_PADMUX_EIM_DATA18 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA18_OFFSET) +#define IMX_PADMUX_EIM_DATA19 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA19_OFFSET) +#define IMX_PADMUX_EIM_DATA20 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA20_OFFSET) +#define IMX_PADMUX_EIM_DATA21 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA21_OFFSET) +#define IMX_PADMUX_EIM_DATA22 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA22_OFFSET) +#define IMX_PADMUX_EIM_DATA23 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA23_OFFSET) +#define IMX_PADMUX_EIM_EB3_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_EB3_B_OFFSET) +#define IMX_PADMUX_EIM_DATA24 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA24_OFFSET) +#define IMX_PADMUX_EIM_DATA25 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA25_OFFSET) +#define IMX_PADMUX_EIM_DATA26 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA26_OFFSET) +#define IMX_PADMUX_EIM_DATA27 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA27_OFFSET) +#define IMX_PADMUX_EIM_DATA28 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA28_OFFSET) +#define IMX_PADMUX_EIM_DATA29 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA29_OFFSET) +#define IMX_PADMUX_EIM_DATA30 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA30_OFFSET) +#define IMX_PADMUX_EIM_DATA31 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_DATA31_OFFSET) +#define IMX_PADMUX_EIM_ADDR24 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR24_OFFSET) +#define IMX_PADMUX_EIM_ADDR23 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR23_OFFSET) +#define IMX_PADMUX_EIM_ADDR22 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR22_OFFSET) +#define IMX_PADMUX_EIM_ADDR21 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR21_OFFSET) +#define IMX_PADMUX_EIM_ADDR20 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR20_OFFSET) +#define IMX_PADMUX_EIM_ADDR19 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR19_OFFSET) +#define IMX_PADMUX_EIM_ADDR18 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR18_OFFSET) +#define IMX_PADMUX_EIM_ADDR17 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR17_OFFSET) +#define IMX_PADMUX_EIM_ADDR16 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_ADDR16_OFFSET) +#define IMX_PADMUX_EIM_CS0_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_CS0_B_OFFSET) +#define IMX_PADMUX_EIM_CS1_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_CS1_B_OFFSET) +#define IMX_PADMUX_EIM_OE_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_OE_B_OFFSET) +#define IMX_PADMUX_EIM_RW (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_RW_OFFSET) +#define IMX_PADMUX_EIM_LBA_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_LBA_B_OFFSET) +#define IMX_PADMUX_EIM_EB0_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_EB0_B_OFFSET) +#define IMX_PADMUX_EIM_EB1_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_EB1_B_OFFSET) +#define IMX_PADMUX_EIM_AD00 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD00_OFFSET) +#define IMX_PADMUX_EIM_AD01 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD01_OFFSET) +#define IMX_PADMUX_EIM_AD02 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD02_OFFSET) +#define IMX_PADMUX_EIM_AD03 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD03_OFFSET) +#define IMX_PADMUX_EIM_AD04 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD04_OFFSET) +#define IMX_PADMUX_EIM_AD05 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD05_OFFSET) +#define IMX_PADMUX_EIM_AD06 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD06_OFFSET) +#define IMX_PADMUX_EIM_AD07 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD07_OFFSET) +#define IMX_PADMUX_EIM_AD08 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD08_OFFSET) +#define IMX_PADMUX_EIM_AD09 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD09_OFFSET) +#define IMX_PADMUX_EIM_AD10 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD10_OFFSET) +#define IMX_PADMUX_EIM_AD11 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD11_OFFSET) +#define IMX_PADMUX_EIM_AD12 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD12_OFFSET) +#define IMX_PADMUX_EIM_AD13 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD13_OFFSET) +#define IMX_PADMUX_EIM_AD14 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD14_OFFSET) +#define IMX_PADMUX_EIM_AD15 (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_AD15_OFFSET) +#define IMX_PADMUX_EIM_WAIT_B (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_WAIT_B_OFFSET) +#define IMX_PADMUX_EIM_BCLK (IMX_IOMUXC_VBASE+IMX_PADMUX_EIM_BCLK_OFFSET) +#define IMX_PADMUX_DI0_DISP_CLK (IMX_IOMUXC_VBASE+IMX_PADMUX_DI0_DISP_CLK_OFFSET) +#define IMX_PADMUX_DI0_PIN15 (IMX_IOMUXC_VBASE+IMX_PADMUX_DI0_PIN15_OFFSET) +#define IMX_PADMUX_DI0_PIN02 (IMX_IOMUXC_VBASE+IMX_PADMUX_DI0_PIN02_OFFSET) +#define IMX_PADMUX_DI0_PIN03 (IMX_IOMUXC_VBASE+IMX_PADMUX_DI0_PIN03_OFFSET) +#define IMX_PADMUX_DI0_PIN04 (IMX_IOMUXC_VBASE+IMX_PADMUX_DI0_PIN04_OFFSET) +#define IMX_PADMUX_DISP0_DATA00 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA00_OFFSET) +#define IMX_PADMUX_DISP0_DATA01 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA01_OFFSET) +#define IMX_PADMUX_DISP0_DATA02 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA02_OFFSET) +#define IMX_PADMUX_DISP0_DATA03 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA03_OFFSET) +#define IMX_PADMUX_DISP0_DATA04 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA04_OFFSET) +#define IMX_PADMUX_DISP0_DATA05 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA05_OFFSET) +#define IMX_PADMUX_DISP0_DATA06 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA06_OFFSET) +#define IMX_PADMUX_DISP0_DATA07 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA07_OFFSET) +#define IMX_PADMUX_DISP0_DATA08 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA08_OFFSET) +#define IMX_PADMUX_DISP0_DATA09 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA09_OFFSET) +#define IMX_PADMUX_DISP0_DATA10 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA10_OFFSET) +#define IMX_PADMUX_DISP0_DATA11 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA11_OFFSET) +#define IMX_PADMUX_DISP0_DATA12 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA12_OFFSET) +#define IMX_PADMUX_DISP0_DATA13 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA13_OFFSET) +#define IMX_PADMUX_DISP0_DATA14 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA14_OFFSET) +#define IMX_PADMUX_DISP0_DATA15 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA15_OFFSET) +#define IMX_PADMUX_DISP0_DATA16 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA16_OFFSET) +#define IMX_PADMUX_DISP0_DATA17 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA17_OFFSET) +#define IMX_PADMUX_DISP0_DATA18 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA18_OFFSET) +#define IMX_PADMUX_DISP0_DATA19 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA19_OFFSET) +#define IMX_PADMUX_DISP0_DATA20 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA20_OFFSET) +#define IMX_PADMUX_DISP0_DATA21 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA21_OFFSET) +#define IMX_PADMUX_DISP0_DATA22 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA22_OFFSET) +#define IMX_PADMUX_DISP0_DATA23 (IMX_IOMUXC_VBASE+IMX_PADMUX_DISP0_DATA23_OFFSET) +#define IMX_PADMUX_ENET_MDIO (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_MDIO_OFFSET) +#define IMX_PADMUX_ENET_REF_CLK (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_REF_CLK_OFFSET) +#define IMX_PADMUX_ENET_RX_ER (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_RX_ER_OFFSET) +#define IMX_PADMUX_ENET_CRS_DV (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_CRS_DV_OFFSET) +#define IMX_PADMUX_ENET_RX_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_RX_DATA1_OFFSET) +#define IMX_PADMUX_ENET_RX_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_RX_DATA0_OFFSET) +#define IMX_PADMUX_ENET_TX_EN (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_TX_EN_OFFSET) +#define IMX_PADMUX_ENET_TX_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_TX_DATA1_OFFSET) +#define IMX_PADMUX_ENET_TX_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_TX_DATA0_OFFSET) +#define IMX_PADMUX_ENET_MDC (IMX_IOMUXC_VBASE+IMX_PADMUX_ENET_MDC_OFFSET) +#define IMX_PADMUX_KEY_COL0 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_COL0_OFFSET) +#define IMX_PADMUX_KEY_ROW0 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_ROW0_OFFSET) +#define IMX_PADMUX_KEY_COL1 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_COL1_OFFSET) +#define IMX_PADMUX_KEY_ROW1 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_ROW1_OFFSET) +#define IMX_PADMUX_KEY_COL2 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_COL2_OFFSET) +#define IMX_PADMUX_KEY_ROW2 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_ROW2_OFFSET) +#define IMX_PADMUX_KEY_COL3 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_COL3_OFFSET) +#define IMX_PADMUX_KEY_ROW3 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_ROW3_OFFSET) +#define IMX_PADMUX_KEY_COL4 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_COL4_OFFSET) +#define IMX_PADMUX_KEY_ROW4 (IMX_IOMUXC_VBASE+IMX_PADMUX_KEY_ROW4_OFFSET) +#define IMX_PADMUX_GPIO00 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO00_OFFSET) +#define IMX_PADMUX_GPIO01 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO01_OFFSET) +#define IMX_PADMUX_GPIO09 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO09_OFFSET) +#define IMX_PADMUX_GPIO03 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO03_OFFSET) +#define IMX_PADMUX_GPIO06 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO06_OFFSET) +#define IMX_PADMUX_GPIO02 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO02_OFFSET) +#define IMX_PADMUX_GPIO04 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO04_OFFSET) +#define IMX_PADMUX_GPIO05 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO05_OFFSET) +#define IMX_PADMUX_GPIO07 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO07_OFFSET) +#define IMX_PADMUX_GPIO08 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO08_OFFSET) +#define IMX_PADMUX_GPIO16 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO16_OFFSET) +#define IMX_PADMUX_GPIO17 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO17_OFFSET) +#define IMX_PADMUX_GPIO18 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO18_OFFSET) +#define IMX_PADMUX_GPIO19 (IMX_IOMUXC_VBASE+IMX_PADMUX_GPIO19_OFFSET) +#define IMX_PADMUX_CSI0_PIXCLK (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_PIXCLK_OFFSET) +#define IMX_PADMUX_CSI0_HSYNC (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_HSYNC_OFFSET) +#define IMX_PADMUX_CSI0_DATA_EN (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA_EN_OFFSET) +#define IMX_PADMUX_CSI0_VSYNC (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_VSYNC_OFFSET) +#define IMX_PADMUX_CSI0_DATA04 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA04_OFFSET) +#define IMX_PADMUX_CSI0_DATA05 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA05_OFFSET) +#define IMX_PADMUX_CSI0_DATA06 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA06_OFFSET) +#define IMX_PADMUX_CSI0_DATA07 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA07_OFFSET) +#define IMX_PADMUX_CSI0_DATA08 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA08_OFFSET) +#define IMX_PADMUX_CSI0_DATA09 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA09_OFFSET) +#define IMX_PADMUX_CSI0_DATA10 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA10_OFFSET) +#define IMX_PADMUX_CSI0_DATA11 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA11_OFFSET) +#define IMX_PADMUX_CSI0_DATA12 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA12_OFFSET) +#define IMX_PADMUX_CSI0_DATA13 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA13_OFFSET) +#define IMX_PADMUX_CSI0_DATA14 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA14_OFFSET) +#define IMX_PADMUX_CSI0_DATA15 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA15_OFFSET) +#define IMX_PADMUX_CSI0_DATA16 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA16_OFFSET) +#define IMX_PADMUX_CSI0_DATA17 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA17_OFFSET) +#define IMX_PADMUX_CSI0_DATA18 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA18_OFFSET) +#define IMX_PADMUX_CSI0_DATA19 (IMX_IOMUXC_VBASE+IMX_PADMUX_CSI0_DATA19_OFFSET) +#define IMX_PADMUX_SD3_DATA7 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA7_OFFSET) +#define IMX_PADMUX_SD3_DATA6 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA6_OFFSET) +#define IMX_PADMUX_SD3_DATA5 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA5_OFFSET) +#define IMX_PADMUX_SD3_DATA4 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA4_OFFSET) +#define IMX_PADMUX_SD3_CMD (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_CMD_OFFSET) +#define IMX_PADMUX_SD3_CLK (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_CLK_OFFSET) +#define IMX_PADMUX_SD3_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA0_OFFSET) +#define IMX_PADMUX_SD3_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA1_OFFSET) +#define IMX_PADMUX_SD3_DATA2 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA2_OFFSET) +#define IMX_PADMUX_SD3_DATA3 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_DATA3_OFFSET) +#define IMX_PADMUX_SD3_RESET (IMX_IOMUXC_VBASE+IMX_PADMUX_SD3_RESET_OFFSET) +#define IMX_PADMUX_NAND_CLE (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_CLE_OFFSET) +#define IMX_PADMUX_NAND_ALE (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_ALE_OFFSET) +#define IMX_PADMUX_NAND_WP_B (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_WP_B_OFFSET) +#define IMX_PADMUX_NAND_READY_B (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_READY_B_OFFSET) +#define IMX_PADMUX_NAND_CS0_B (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_CS0_B_OFFSET) +#define IMX_PADMUX_NAND_CS1_B (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_CS1_B_OFFSET) +#define IMX_PADMUX_NAND_CS2_B (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_CS2_B_OFFSET) +#define IMX_PADMUX_NAND_CS3_B (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_CS3_B_OFFSET) +#define IMX_PADMUX_SD4_CMD (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_CMD_OFFSET) +#define IMX_PADMUX_SD4_CLK (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_CLK_OFFSET) +#define IMX_PADMUX_NAND_DATA00 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA00_OFFSET) +#define IMX_PADMUX_NAND_DATA01 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA01_OFFSET) +#define IMX_PADMUX_NAND_DATA02 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA02_OFFSET) +#define IMX_PADMUX_NAND_DATA03 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA03_OFFSET) +#define IMX_PADMUX_NAND_DATA04 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA04_OFFSET) +#define IMX_PADMUX_NAND_DATA05 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA05_OFFSET) +#define IMX_PADMUX_NAND_DATA06 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA06_OFFSET) +#define IMX_PADMUX_NAND_DATA07 (IMX_IOMUXC_VBASE+IMX_PADMUX_NAND_DATA07_OFFSET) +#define IMX_PADMUX_SD4_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA0_OFFSET) +#define IMX_PADMUX_SD4_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA1_OFFSET) +#define IMX_PADMUX_SD4_DATA2 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA2_OFFSET) +#define IMX_PADMUX_SD4_DATA3 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA3_OFFSET) +#define IMX_PADMUX_SD4_DATA4 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA4_OFFSET) +#define IMX_PADMUX_SD4_DATA5 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA5_OFFSET) +#define IMX_PADMUX_SD4_DATA6 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA6_OFFSET) +#define IMX_PADMUX_SD4_DATA7 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD4_DATA7_OFFSET) +#define IMX_PADMUX_SD1_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD1_DATA1_OFFSET) +#define IMX_PADMUX_SD1_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD1_DATA0_OFFSET) +#define IMX_PADMUX_SD1_DATA3 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD1_DATA3_OFFSET) +#define IMX_PADMUX_SD1_CMD (IMX_IOMUXC_VBASE+IMX_PADMUX_SD1_CMD_OFFSET) +#define IMX_PADMUX_SD1_DATA2 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD1_DATA2_OFFSET) +#define IMX_PADMUX_SD1_CLK (IMX_IOMUXC_VBASE+IMX_PADMUX_SD1_CLK_OFFSET) +#define IMX_PADMUX_SD2_CLK (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_CLK_OFFSET) +#define IMX_PADMUX_SD2_CMD (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_CMD_OFFSET) +#define IMX_PADMUX_SD2_DATA3 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA3_OFFSET) + +/* Pad Control Registers */ + +#define IMX_PADCTL_SD2_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA1_OFFSET) +#define IMX_PADCTL_SD2_DATA2 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA2_OFFSET) +#define IMX_PADCTL_SD2_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA0_OFFSET) +#define IMX_PADCTL_RGMII_TXC (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_TXC_OFFSET) +#define IMX_PADCTL_RGMII_TD0 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_TD0_OFFSET) +#define IMX_PADCTL_RGMII_TD1 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_TD1_OFFSET) +#define IMX_PADCTL_RGMII_TD2 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_TD2_OFFSET) +#define IMX_PADCTL_RGMII_TD3 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_TD3_OFFSET) +#define IMX_PADCTL_RGMII_RX_CTL (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_RX_CTL_OFFSET) +#define IMX_PADCTL_RGMII_RD0 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_RD0_OFFSET) +#define IMX_PADCTL_RGMII_TX_CTL (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_TX_CTL_OFFSET) +#define IMX_PADCTL_RGMII_RD1 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_RD1_OFFSET) +#define IMX_PADCTL_RGMII_RD2 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_RD2_OFFSET) +#define IMX_PADCTL_RGMII_RD3 (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_RD3_OFFSET) +#define IMX_PADCTL_RGMII_RXC (IMX_IOMUXC_VBASE+IMX_PADCTL_RGMII_RXC_OFFSET) +#define IMX_PADCTL_EIM_ADDR25 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR25_OFFSET) +#define IMX_PADCTL_EIM_EB2_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_EB2_B_OFFSET) +#define IMX_PADCTL_EIM_DATA16 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA16_OFFSET) +#define IMX_PADCTL_EIM_DATA17 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA17_OFFSET) +#define IMX_PADCTL_EIM_DATA18 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA18_OFFSET) +#define IMX_PADCTL_EIM_DATA19 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA19_OFFSET) +#define IMX_PADCTL_EIM_DATA20 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA20_OFFSET) +#define IMX_PADCTL_EIM_DATA21 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA21_OFFSET) +#define IMX_PADCTL_EIM_DATA22 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA22_OFFSET) +#define IMX_PADCTL_EIM_DATA23 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA23_OFFSET) +#define IMX_PADCTL_EIM_EB3_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_EB3_B_OFFSET) +#define IMX_PADCTL_EIM_DATA24 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA24_OFFSET) +#define IMX_PADCTL_EIM_DATA25 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA25_OFFSET) +#define IMX_PADCTL_EIM_DATA26 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA26_OFFSET) +#define IMX_PADCTL_EIM_DATA27 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA27_OFFSET) +#define IMX_PADCTL_EIM_DATA28 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA28_OFFSET) +#define IMX_PADCTL_EIM_DATA29 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA29_OFFSET) +#define IMX_PADCTL_EIM_DATA30 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA30_OFFSET) +#define IMX_PADCTL_EIM_DATA31 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_DATA31_OFFSET) +#define IMX_PADCTL_EIM_ADDR24 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR24_OFFSET) +#define IMX_PADCTL_EIM_ADDR23 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR23_OFFSET) +#define IMX_PADCTL_EIM_ADDR22 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR22_OFFSET) +#define IMX_PADCTL_EIM_ADDR21 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR21_OFFSET) +#define IMX_PADCTL_EIM_ADDR20 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR20_OFFSET) +#define IMX_PADCTL_EIM_ADDR19 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR19_OFFSET) +#define IMX_PADCTL_EIM_ADDR18 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR18_OFFSET) +#define IMX_PADCTL_EIM_ADDR17 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR17_OFFSET) +#define IMX_PADCTL_EIM_ADDR16 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_ADDR16_OFFSET) +#define IMX_PADCTL_EIM_CS0_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_CS0_B_OFFSET) +#define IMX_PADCTL_EIM_CS1_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_CS1_B_OFFSET) +#define IMX_PADCTL_EIM_OE_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_OE_B_OFFSET) +#define IMX_PADCTL_EIM_RW (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_RW_OFFSET) +#define IMX_PADCTL_EIM_LBA_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_LBA_B_OFFSET) +#define IMX_PADCTL_EIM_EB0_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_EB0_B_OFFSET) +#define IMX_PADCTL_EIM_EB1_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_EB1_B_OFFSET) +#define IMX_PADCTL_EIM_AD00 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD00_OFFSET) +#define IMX_PADCTL_EIM_AD01 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD01_OFFSET) +#define IMX_PADCTL_EIM_AD02 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD02_OFFSET) +#define IMX_PADCTL_EIM_AD03 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD03_OFFSET) +#define IMX_PADCTL_EIM_AD04 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD04_OFFSET) +#define IMX_PADCTL_EIM_AD05 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD05_OFFSET) +#define IMX_PADCTL_EIM_AD06 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD06_OFFSET) +#define IMX_PADCTL_EIM_AD07 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD07_OFFSET) +#define IMX_PADCTL_EIM_AD08 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD08_OFFSET) +#define IMX_PADCTL_EIM_AD09 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD09_OFFSET) +#define IMX_PADCTL_EIM_AD10 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD10_OFFSET) +#define IMX_PADCTL_EIM_AD11 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD11_OFFSET) +#define IMX_PADCTL_EIM_AD12 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD12_OFFSET) +#define IMX_PADCTL_EIM_AD13 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD13_OFFSET) +#define IMX_PADCTL_EIM_AD14 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD14_OFFSET) +#define IMX_PADCTL_EIM_AD15 (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_AD15_OFFSET) +#define IMX_PADCTL_EIM_WAIT_B (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_WAIT_B_OFFSET) +#define IMX_PADCTL_EIM_BCLK (IMX_IOMUXC_VBASE+IMX_PADCTL_EIM_BCLK_OFFSET) +#define IMX_PADCTL_DI0_DISP_CLK (IMX_IOMUXC_VBASE+IMX_PADCTL_DI0_DISP_CLK_OFFSET) +#define IMX_PADCTL_DI0_PIN15 (IMX_IOMUXC_VBASE+IMX_PADCTL_DI0_PIN15_OFFSET) +#define IMX_PADCTL_DI0_PIN02 (IMX_IOMUXC_VBASE+IMX_PADCTL_DI0_PIN02_OFFSET) +#define IMX_PADCTL_DI0_PIN03 (IMX_IOMUXC_VBASE+IMX_PADCTL_DI0_PIN03_OFFSET) +#define IMX_PADCTL_DI0_PIN04 (IMX_IOMUXC_VBASE+IMX_PADCTL_DI0_PIN04_OFFSET) +#define IMX_PADCTL_DISP0_DATA00 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA00_OFFSET) +#define IMX_PADCTL_DISP0_DATA01 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA01_OFFSET) +#define IMX_PADCTL_DISP0_DATA02 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA02_OFFSET) +#define IMX_PADCTL_DISP0_DATA03 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA03_OFFSET) +#define IMX_PADCTL_DISP0_DATA04 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA04_OFFSET) +#define IMX_PADCTL_DISP0_DATA05 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA05_OFFSET) +#define IMX_PADCTL_DISP0_DATA06 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA06_OFFSET) +#define IMX_PADCTL_DISP0_DATA07 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA07_OFFSET) +#define IMX_PADCTL_DISP0_DATA08 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA08_OFFSET) +#define IMX_PADCTL_DISP0_DATA09 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA09_OFFSET) +#define IMX_PADCTL_DISP0_DATA10 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA10_OFFSET) +#define IMX_PADCTL_DISP0_DATA11 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA11_OFFSET) +#define IMX_PADCTL_DISP0_DATA12 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA12_OFFSET) +#define IMX_PADCTL_DISP0_DATA13 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA13_OFFSET) +#define IMX_PADCTL_DISP0_DATA14 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA14_OFFSET) +#define IMX_PADCTL_DISP0_DATA15 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA15_OFFSET) +#define IMX_PADCTL_DISP0_DATA16 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA16_OFFSET) +#define IMX_PADCTL_DISP0_DATA17 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA17_OFFSET) +#define IMX_PADCTL_DISP0_DATA18 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA18_OFFSET) +#define IMX_PADCTL_DISP0_DATA19 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA19_OFFSET) +#define IMX_PADCTL_DISP0_DATA20 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA20_OFFSET) +#define IMX_PADCTL_DISP0_DATA21 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA21_OFFSET) +#define IMX_PADCTL_DISP0_DATA22 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA22_OFFSET) +#define IMX_PADCTL_DISP0_DATA23 (IMX_IOMUXC_VBASE+IMX_PADCTL_DISP0_DATA23_OFFSET) +#define IMX_PADCTL_ENET_MDIO (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_MDIO_OFFSET) +#define IMX_PADCTL_ENET_REF_CLK (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_REF_CLK_OFFSET) +#define IMX_PADCTL_ENET_RX_ER (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_RX_ER_OFFSET) +#define IMX_PADCTL_ENET_CRS_DV (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_CRS_DV_OFFSET) +#define IMX_PADCTL_ENET_RX_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_RX_DATA1_OFFSET) +#define IMX_PADCTL_ENET_RX_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_RX_DATA0_OFFSET) +#define IMX_PADCTL_ENET_TX_EN (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_TX_EN_OFFSET) +#define IMX_PADCTL_ENET_TX_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_TX_DATA1_OFFSET) +#define IMX_PADCTL_ENET_TX_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_TX_DATA0_OFFSET) +#define IMX_PADCTL_ENET_MDC (IMX_IOMUXC_VBASE+IMX_PADCTL_ENET_MDC_OFFSET) +#define IMX_PADCTL_DRAM_SDQS5_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS5_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM5 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM5_OFFSET) +#define IMX_PADCTL_DRAM_DQM4 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM4_OFFSET) +#define IMX_PADCTL_DRAM_SDQS4_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS4_P_OFFSET) +#define IMX_PADCTL_DRAM_SDQS3_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS3_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM3 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM3_OFFSET) +#define IMX_PADCTL_DRAM_SDQS2_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS2_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM2 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM2_OFFSET) +#define IMX_PADCTL_DRAM_ADDR00 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR00_OFFSET) +#define IMX_PADCTL_DRAM_ADDR01 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR01_OFFSET) +#define IMX_PADCTL_DRAM_ADDR02 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR02_OFFSET) +#define IMX_PADCTL_DRAM_ADDR03 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR03_OFFSET) +#define IMX_PADCTL_DRAM_ADDR04 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR04_OFFSET) +#define IMX_PADCTL_DRAM_ADDR05 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR05_OFFSET) +#define IMX_PADCTL_DRAM_ADDR06 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR06_OFFSET) +#define IMX_PADCTL_DRAM_ADDR07 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR07_OFFSET) +#define IMX_PADCTL_DRAM_ADDR08 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR08_OFFSET) +#define IMX_PADCTL_DRAM_ADDR09 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR09_OFFSET) +#define IMX_PADCTL_DRAM_ADDR10 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR10_OFFSET) +#define IMX_PADCTL_DRAM_ADDR11 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR11_OFFSET) +#define IMX_PADCTL_DRAM_ADDR12 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR12_OFFSET) +#define IMX_PADCTL_DRAM_ADDR13 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR13_OFFSET) +#define IMX_PADCTL_DRAM_ADDR14 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR14_OFFSET) +#define IMX_PADCTL_DRAM_ADDR15 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ADDR15_OFFSET) +#define IMX_PADCTL_DRAM_CAS_B (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_CAS_B_OFFSET) +#define IMX_PADCTL_DRAM_CS0_B (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_CS0_B_OFFSET) +#define IMX_PADCTL_DRAM_CS1_B (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_CS1_B_OFFSET) +#define IMX_PADCTL_DRAM_RAS_B (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_RAS_B_OFFSET) +#define IMX_PADCTL_DRAM_RESET (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_RESET_OFFSET) +#define IMX_PADCTL_DRAM_SDBA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDBA0_OFFSET) +#define IMX_PADCTL_DRAM_SDBA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDBA1_OFFSET) +#define IMX_PADCTL_DRAM_SDCLK0_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDCLK0_P_OFFSET) +#define IMX_PADCTL_DRAM_SDBA2 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDBA2_OFFSET) +#define IMX_PADCTL_DRAM_SDCKE0 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDCKE0_OFFSET) +#define IMX_PADCTL_DRAM_SDCLK1_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDCLK1_P_OFFSET) +#define IMX_PADCTL_DRAM_SDCKE1 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDCKE1_OFFSET) +#define IMX_PADCTL_DRAM_ODT0 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ODT0_OFFSET) +#define IMX_PADCTL_DRAM_ODT1 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_ODT1_OFFSET) +#define IMX_PADCTL_DRAM_SDWE_B (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDWE_B_OFFSET) +#define IMX_PADCTL_DRAM_SDQS0_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS0_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM0 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM0_OFFSET) +#define IMX_PADCTL_DRAM_SDQS1_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS1_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM1 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM1_OFFSET) +#define IMX_PADCTL_DRAM_SDQS6_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS6_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM6 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM6_OFFSET) +#define IMX_PADCTL_DRAM_SDQS7_P (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_SDQS7_P_OFFSET) +#define IMX_PADCTL_DRAM_DQM7 (IMX_IOMUXC_VBASE+IMX_PADCTL_DRAM_DQM7_OFFSET) +#define IMX_PADCTL_KEY_COL0 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_COL0_OFFSET) +#define IMX_PADCTL_KEY_ROW0 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_ROW0_OFFSET) +#define IMX_PADCTL_KEY_COL1 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_COL1_OFFSET) +#define IMX_PADCTL_KEY_ROW1 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_ROW1_OFFSET) +#define IMX_PADCTL_KEY_COL2 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_COL2_OFFSET) +#define IMX_PADCTL_KEY_ROW2 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_ROW2_OFFSET) +#define IMX_PADCTL_KEY_COL3 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_COL3_OFFSET) +#define IMX_PADCTL_KEY_ROW3 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_ROW3_OFFSET) +#define IMX_PADCTL_KEY_COL4 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_COL4_OFFSET) +#define IMX_PADCTL_KEY_ROW4 (IMX_IOMUXC_VBASE+IMX_PADCTL_KEY_ROW4_OFFSET) +#define IMX_PADCTL_GPIO00 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO00_OFFSET) +#define IMX_PADCTL_GPIO01 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO01_OFFSET) +#define IMX_PADCTL_GPIO09 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO09_OFFSET) +#define IMX_PADCTL_GPIO03 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO03_OFFSET) +#define IMX_PADCTL_GPIO06 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO06_OFFSET) +#define IMX_PADCTL_GPIO02 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO02_OFFSET) +#define IMX_PADCTL_GPIO04 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO04_OFFSET) +#define IMX_PADCTL_GPIO05 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO05_OFFSET) +#define IMX_PADCTL_GPIO07 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO07_OFFSET) +#define IMX_PADCTL_GPIO08 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO08_OFFSET) +#define IMX_PADCTL_GPIO16 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO16_OFFSET) +#define IMX_PADCTL_GPIO17 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO17_OFFSET) +#define IMX_PADCTL_GPIO18 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO18_OFFSET) +#define IMX_PADCTL_GPIO19 (IMX_IOMUXC_VBASE+IMX_PADCTL_GPIO19_OFFSET) +#define IMX_PADCTL_CSI0_PIXCLK (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_PIXCLK_OFFSET) +#define IMX_PADCTL_CSI0_HSYNC (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_HSYNC_OFFSET) +#define IMX_PADCTL_CSI0_DATA_EN (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA_EN_OFFSET) +#define IMX_PADCTL_CSI0_VSYNC (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_VSYNC_OFFSET) +#define IMX_PADCTL_CSI0_DATA04 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA04_OFFSET) +#define IMX_PADCTL_CSI0_DATA05 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA05_OFFSET) +#define IMX_PADCTL_CSI0_DATA06 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA06_OFFSET) +#define IMX_PADCTL_CSI0_DATA07 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA07_OFFSET) +#define IMX_PADCTL_CSI0_DATA08 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA08_OFFSET) +#define IMX_PADCTL_CSI0_DATA09 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA09_OFFSET) +#define IMX_PADCTL_CSI0_DATA10 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA10_OFFSET) +#define IMX_PADCTL_CSI0_DATA11 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA11_OFFSET) +#define IMX_PADCTL_CSI0_DATA12 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA12_OFFSET) +#define IMX_PADCTL_CSI0_DATA13 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA13_OFFSET) +#define IMX_PADCTL_CSI0_DATA14 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA14_OFFSET) +#define IMX_PADCTL_CSI0_DATA15 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA15_OFFSET) +#define IMX_PADCTL_CSI0_DATA16 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA16_OFFSET) +#define IMX_PADCTL_CSI0_DATA17 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA17_OFFSET) +#define IMX_PADCTL_CSI0_DATA18 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA18_OFFSET) +#define IMX_PADCTL_CSI0_DATA19 (IMX_IOMUXC_VBASE+IMX_PADCTL_CSI0_DATA19_OFFSET) +#define IMX_PADCTL_JTAG_TMS (IMX_IOMUXC_VBASE+IMX_PADCTL_JTAG_TMS_OFFSET) +#define IMX_PADCTL_JTAG_MOD (IMX_IOMUXC_VBASE+IMX_PADCTL_JTAG_MOD_OFFSET) +#define IMX_PADCTL_JTAG_TRSTB (IMX_IOMUXC_VBASE+IMX_PADCTL_JTAG_TRSTB_OFFSET) +#define IMX_PADCTL_JTAG_TDI (IMX_IOMUXC_VBASE+IMX_PADCTL_JTAG_TDI_OFFSET) +#define IMX_PADCTL_JTAG_TCK (IMX_IOMUXC_VBASE+IMX_PADCTL_JTAG_TCK_OFFSET) +#define IMX_PADCTL_JTAG_TDO (IMX_IOMUXC_VBASE+IMX_PADCTL_JTAG_TDO_OFFSET) +#define IMX_PADCTL_SD3_DATA7 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA7_OFFSET) +#define IMX_PADCTL_SD3_DATA6 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA6_OFFSET) +#define IMX_PADCTL_SD3_DATA5 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA5_OFFSET) +#define IMX_PADCTL_SD3_DATA4 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA4_OFFSET) +#define IMX_PADCTL_SD3_CMD (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_CMD_OFFSET) +#define IMX_PADCTL_SD3_CLK (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_CLK_OFFSET) +#define IMX_PADCTL_SD3_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA0_OFFSET) +#define IMX_PADCTL_SD3_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA1_OFFSET) +#define IMX_PADCTL_SD3_DATA2 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA2_OFFSET) +#define IMX_PADCTL_SD3_DATA3 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_DATA3_OFFSET) +#define IMX_PADCTL_SD3_RESET (IMX_IOMUXC_VBASE+IMX_PADCTL_SD3_RESET_OFFSET) +#define IMX_PADCTL_NAND_CLE (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_CLE_OFFSET) +#define IMX_PADCTL_NAND_ALE (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_ALE_OFFSET) +#define IMX_PADCTL_NAND_WP_B (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_WP_B_OFFSET) +#define IMX_PADCTL_NAND_READY_B (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_READY_B_OFFSET) +#define IMX_PADCTL_NAND_CS0_B (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_CS0_B_OFFSET) +#define IMX_PADCTL_NAND_CS1_B (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_CS1_B_OFFSET) +#define IMX_PADCTL_NAND_CS2_B (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_CS2_B_OFFSET) +#define IMX_PADCTL_NAND_CS3_B (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_CS3_B_OFFSET) +#define IMX_PADCTL_SD4_CMD (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_CMD_OFFSET) +#define IMX_PADCTL_SD4_CLK (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_CLK_OFFSET) +#define IMX_PADCTL_NAND_DATA00 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA00_OFFSET) +#define IMX_PADCTL_NAND_DATA01 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA01_OFFSET) +#define IMX_PADCTL_NAND_DATA02 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA02_OFFSET) +#define IMX_PADCTL_NAND_DATA03 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA03_OFFSET) +#define IMX_PADCTL_NAND_DATA04 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA04_OFFSET) +#define IMX_PADCTL_NAND_DATA05 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA05_OFFSET) +#define IMX_PADCTL_NAND_DATA06 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA06_OFFSET) +#define IMX_PADCTL_NAND_DATA07 (IMX_IOMUXC_VBASE+IMX_PADCTL_NAND_DATA07_OFFSET) +#define IMX_PADCTL_SD4_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA0_OFFSET) +#define IMX_PADCTL_SD4_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA1_OFFSET) +#define IMX_PADCTL_SD4_DATA2 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA2_OFFSET) +#define IMX_PADCTL_SD4_DATA3 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA3_OFFSET) +#define IMX_PADCTL_SD4_DATA4 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA4_OFFSET) +#define IMX_PADCTL_SD4_DATA5 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA5_OFFSET) +#define IMX_PADCTL_SD4_DATA6 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA6_OFFSET) +#define IMX_PADCTL_SD4_DATA7 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD4_DATA7_OFFSET) +#define IMX_PADCTL_SD1_DATA1 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD1_DATA1_OFFSET) +#define IMX_PADCTL_SD1_DATA0 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD1_DATA0_OFFSET) +#define IMX_PADCTL_SD1_DATA3 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD1_DATA3_OFFSET) +#define IMX_PADCTL_SD1_CMD (IMX_IOMUXC_VBASE+IMX_PADCTL_SD1_CMD_OFFSET) +#define IMX_PADCTL_SD1_DATA2 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD1_DATA2_OFFSET) +#define IMX_PADCTL_SD1_CLK (IMX_IOMUXC_VBASE+IMX_PADCTL_SD1_CLK_OFFSET) +#define IMX_PADCTL_SD2_CLK (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_CLK_OFFSET) +#define IMX_PADCTL_SD2_CMD (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_CMD_OFFSET) +#define IMX_PADCTL_SD2_DATA3 (IMX_IOMUXC_VBASE+IMX_PADCTL_SD2_DATA3_OFFSET) + +/* Pad Group Control Registers */ + +#define IMX_PADGROUP_B7DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B7DS_OFFSET) +#define IMX_PADGROUP_ADDDS (IMX_IOMUXC_VBASE+IMX_PADGROUP_ADDDS_OFFSET) +#define IMX_PADGROUP_DDRMODE_CTL (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDRMODE_CTL_OFFSET) +#define IMX_PADGROUP_TERM_CTL0 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL0_OFFSET) +#define IMX_PADGROUP_DDRPKE (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDRPKE_OFFSET) +#define IMX_PADGROUP_TERM_CTL1 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL1_OFFSET) +#define IMX_PADGROUP_TERM_CTL2 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL2_OFFSET) +#define IMX_PADGROUP_TERM_CTL3 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL3_OFFSET) +#define IMX_PADGROUP_DDRPK (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDRPK_OFFSET) +#define IMX_PADGROUP_TERM_CTL4 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL4_OFFSET) +#define IMX_PADGROUP_DDRHYS (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDRHYS_OFFSET) +#define IMX_PADGROUP_DDRMODE (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDRMODE_OFFSET) +#define IMX_PADGROUP_TERM_CTL5 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL5_OFFSET) +#define IMX_PADGROUP_TERM_CTL6 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL6_OFFSET) +#define IMX_PADGROUP_TERM_CTL7 (IMX_IOMUXC_VBASE+IMX_PADGROUP_TERM_CTL7_OFFSET) +#define IMX_PADGROUP_B0DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B0DS_OFFSET) +#define IMX_PADGROUP_B1DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B1DS_OFFSET) +#define IMX_PADGROUP_CTLDS (IMX_IOMUXC_VBASE+IMX_PADGROUP_CTLDS_OFFSET) +#define IMX_PADGROUP_DDR_TYPE_RGMII (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDR_TYPE_RGMII_OFFSET) +#define IMX_PADGROUP_B2DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B2DS_OFFSET) +#define IMX_PADGROUP_DDR_TYPE (IMX_IOMUXC_VBASE+IMX_PADGROUP_DDR_TYPE_OFFSET) +#define IMX_PADGROUP_B3DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B3DS_OFFSET) +#define IMX_PADGROUP_B4DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B4DS_OFFSET) +#define IMX_PADGROUP_B5DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B5DS_OFFSET) +#define IMX_PADGROUP_B6DS (IMX_IOMUXC_VBASE+IMX_PADGROUP_B6DS_OFFSET) +#define IMX_PADGROUP_RGMII_TERM (IMX_IOMUXC_VBASE+IMX_PADGROUP_RGMII_TERM_OFFSET) + +/* Select Input Registers */ + +#define IMX_INPUT_ASRC_ASRCK_CLOCK_6 (IMX_IOMUXC_VBASE+IMX_INPUT_ASRC_ASRCK_CLOCK_6_OFFSET) +#define IMX_INPUT_AUD4_INPUT_DA_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD4_INPUT_DA_AMX_OFFSET) +#define IMX_INPUT_AUD4_INPUT_DB_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD4_INPUT_DB_AMX_OFFSET) +#define IMX_INPUT_AUD4_INPUT_RXCLK_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD4_INPUT_RXCLK_AMX_OFFSET) +#define IMX_INPUT_AUD4_INPUT_RXFS_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD4_INPUT_RXFS_AMX_OFFSET) +#define IMX_INPUT_AUD4_INPUT_TXCLK_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD4_INPUT_TXCLK_AMX_OFFSET) +#define IMX_INPUT_AUD4_INPUT_TXFS_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD4_INPUT_TXFS_AMX_OFFSET) +#define IMX_INPUT_AUD5_INPUT_DA_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD5_INPUT_DA_AMX_OFFSET) +#define IMX_INPUT_AUD5_INPUT_DB_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD5_INPUT_DB_AMX_OFFSET) +#define IMX_INPUT_AUD5_INPUT_RXCLK_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD5_INPUT_RXCLK_AMX_OFFSET) +#define IMX_INPUT_AUD5_INPUT_RXFS_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD5_INPUT_RXFS_AMX_OFFSET) +#define IMX_INPUT_AUD5_INPUT_TXCLK_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD5_INPUT_TXCLK_AMX_OFFSET) +#define IMX_INPUT_AUD5_INPUT_TXFS_AMX (IMX_IOMUXC_VBASE+IMX_INPUT_AUD5_INPUT_TXFS_AMX_OFFSET) +#define IMX_INPUT_FLEXCAN1_RX (IMX_IOMUXC_VBASE+IMX_INPUT_FLEXCAN1_RX_OFFSET) +#define IMX_INPUT_FLEXCAN2_RX (IMX_IOMUXC_VBASE+IMX_INPUT_FLEXCAN2_RX_OFFSET) +#define IMX_INPUT_CCM_PMIC_READY (IMX_IOMUXC_VBASE+IMX_INPUT_CCM_PMIC_READY_OFFSET) +#define IMX_INPUT_ECSPI1_CSPI_CLK_IN (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_CSPI_CLK_IN_OFFSET) +#define IMX_INPUT_ECSPI1_MISO (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_MISO_OFFSET) +#define IMX_INPUT_ECSPI1_MOSI (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_MOSI_OFFSET) +#define IMX_INPUT_ECSPI1_SS0 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_SS0_OFFSET) +#define IMX_INPUT_ECSPI1_SS1 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_SS1_OFFSET) +#define IMX_INPUT_ECSPI1_SS2 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_SS2_OFFSET) +#define IMX_INPUT_ECSPI1_SS3 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI1_SS3_OFFSET) +#define IMX_INPUT_ECSPI2_CSPI_CLK_IN (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI2_CSPI_CLK_IN_OFFSET) +#define IMX_INPUT_ECSPI2_MISO (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI2_MISO_OFFSET) +#define IMX_INPUT_ECSPI2_MOSI (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI2_MOSI_OFFSET) +#define IMX_INPUT_ECSPI2_SS0 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI2_SS0_OFFSET) +#define IMX_INPUT_ECSPI2_SS1 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI2_SS1_OFFSET) +#define IMX_INPUT_ECSPI4_SS0 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI4_SS0_OFFSET) +#define IMX_INPUT_ECSPI5_CSPI_CLK_IN (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI5_CSPI_CLK_IN_OFFSET) +#define IMX_INPUT_ECSPI5_MISO (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI5_MISO_OFFSET) +#define IMX_INPUT_ECSPI5_MOSI (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI5_MOSI_OFFSET) +#define IMX_INPUT_ECSPI5_SS0 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI5_SS0_OFFSET) +#define IMX_INPUT_ECSPI5_SS1 (IMX_IOMUXC_VBASE+IMX_INPUT_ECSPI5_SS1_OFFSET) +#define IMX_INPUT_ENET_REF_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_REF_CLK_OFFSET) +#define IMX_INPUT_ENET_MAC0_MDIO (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_MDIO_OFFSET) +#define IMX_INPUT_ENET_MAC0_RX_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_RX_CLK_OFFSET) +#define IMX_INPUT_ENET_MAC0_RX_DATA0 (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_RX_DATA0_OFFSET) +#define IMX_INPUT_ENET_MAC0_RX_DATA1 (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_RX_DATA1_OFFSET) +#define IMX_INPUT_ENET_MAC0_RX_DATA2 (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_RX_DATA2_OFFSET) +#define IMX_INPUT_ENET_MAC0_RX_DATA3 (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_RX_DATA3_OFFSET) +#define IMX_INPUT_ENET_MAC0_RX_EN (IMX_IOMUXC_VBASE+IMX_INPUT_ENET_MAC0_RX_EN_OFFSET) +#define IMX_INPUT_ESAI_RX_FS (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_RX_FS_OFFSET) +#define IMX_INPUT_ESAI_TX_FS (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_TX_FS_OFFSET) +#define IMX_INPUT_ESAI_RX_HF_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_RX_HF_CLK_OFFSET) +#define IMX_INPUT_ESAI_TX_HF_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_TX_HF_CLK_OFFSET) +#define IMX_INPUT_ESAI_RX_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_RX_CLK_OFFSET) +#define IMX_INPUT_ESAI_TX_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_TX_CLK_OFFSET) +#define IMX_INPUT_ESAI_SDO0 (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_SDO0_OFFSET) +#define IMX_INPUT_ESAI_SDO1 (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_SDO1_OFFSET) +#define IMX_INPUT_ESAI_SDO2_SDI3 (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_SDO2_SDI3_OFFSET) +#define IMX_INPUT_ESAI_SDO3_SDI2 (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_SDO3_SDI2_OFFSET) +#define IMX_INPUT_ESAI_SDO4_SDI1 (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_SDO4_SDI1_OFFSET) +#define IMX_INPUT_ESAI_SDO5_SDI0 (IMX_IOMUXC_VBASE+IMX_INPUT_ESAI_SDO5_SDI0_OFFSET) +#define IMX_INPUT_HDMI_ICECIN (IMX_IOMUXC_VBASE+IMX_INPUT_HDMI_ICECIN_OFFSET) +#define IMX_INPUT_HDMI_II2C_CLKIN (IMX_IOMUXC_VBASE+IMX_INPUT_HDMI_II2C_CLKIN_OFFSET) +#define IMX_INPUT_HDMI_II2C_DATAIN (IMX_IOMUXC_VBASE+IMX_INPUT_HDMI_II2C_DATAIN_OFFSET) +#define IMX_INPUT_I2C1_SCL_IN (IMX_IOMUXC_VBASE+IMX_INPUT_I2C1_SCL_IN_OFFSET) +#define IMX_INPUT_I2C1_SDA_IN (IMX_IOMUXC_VBASE+IMX_INPUT_I2C1_SDA_IN_OFFSET) +#define IMX_INPUT_I2C2_SCL_IN (IMX_IOMUXC_VBASE+IMX_INPUT_I2C2_SCL_IN_OFFSET) +#define IMX_INPUT_I2C2_SDA_IN (IMX_IOMUXC_VBASE+IMX_INPUT_I2C2_SDA_IN_OFFSET) +#define IMX_INPUT_I2C3_SCL_IN (IMX_IOMUXC_VBASE+IMX_INPUT_I2C3_SCL_IN_OFFSET) +#define IMX_INPUT_I2C3_SDA_IN (IMX_IOMUXC_VBASE+IMX_INPUT_I2C3_SDA_IN_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA10 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA10_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA11 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA11_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA12 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA12_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA13 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA13_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA14 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA14_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA15 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA15_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA16 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA16_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA17 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA17_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA18 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA18_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA19 (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA19_OFFSET) +#define IMX_INPUT_IPU2_SENS1_DATA_EN (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_DATA_EN_OFFSET) +#define IMX_INPUT_IPU2_SENS1_HSYNC (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_HSYNC_OFFSET) +#define IMX_INPUT_IPU2_SENS1_PIX_CLK (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_PIX_CLK_OFFSET) +#define IMX_INPUT_IPU2_SENS1_VSYNC (IMX_IOMUXC_VBASE+IMX_INPUT_IPU2_SENS1_VSYNC_OFFSET) +#define IMX_INPUT_KEY_COL5 (IMX_IOMUXC_VBASE+IMX_INPUT_KEY_COL5_OFFSET) +#define IMX_INPUT_KEY_COL6 (IMX_IOMUXC_VBASE+IMX_INPUT_KEY_COL6_OFFSET) +#define IMX_INPUT_KEY_COL7 (IMX_IOMUXC_VBASE+IMX_INPUT_KEY_COL7_OFFSET) +#define IMX_INPUT_KEY_ROW5 (IMX_IOMUXC_VBASE+IMX_INPUT_KEY_ROW5_OFFSET) +#define IMX_INPUT_KEY_ROW6 (IMX_IOMUXC_VBASE+IMX_INPUT_KEY_ROW6_OFFSET) +#define IMX_INPUT_KEY_ROW7 (IMX_IOMUXC_VBASE+IMX_INPUT_KEY_ROW7_OFFSET) +#define IMX_INPUT_MLB_MLB_CLK_IN (IMX_IOMUXC_VBASE+IMX_INPUT_MLB_MLB_CLK_IN_OFFSET) +#define IMX_INPUT_MLB_MLB_DATA_IN (IMX_IOMUXC_VBASE+IMX_INPUT_MLB_MLB_DATA_IN_OFFSET) +#define IMX_INPUT_MLB_MLB_SIG_IN (IMX_IOMUXC_VBASE+IMX_INPUT_MLB_MLB_SIG_IN_OFFSET) +#define IMX_INPUT_SDMA_EVENTS14 (IMX_IOMUXC_VBASE+IMX_INPUT_SDMA_EVENTS14_OFFSET) +#define IMX_INPUT_SDMA_EVENTS47 (IMX_IOMUXC_VBASE+IMX_INPUT_SDMA_EVENTS47_OFFSET) +#define IMX_INPUT_SPDIF_SPDIF_IN1 (IMX_IOMUXC_VBASE+IMX_INPUT_SPDIF_SPDIF_IN1_OFFSET) +#define IMX_INPUT_SPDIF_TX_CLK2 (IMX_IOMUXC_VBASE+IMX_INPUT_SPDIF_TX_CLK2_OFFSET) +#define IMX_INPUT_UART1_UART_RTS_B (IMX_IOMUXC_VBASE+IMX_INPUT_UART1_UART_RTS_B_OFFSET) +#define IMX_INPUT_UART1_UART_RX_DATA (IMX_IOMUXC_VBASE+IMX_INPUT_UART1_UART_RX_DATA_OFFSET) +#define IMX_INPUT_UART2_UART_RTS_B (IMX_IOMUXC_VBASE+IMX_INPUT_UART2_UART_RTS_B_OFFSET) +#define IMX_INPUT_UART2_UART_RX_DATA (IMX_IOMUXC_VBASE+IMX_INPUT_UART2_UART_RX_DATA_OFFSET) +#define IMX_INPUT_UART3_UART_RTS_B (IMX_IOMUXC_VBASE+IMX_INPUT_UART3_UART_RTS_B_OFFSET) +#define IMX_INPUT_UART3_UART_RX_DATA (IMX_IOMUXC_VBASE+IMX_INPUT_UART3_UART_RX_DATA_OFFSET) +#define IMX_INPUT_UART4_UART_RTS_B (IMX_IOMUXC_VBASE+IMX_INPUT_UART4_UART_RTS_B_OFFSET) +#define IMX_INPUT_UART4_UART_RX_DATA (IMX_IOMUXC_VBASE+IMX_INPUT_UART4_UART_RX_DATA_OFFSET) +#define IMX_INPUT_UART5_UART_RTS_B (IMX_IOMUXC_VBASE+IMX_INPUT_UART5_UART_RTS_B_OFFSET) +#define IMX_INPUT_UART5_UART_RX_DATA (IMX_IOMUXC_VBASE+IMX_INPUT_UART5_UART_RX_DATA_OFFSET) +#define IMX_INPUT_USB_OTG_OC (IMX_IOMUXC_VBASE+IMX_INPUT_USB_OTG_OC_OFFSET) +#define IMX_INPUT_USB_H1_OC (IMX_IOMUXC_VBASE+IMX_INPUT_USB_H1_OC_OFFSET) +#define IMX_INPUT_USDHC1_WP_ON (IMX_IOMUXC_VBASE+IMX_INPUT_USDHC1_WP_ON_OFFSET) + +/* IOMUXC Register Bit Definitions **************************************************/ + + +#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_IOMUXC_H */