Merged in masayuki2009/nuttx.nuttx/fe310_updates (pull request #1085)
fe310 updates * arch: fe310: Rename CLIC to CLINT * boards: hifive1-revb: Add README.txt * arch: fe310: Use atomic operations in up_irq_save() and up_irq_enable() * arch: fe310: Remove unused configs in Kconfig * boards: hifive1-revb: Change UART0 buff size and remove debug features. Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Masayuki Ishikawa
Gregory Nutt
parent
b599aa0cee
commit
f46e5d58d0
@ -15,7 +15,7 @@ config ARCH_CHIP_FE310_G002
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select FE310_HAVE_UART0
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select FE310_HAVE_GPIO
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---help---
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FE310, RV32IMAC 32Mbit SPI-Flash, 16KB SRAM
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FE310, RV32IMAC 16KB SRAM
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endchoice
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@ -45,18 +45,3 @@ config FE310_UART0
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select FE310_UART
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endmenu
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config FE310_UART_RX_BUF_SIZE
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int "UART RX Bufer size"
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default 64
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depends on FE310_UART
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---help---
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Size of RX buffers for FE310 UARTs
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config FE310_UART_TX_BUF_SIZE
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int "UART TX Bufer size"
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default 64
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depends on FE310_UART
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---help---
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Size of TX buffers for FE310 UARTs
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@ -191,14 +191,10 @@ void up_ack_irq(int irq)
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irqstate_t up_irq_save(void)
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{
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uint32_t oldstat;
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uint32_t newstat;
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/* Clear machine interrupt enable bit */
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asm volatile ("csrr %0, mstatus": "=r" (oldstat));
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newstat = oldstat & ~MSTATUS_MIE;
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asm volatile("csrw mstatus, %0" : /* no output */ : "r" (newstat));
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/* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
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asm volatile ("csrrc %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
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return oldstat;
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}
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@ -242,11 +238,8 @@ irqstate_t up_irq_enable(void)
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asm volatile("csrw mie, %0" : /* no output */ : "r" (mie));
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#endif
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/* Set machine interrupt enable (MIE) in mstatus */
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asm volatile ("csrr %0, mstatus": "=r" (oldstat));
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newstat = oldstat | MSTATUS_MIE;
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asm volatile("csrw mstatus, %0" : /* no output */ : "r" (newstat));
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/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
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asm volatile ("csrrs %0, mstatus, %1": "=r" (oldstat) : "r"(MSTATUS_MIE));
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return oldstat;
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}
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@ -39,7 +39,7 @@
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#include "hardware/fe310_memorymap.h"
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#include "hardware/fe310_uart.h"
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#include "hardware/fe310_clic.h"
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#include "hardware/fe310_clint.h"
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#include "hardware/fe310_plic.h"
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/****************************************************************************
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@ -81,17 +81,17 @@ static void fe310_reload_mtimecmp(void)
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if (!_b_tick_started)
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{
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_b_tick_started = true;
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current = getreg64(FE310_CLIC_MTIME);
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current = getreg64(FE310_CLINT_MTIME);
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}
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else
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{
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current = getreg64(FE310_CLIC_MTIMECMP);
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current = getreg64(FE310_CLINT_MTIMECMP);
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}
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uint64_t tick = 100000; /* TODO */
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next = current + tick;
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putreg64(next, FE310_CLIC_MTIMECMP);
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putreg64(next, FE310_CLINT_MTIMECMP);
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spin_unlock_irqrestore(flags);
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}
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@ -129,7 +129,7 @@ void riscv_timer_initialize(void)
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(void)irq_attach(FE310_IRQ_MTIMER, fe310_timerisr, NULL);
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/* Reload CLIC mtimecmp */
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/* Reload CLINT mtimecmp */
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fe310_reload_mtimecmp();
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/fe310/hardware/fe310_clic.h
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* arch/risc-v/src/fe310/hardware/fe310_clint.h
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*
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* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
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* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
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@ -30,14 +30,14 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H
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#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H
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#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLINT_H
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#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLINT_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define FE310_CLIC_MTIMECMP (FE310_CLIC_BASE + 0x4000)
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#define FE310_CLIC_MTIME (FE310_CLIC_BASE + 0xbff8)
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#define FE310_CLINT_MTIMECMP (FE310_CLINT_BASE + 0x4000)
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#define FE310_CLINT_MTIME (FE310_CLINT_BASE + 0xbff8)
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#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H */
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#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLINT_H */
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@ -39,7 +39,7 @@
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/* Register Base Address ****************************************************/
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#define FE310_CLIC_BASE 0x02000000
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#define FE310_CLINT_BASE 0x02000000
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#define FE310_PLIC_BASE 0x0c000000
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#define FE310_GPIO_BASE 0x10012000 /* 0x10012000 - 0x10012fff: GPIO */
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32
boards/risc-v/fe310/hifive1-revb/README.txt
Normal file
32
boards/risc-v/fe310/hifive1-revb/README.txt
Normal file
@ -0,0 +1,32 @@
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1. Download and install toolchain
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$ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
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2. Build and install qemu
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$ git clone https://github.com/qemu/qemu
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$ cd qemu
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$ ./configure --target-list=riscv32-softmmu
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$ make
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$ sudo make install
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3. Configure and build NuttX
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$ mkdir ./nuttx; cd ./nuttx
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$ git clone https://bitbucket.org/nuttx/nuttx.git
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$ git clone https://bitbucket.org/nuttx/apps.git
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$ cd nuttx
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$ make distclean
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$ ./tools/configure.sh hifive1-revb:nsh
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$ make V=1
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4. Run the nuttx with qemu
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$ qemu-system-riscv32 -nographic -machine sifive_e -kernel ./nuttx
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5. TODO
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Configure PLL and UART divisor
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Run nuttx on HiFive1-Rev.B board
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Support GPIO/SPI/I2C/RTC/WDT/PWM
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Support RISC-V User mode
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@ -21,9 +21,6 @@ CONFIG_ARCH_STACKDUMP=y
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CONFIG_BINFMT_DISABLE=y
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CONFIG_BOARD_LOOPSPERMSEC=15000
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_ASSERTIONS=y
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CONFIG_DEBUG_ERROR=y
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CONFIG_DEBUG_FEATURES=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEFAULT_SMALL=y
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@ -68,6 +65,8 @@ CONFIG_STDIO_DISABLE_BUFFERING=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_TASK_NAME_SIZE=12
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CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
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CONFIG_UART0_RXBUFSIZE=8
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CONFIG_UART0_SERIAL_CONSOLE=y
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CONFIG_UART0_TXBUFSIZE=4
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_WDOG_INTRESERVE=0
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