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stm32/chip: Add some STM32L15XX support bits (from Thingsee)

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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
This commit is contained in:
Juha Niskanen 2015-07-29 07:34:24 -06:00 committed by Gregory Nutt
parent eddf8161a5
commit f4812bfbf9
6 changed files with 65 additions and 15 deletions
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12
arch/arm/src/stm32/chip/stm32_dbgmcu.h
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@ -53,7 +53,7 @@
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ #define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ #define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX) defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
#endif #endif
@ -118,7 +118,7 @@
# define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */ # define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ # define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
# define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ # define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */
#elif defined(CONFIG_STM32_STM32F30XX) #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32L15XX)
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ # define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
@ -129,7 +129,9 @@
# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ # define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ # define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ # define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ # if defined(CONFIG_STM32_STM32F30XX)
# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
# endif
#endif #endif
/* Debug MCU APB2 freeze register */ /* Debug MCU APB2 freeze register */
@ -146,6 +148,10 @@
# define DBGMCU_APB2_TIM15STOP (1 << 2) /* Bit 2: TIM15 stopped when core is halted */ # define DBGMCU_APB2_TIM15STOP (1 << 2) /* Bit 2: TIM15 stopped when core is halted */
# define DBGMCU_APB2_TIM16STOP (1 << 3) /* Bit 3: TIM16 stopped when core is halted */ # define DBGMCU_APB2_TIM16STOP (1 << 3) /* Bit 3: TIM16 stopped when core is halted */
# define DBGMCU_APB2_TIM17STOP (1 << 4) /* Bit 4: TIM17 stopped when core is halted */ # define DBGMCU_APB2_TIM17STOP (1 << 4) /* Bit 4: TIM17 stopped when core is halted */
#elif defined(CONFIG_STM32_STM32L15XX)
# define DBGMCU_APB2_TIM9STOP (1 << 2) /* Bit 2: TIM9 stopped when core is halted */
# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */
# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */
#endif #endif
/**************************************************************************************************** /****************************************************************************************************

2
arch/arm/src/stm32/chip/stm32_pwr.h
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@ -107,7 +107,7 @@
#if defined(CONFIG_STM32_STM32L15XX) #if defined(CONFIG_STM32_STM32L15XX)
# define PWR_CR_ULP (1 << 9) /* Ultralow power mode */ # define PWR_CR_ULP (1 << 9) /* Ultralow power mode */
# define PWR_CR_FWU (1 << 10) /* Low power run mode */ # define PWR_CR_FWU (1 << 10) /* Fast wake-up */
# define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */ # define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */
# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */ # define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */
# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */ # define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */

49
arch/arm/src/stm32/chip/stm32_rtcc.h
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@ -57,7 +57,7 @@
#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ #define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ #define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ #define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
#define STM32_RTC_TSDR_OFFSET 0x0030 /* RTC time stamp date register */ #define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ #define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ #define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ #define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */
@ -87,6 +87,20 @@
# define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ # define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
# define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ # define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
#endif #endif
#ifdef CONFIG_STM32_STM32L15XX
# define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
# define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
# define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
# define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
# define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
# define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
# define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
# define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
# define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
# define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
# define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
# define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
#endif
/* Register Addresses ***************************************************************/ /* Register Addresses ***************************************************************/
@ -135,6 +149,28 @@
# define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) # define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET)
# define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) # define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET)
#endif #endif
#ifdef CONFIG_STM32_STM32L15XX
# define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET)
# define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET)
# define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET)
# define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET)
# define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET)
# define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET)
# define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET)
# define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET)
# define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET)
# define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET)
# define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET)
# define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET)
#endif
#ifdef CONFIG_STM32_STM32F30XX
# define STM32_RTC_BKCOUNT 16
#elif defined(CONFIG_STM32_STM32L15XX)
# define STM32_RTC_BKCOUNT 32
#else
# define STM32_RTC_BKCOUNT 20
#endif
/* Register Bitfield Definitions ****************************************************/ /* Register Bitfield Definitions ****************************************************/
@ -232,6 +268,9 @@
#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ #define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ #define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ #define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
#ifdef CONFIG_STM32_STM32L15XX
# define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */
#endif
#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */ #define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */
#define RTC_ISR_ALLFLAGS (0x00017fff) #define RTC_ISR_ALLFLAGS (0x00017fff)
@ -370,9 +409,9 @@
/* RTC alarm A/B sub second register */ /* RTC alarm A/B sub second register */
#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-15: Sub second value */ #define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
#define RTC_ALRMSSR_SS_MASK (0xffff << RTC_ALRMSSR_SS_SHIFT) #define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
#define RTC_ALRMSSR_MASKSS_SHIFT (0) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xffff << RTC_ALRMSSR_SS_SHIFT) #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H */

2
arch/arm/src/stm32/chip/stm32_tim.h
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@ -822,7 +822,7 @@
#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ #define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ #define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
# define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ # define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
#elif defined(CONFIG_STM32_STM32F30XX) #elif defined(CONFIG_STM32_STM32F30XX)
# define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ # define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */

9
arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
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@ -42,7 +42,7 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* STM32F40XXX Address Blocks *******************************************************/ /* STM32L15XXX Address Blocks *******************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
@ -56,10 +56,8 @@
/* Code Base Addresses **************************************************************/ /* Code Base Addresses **************************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x07ffffff: Aliased boot memory */ #define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x07ffffff: Aliased boot memory */
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0801ffff: FLASH memory */ #define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: Program FLASH memory */
/* 0x08020000-0x807fffff: Reserved */ #define STM32_EEPROM_BASE 0x08080000 /* 0x08080000-0x08083fff: Data FLASH memory */
#define STM32_EEPROM_BASE 0x08080000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */
/* 0x10010000-0x1ffeffff: Reserved */
#define STM32_SYSMEM_BASE 0x1ff00000 /* 0x1ff00000-0x1ff00fff: System memory */ #define STM32_SYSMEM_BASE 0x1ff00000 /* 0x1ff00000-0x1ff00fff: System memory */
/* 0x1ff01000-0x1fff7fff: Reserved */ /* 0x1ff01000-0x1fff7fff: Reserved */
#define STM32_OPTION_BASE 0x1ff80000 /* 0x1fffc000-0x1ff8001f: Option bytes */ #define STM32_OPTION_BASE 0x1ff80000 /* 0x1fffc000-0x1ff8001f: Option bytes */
@ -114,6 +112,7 @@
#define STM32_TIM9_BASE 0x40010800 /* 0x40010800-0x40010bff TIM9 */ #define STM32_TIM9_BASE 0x40010800 /* 0x40010800-0x40010bff TIM9 */
#define STM32_TIM10_BASE 0x40010c00 /* 0x40010c00-0x40010fff TIM10 */ #define STM32_TIM10_BASE 0x40010c00 /* 0x40010c00-0x40010fff TIM10 */
#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ #define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
#define STM32_ADCCMN_BASE (STM32_ADC_BASE+0x300) /* ADC Common */
#define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff SDIO */ #define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff SDIO */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */

6
arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
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@ -100,6 +100,12 @@
#define GPIO_ADC1_IN24 (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN9) #define GPIO_ADC1_IN24 (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN9)
#define GPIO_ADC1_IN25 (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN10) #define GPIO_ADC1_IN25 (GPIO_ANALOG | GPIO_PORTE | GPIO_PIN10)
#define GPIO_ADC1_IN27 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN6)
#define GPIO_ADC1_IN28 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN7)
#define GPIO_ADC1_IN29 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN8)
#define GPIO_ADC1_IN30 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN9)
#define GPIO_ADC1_IN31 (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN10)
/* DAC */ /* DAC */
#define GPIO_DAC_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) #define GPIO_DAC_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)