spi update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1739 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
e506daa279
commit
f4988c7151
@ -50,41 +50,108 @@
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/* CSPI Register Offsets ************************************************************/
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#define CSPI_SPIRXD_OFFSET 0x0000
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#define CSPI_SPITXD_OFFSET 0x0004
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#define CSPI_SPICONT1_OFFSET 0x0008
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#define CSPI_INTCS_OFFSET 0x000c
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#define CSPI_SPITEST_OFFSET 0x0010
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#define CSPI_SPISPCR_OFFSET 0x0014
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#define CSPI_SPIDMA_OFFSET 0x0018
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#define CSPI_SPIRESET_OFFSET 0x001c
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#define CSPI_RXD_OFFSET 0x0000 /* Receive Data Register */
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#define CSPI_TXD_OFFSET 0x0004 /* Transmit Data Register */
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#define CSPI_CTRL_OFFSET 0x0008 /* Control Register */
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#define CSPI_INTCS_OFFSET 0x000c /* Interrupt Control/Status Register */
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#define CSPI_TEST_OFFSET 0x0010 /* Test Register */
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#define CSPI_SPCR_OFFSET 0x0014 /* Sample Period Control Register */
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#define CSPI_DMA_OFFSET 0x0018 /* DMA Control Register */
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#define CSPI_RESET_OFFSET 0x001c /* Soft Reset Register */
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/* CSPI Register Addresses **********************************************************/
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/* CSPI1 */
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#define IMX_CSPI1_SPIRXD (IMX_CSPI1_VBASE + CSPI_SPIRXD_OFFSET)
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#define IMX_CSPI1_SPITXD (IMX_CSPI1_VBASE + CSPI_SPITXD_OFFSET)
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#define IMX_CSPI1_SPICONT1 (IMX_CSPI1_VBASE + CSPI_SPICONT1_OFFSET)
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#define IMX_CSPI1_RXD (IMX_CSPI1_VBASE + CSPI_RXD_OFFSET)
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#define IMX_CSPI1_TXD (IMX_CSPI1_VBASE + CSPI_TXD_OFFSET)
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#define IMX_CSPI1_CTRL (IMX_CSPI1_VBASE + CSPI_CTRL_OFFSET)
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#define IMX_CSPI1_INTCS (IMX_CSPI1_VBASE + CSPI_INTCS_OFFSET)
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#define IMX_CSPI1_SPITEST (IMX_CSPI1_VBASE + CSPI_SPITEST_OFFSET)
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#define IMX_CSPI1_SPISPCR (IMX_CSPI1_VBASE + CSPI_SPISPCR_OFFSET)
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#define IMX_CSPI1_SPIDMA (IMX_CSPI1_VBASE + CSPI_SPIDMA_OFFSET)
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#define IMX_CSPI1_SPIRESET (IMX_CSPI1_VBASE + CSPI_SPIRESET_OFFSET)
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#define IMX_CSPI1_SPITEST (IMX_CSPI1_VBASE + CSPI_TEST_OFFSET)
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#define IMX_CSPI1_SPISPCR (IMX_CSPI1_VBASE + CSPI_SPCR_OFFSET)
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#define IMX_CSPI1_SPIDMA (IMX_CSPI1_VBASE + CSPI_DMA_OFFSET)
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#define IMX_CSPI1_SPIRESET (IMX_CSPI1_VBASE + CSPI_RESET_OFFSET)
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/* CSPI1 */
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#define IMX_CSPI2_SPIRXD (IMX_CSPI2_VBASE + CSPI_SPIRXD_OFFSET)
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#define IMX_CSPI2_SPITXD (IMX_CSPI2_VBASE + CSPI_SPITXD_OFFSET)
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#define IMX_CSPI2_SPICONT1 (IMX_CSPI2_VBASE + CSPI_SPICONT1_OFFSET)
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#define IMX_CSPI2_RXD (IMX_CSPI2_VBASE + CSPI_RXD_OFFSET)
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#define IMX_CSPI2_TXD (IMX_CSPI2_VBASE + CSPI_TXD_OFFSET)
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#define IMX_CSPI2_CTRL (IMX_CSPI2_VBASE + CSPI_CTRL_OFFSET)
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#define IMX_CSPI2_INTCS (IMX_CSPI2_VBASE + CSPI_INTCS_OFFSET)
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#define IMX_CSPI2_SPITEST (IMX_CSPI2_VBASE + CSPI_SPITEST_OFFSET)
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#define IMX_CSPI2_SPISPCR (IMX_CSPI2_VBASE + CSPI_SPISPCR_OFFSET)
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#define IMX_CSPI2_SPIDMA (IMX_CSPI2_VBASE + CSPI_SPIDMA_OFFSET)
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#define IMX_CSPI2_SPIRESET (IMX_CSPI2_VBASE + CSPI_SPIRESET_OFFSET)
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#define IMX_CSPI2_SPITEST (IMX_CSPI2_VBASE + CSPI_TEST_OFFSET)
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#define IMX_CSPI2_SPISPCR (IMX_CSPI2_VBASE + CSPI_SPCR_OFFSET)
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#define IMX_CSPI2_SPIDMA (IMX_CSPI2_VBASE + CSPI_DMA_OFFSET)
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#define IMX_CSPI2_SPIRESET (IMX_CSPI2_VBASE + CSPI_RESET_OFFSET)
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/* CSPI Register Bit Definitions ****************************************************/
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/* CSPI Control Register */
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#define CSPI_CTRL_DATARATE_SHIFT 13
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#define CSPI_CTRL_DATARATE_MASK (7 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV4 (0 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV8 (1 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV16 (2 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV32 (3 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV64 (4 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV128 (5 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV256 (6 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DIV512 (7 << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_CTRL_DRCTL_SHIFT 11
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#define CSPI_CTRL_DRCTL_MASK (3 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_DRCTL_IGNRDY (0 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_DRCTL_FALLING (1 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_DRCTL_ACTVLOW (2 << CSPI_CTRL_DRCTL_SHIFT)
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#define CSPI_CTRL_MODE (1 << 10)
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#define CSPI_CTRL_SPIEN (1 << 9)
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#define CSPI_CTRL_XCH (1 << 8)
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#define CSPI_CTRL_SSPOL (1 << 7)
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#define CSPI_CTRL_SSCTL (1 << 6)
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#define CSPI_CTRL_PHA (1 << 5)
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#define CSPI_CTRL_POL (1 << 4)
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#define CSPI_CTRL_BITCOUNT_SHIFT 0
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#define CSPI_CTRL_BITCOUNT_MASK (15 << CSPI_CTRL_BITCOUNT_SHIFT)
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/* CSPI Interrrupt Control/Status Register */
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#define CSPI_INTCS_TE (1 << 0) /* Bit 0: TXFIFO Empty Status */
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#define CSPI_INTCS_TH (1 << 1) /* Bit 1: TXFIFO Half Status */
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#define CSPI_INTCS_TF (1 << 2) /* Bit 2: TXFIFO Full Status */
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#define CSPI_INTCS_RR (1 << 3) /* Bit 3: RXFIFO Data Ready Status */
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#define CSPI_INTCS_RH (1 << 4) /* Bit 4: RXFIFO Half Status */
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#define CSPI_INTCS_RF (1 << 5) /* Bit 5: RXFIFO Full Status */
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#define CSPI_INTCS_RO (1 << 6) /* Bit 6: RXFIFO Overflow */
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#define CSPI_INTCS_BO (1 << 7) /* Bit 7: Bit Count Overflow */
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#define CSPI_INTCS_TEEN (1 << 8) /* Bit 8: TXFIFO Empty Interrupt Enable */
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#define CSPI_INTCS_THEN (1 << 9) /* Bit 9: TXFIFO Half Interrupt Enable */
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#define CSPI_INTCS_TFEN (1 << 10) /* Bit 10: TXFIFO Full Interrupt Enable */
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#define CSPI_INTCS_RREN (1 << 11) /* Bit 11: RXFIFO Data Ready Interrupt Enable */
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#define CSPI_INTCS_RHEN (1 << 12) /* Bit 12: RXFIFO Half Interrupt Enable */
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#define CSPI_INTCS_RFEN (1 << 13) /* Bit 13: RXFIFO Full Interrupt Enable */
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#define CSPI_INTCS_ROEN (1 << 14) /* BIT 14: RXFIFO Overflow Interrupt Enable */
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#define CSPI_INTCS_BOEN (1 << 15) /* Bit 15: Bit Count Overflow Interrupt Enable */
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/* CSPI Sample Period Control Register */
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#define CSPI_SPCR_WAIT_SHIFT 0
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#define CSPI_SPCR_WAIT_MASK (0x7ff << CSPI_CTRL_DATARATE_SHIFT)
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#define CSPI_SPCR_CSRC (1 << 15) /* Bit 15: 1:32768 or 32 kHz clock source */
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/* CSPI DMA Control Register */
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#define CSPI_DMA_RHDMA (1 << 4) /* Bit 4: RXFIFO Half Status */
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#define CSPI_DMA_RFDMA (1 << 5) /* Bit 5: RXFIFO Full Status */
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#define CSPI_DMA_TEDMA (1 << 6) /* Bit 6: TXFIFO Empty Status */
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#define CSPI_DMA_THDMA (1 << 7) /* Bit 7: TXFIFO Half Status */
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#define CSPI_DMA_RHDEN (1 << 12) /* Bit 12: Enable RXFIFO Half DMA Request */
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#define CSPI_DMA_RFDEN (1 << 13) /* Bit 13: Enables RXFIFO Full DMA Request */
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#define CSPI_DMA_TEDEN (1 << 14) /* Bit 14: Enable TXFIFO Empty DMA Request */
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#define CSPI_DMA_THDEN (1 << 15) /* Bit 15: Enable TXFIFO Half DMA Request */
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/* Soft Reset Register */
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#define CSPI_RESET_START (1 << 0) /* Bit 0: Execute soft reset */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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@ -550,6 +550,7 @@ static inline void imxgpio_clroutput(int port, int bit)
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extern void imxgpio_configoutput(int port, int bit, int value);
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extern void imxgpio_configinput(int port, int bit);
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extern void imxgpio_configpfoutput(int port, int bit);
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extern void imxgpio_configpfinput(int port, int bit);
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@ -88,6 +88,11 @@ struct imx_spidev_s
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{
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const struct spi_ops_s *ops; /* Common SPI operations */
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uint32 base; /* SPI register base address */
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uint32 frequency; /* Current desired SCLK frequency */
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uint32 actual; /* Current actual SCLK frequency */
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ubyte mode; /* Current mode */
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ubyte nbytes; /* Current number of bits per word */
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ubyte irq; /* SPI IRQ number */
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};
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/****************************************************************************
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@ -97,7 +102,7 @@ struct imx_spidev_s
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/* SPI helpers */
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static inline uint32 spi_getreg(struct imx_spidev_s *priv, unsigned int offset);
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static inline void spi_readreg(struct imx_spidev_s *priv, unsigned int offset, uint32 value);
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static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32 value);
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static ubyte spi_waitspif(struct imx_spidev_s *priv);
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static ubyte spi_transfer(struct imx_spidev_s *priv, ubyte ch);
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@ -134,12 +139,14 @@ static struct imx_spidev_s g_spidev[] =
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{
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.ops = &g_spiops,
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.base = IMX_CSPI1_VBASE
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.irq = IMX_IRQ_CSPI1,
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},
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#endif
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#ifndef CONFIG_SPI1_DISABLE
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{
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.ops = &g_spiops,
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.base = IMX_CSPI2_VBASE
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.irq = IMX_IRQ_CSPI2,
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},
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#endif
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};
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@ -188,7 +195,7 @@ static inline uint32 spi_getreg(struct imx_spidev_s *priv, unsigned int offset)
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*
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****************************************************************************/
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static inline void spi_readreg(struct imx_spidev_s *priv, unsigned int offset, uint32 value)
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static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32 value)
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{
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putreg32(value, priv->base + offset);
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}
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@ -270,8 +277,66 @@ static ubyte spi_transfer(struct imx_spidev_s *priv, ubyte ch)
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static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency)
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{
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struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
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#error "Missing logic"
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return frequency;
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uint32 actual = priv->actual;
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if (priv & frequency != priv->frequency)
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{
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uint32 freqbits;
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uint32 regval;
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if (frequency >= PERCLK2 / 4)
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{
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freqbits = CSPI_CTRL_DIV4;
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actual = PERCLK2 / 4;
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}
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else if (frequency >= PERCLK2 / 8)
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{
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freqbits = CSPI_CTRL_DIV8;
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actual = PERCLK2 / 8;
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}
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else if (frequency >= PERCLK2 / 16)
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{
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freqbits = CSPI_CTRL_DIV16;
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actual = PERCLK2 / 16;
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}
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else if (frequency >= PERCLK2 / 32)
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{
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freqbits = CSPI_CTRL_DIV32;
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actual = PERCLK2 / 32;
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}
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else if (frequency >= PERCLK2 / 64)
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{
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freqbits = CSPI_CTRL_DIV64;
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actual = PERCLK2 / 64;
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}
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else if (frequency >= PERCLK2 / 128)
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{
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freqbits = CSPI_CTRL_DIV128;
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actual = PERCLK2 / 128;
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}
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else if (frequency >= PERCLK2 / 256)
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{
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freqbits = CSPI_CTRL_DIV256;
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actual = PERCLK2 / 256;
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}
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else /*if (frequency >= PERCLK2 / 512) */
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{
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freqbits = CSPI_CTRL_DIV512;
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actual = PERCLK2 / 512;
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}
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/* Then set the selected frequency */
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regval = spi_regreg(priv, CSPI_CTRL_OFFSET);
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regval &= ~(CSPI_CTRL_DATARATE_MASK);
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regval |= freqbits;
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spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
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priv->frequency = frequency;
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priv->actual = actual;
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}
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return actual;
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}
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/****************************************************************************
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@ -292,27 +357,29 @@ static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency)
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static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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{
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struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
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if (priv & mode != priv->mode)
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{
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uint32 modebits;
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ubyte regval;
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uint32 regval;
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/* Select the CTL register bits based on the selected mode */
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switch (mode)
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{
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case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
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#error "Missing logic"
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modebits = 0;
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break;
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case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
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#error "Missing logic"
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modebits = CSPI_CTRL_PHA;
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break;
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case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
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#error "Missing logic"
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modebits = CSPI_CTRL_POL;
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break;
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case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
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#error "Missing logic"
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modebits = CSPI_CTRL_PHA|CSPI_CTRL_POL;
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break;
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default:
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@ -320,7 +387,12 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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}
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/* Then set the selected mode */
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#error "Missing logic"
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regval = spi_regreg(priv, CSPI_CTRL_OFFSET);
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regval &= ~(CSPI_CTRL_PHA|CSPI_CTRL_POL);
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regval |= modebits;
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spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
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}
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}
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/****************************************************************************
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@ -442,8 +514,14 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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priv = &g_spidev[SPI1_NDX];
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/* Configure SPI1 GPIOs */
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#error "Missing logic"
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/* Configure SPI1 GPIOs (NOTE that SS is not initialized here, the
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* logic in this file makes no assumptions about chip select)
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*/
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imxgpio_configpfinput(GPIOC, 13); /* Port C, pin 13: RDY */
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imxgpio_configpfoutput(GPIOC, 14); /* Port C, pin 14: SCLK */
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imxgpio_configpfinput(GPIOC, 16); /* Port C, pin 16: MISO */
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imxgpio_configpfoutput(GPIOC, 17); /* Port C, pin 17: MOSI */
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break;
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#endif
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@ -454,7 +532,48 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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priv = &g_spidev[SPI2_NDX];
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/* Configure SPI1 GPIOs */
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#error "Missing logic"
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/* SCLK: AIN of Port A, pin 0 -OR- AIN of Port D, pin 7 */
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#if 1
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imxgpio_configoutput(GPIOA, 0); /* Set GIUS=1 OCR=0 DIR=OUT */
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#else
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imxgpio_configoutput(GPIOD, 7); /* Set GIUS=1 OCR=0 DIR=OUT */
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#endif
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/* SS: AIN of Port A, pin 17 -OR- AIN of Port D, pin 8.(NOTE that SS
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* is not initialized here, the logic in this file makes no assumptions
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* about chip select)
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*/
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/* RXD: AOUT of Port A, pin 1 -OR- AOUT of Port D, pin 9 */
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#if 1
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imxgpio_configinput(GPIOA, 1); /* Set GIUS=1 OCR=0 DIR=IN */
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/* Select input from SPI2_RXD_0 pin (AOUT Port A, pin 1) */
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regval = getreg32(IMX_SC_FMCR);
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regval &= ~FMCR_SPI2_RXDSEL;
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putreg32(regval, IMX_SC_FMCR);
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#else
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imxgpio_configinput(GPIOD, 9); /* Set GIUS=1 OCR=0 DIR=IN */
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/* Select input from SPI2_RXD_1 pin (AOUT Port D, pin 9) */
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regval = getreg32(IMX_SC_FMCR);
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regval |= FMCR_SPI2_RXDSEL;
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putreg32(regval, IMX_SC_FMCR);
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#endif
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/* TXD: BIN of Port D, pin 31 -OR- AIN of Port D, pin 10 */
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#if 1
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imxgpio_configinput(GPIOD, 31);
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imxgpio_ocrbin(GPIOD, 31);
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imxgpio_dirout(GPIOD, 31);
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#else
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imxgpio_configoutput(GPIOD, 10);
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#endif
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break;
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#endif
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@ -465,16 +584,53 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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/* Disable SPI */
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#error "Missing logic"
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/* Set the initial clock frequency for indentification mode < 400kHz */
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/* Initialize control rebistger: min frequency, ignore ready, master mode, mode=0, 8-bit */
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spi_putreg(priv, IMX_CSPI_CTRL_OFFSET,
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CSPI_CTRL_DIV512 | /* Lowest frequency */
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CSPI_CTRL_DRCTL_IGNRDY | /* Ignore ready */
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CSPI_CTRL_MODE | /* Master mode */
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(7 << CSPI_CTRL_BITCOUNT_SHIFT)); /* 8-bit data */
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/* Make sure state agrees with data */
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||||
priv->mode = SPIDEV_MODE0;
|
||||
priv->nbits = 8;
|
||||
|
||||
/* Set the initial clock frequency for identification mode < 400kHz */
|
||||
|
||||
spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
|
||||
|
||||
/* Enable the SPI.
|
||||
* NOTE 1: Interrupts are not used in this driver version.
|
||||
* NOTE 2: Initial mode is mode=0.
|
||||
/* Enable interrupts on data ready (and certain error conditions */
|
||||
|
||||
spi_putreg(priv, CSPI_INTCS_OFFSET,
|
||||
CSPI_INTCS_RREN | /* RXFIFO Data Ready Interrupt Enable */
|
||||
CSPI_INTCS_ROEN | /* RXFIFO Overflow Interrupt Enable */
|
||||
CSPI_INTCS_BOEN); /* Bit Count Overflow Interrupt Enable */
|
||||
|
||||
/* Set the clock source=bit clock and number of clocks inserted between
|
||||
* transactions = 2.
|
||||
*/
|
||||
|
||||
#error "Missing logic"
|
||||
spi_putreg(priv, CSPI_SPCR_OFFSET, 2);
|
||||
|
||||
/* No DMA */
|
||||
|
||||
spi_putreg(priv, CSPI_DMA_OFFSET, 0);
|
||||
|
||||
/* Attach the interrupt */
|
||||
|
||||
irq_attach(priv->irq, (xcpt_t)imx_spinterrupt);
|
||||
|
||||
/* Enable SPI */
|
||||
|
||||
regval = spi_getreg(priv, IMX_CSPI_CTRL_OFFSET);
|
||||
regval |= CSPI_CTRL_SPIEN;
|
||||
spi_putreg(priv, IMX_CSPI_CTRL_OFFSET, regval);
|
||||
|
||||
/* Enable SPI interrupts */
|
||||
|
||||
up_enable_irq(priv->irq);
|
||||
return (FAR struct spi_dev_s *)priv;
|
||||
}
|
||||
|
||||
|
||||
@ -156,6 +156,18 @@
|
||||
|
||||
/* SC Register Bit Definitions ******************************************************/
|
||||
|
||||
|
||||
#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */
|
||||
#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */
|
||||
#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */
|
||||
#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */
|
||||
#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */
|
||||
#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */
|
||||
#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */
|
||||
#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */
|
||||
#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin
|
||||
* (AOUT of Port D[9]) */
|
||||
|
||||
/* SDRAMC Register Offsets **********************************************************/
|
||||
|
||||
#define SDRAMC_SDCTL0_OFFSET 0x0000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user