sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

SAMA UDPHS: Add pull-up and stall logic. Added to build system but does not yet build

Browse Source
This commit is contained in:
Gregory Nutt 2013-08-31 17:37:51 -06:00
parent 147dc5206d
commit f4c1568c17
7 changed files with 598 additions and 287 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
arch/arm/src/sama5/Kconfig
View File

@ -335,8 +335,44 @@ config SAMA5_HSMCI_REGDEBUG
endmenu # HSMCI device driver options
endif # SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2
if SAMA5_UDPHS
menu "USB High Speed Device Controller driver (DCD) options"
config UDPHS_SCATTERGATHER
bool
default n
---help---
Scatter gather DMA is not yet supported
config SAMA5_UDPHS_NDTDS
int "Number of UDPHS DMA transfer descriptors"
default 9
depends on UDPHS_SCATTERGATHER
---help---
DMA tranfer descriptors are allocated in a pool at boot time. This
setting provides the number of DMA transfer descriptors to be
allocated.
config SAMA5_UDPHS_PREALLOCATE
bool "Pre-allocate DMA transfer descriptors"
default y
depends on UDPHS_SCATTERGATHER
---help---
If this option is selected then DMA tranfer descriptors will be
pre-allocated in .bss. Otherwise, the descriptors will be allocated
at start-up time with kmalloc(). This might be important if a larger
memory pool is available after startup.
config SAMA5_UDPHS_REGDEBUG
bool "Enable low-level UPPHS register debug"
default n
depends on DEBUG
endmenu # USB High Speed Host Device driver (DCD) options
endif # SAMA5_UDPHS
if SAMA5_UHPHS
menu "USB High Speed Host device driver options"
menu "USB High Speed Host Controller driver (HCD) options"
config SAMA5_OHCI
bool "Full/low speed OHCI support"
@ -436,7 +472,7 @@ config SAMA5_UHPHS_RHPORT3
endif # SAMA5_OHCI || SAMA5_EHCI
endmenu # USB High Speed Host driver option
endmenu # USB High Speed Host Controller driver (HCD) options
endif # SAMA5_UHPHS
menu "External Memory Configuration"

4
arch/arm/src/sama5/Make.defs
View File

@ -124,6 +124,10 @@ CHIP_CSRCS += sam_ehci.c
endif
endif
ifeq ($(CONFIG_SAMA5_UDPHS),y)
CHIP_CSRCS += sam_udphs.c
endif
ifeq ($(CONFIG_SAMA5_HSMCI0),y)
CHIP_CSRCS += sam_hsmci.c
else

4
arch/arm/src/sama5/chip/sam_udphs.h
View File

@ -82,7 +82,7 @@
/* 0x00e4-0x00e8 Reserved */
/* Endpoint Offsets */
#define SAM_UPPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5)
#define SAM_UPPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5))
#define SAM_UPPHS_EP0_OFFSET 0x0100
#define SAM_UPPHS_EP1_OFFSET 0x0120
#define SAM_UPPHS_EP2_OFFSET 0x0140
@ -252,7 +252,7 @@
# define UDPHS_INT_EPT15 (1 << 23) /* Bit 23: Endpoint 15 Interrupt */
#define UDPHS_INT_DMA_SHIFT (25) /* Bits 25-31: Endpoint interrupts */
#define UDPHS_INT_DMA_MASK (0x7f << UDPHS_INT_DMA_SHIFT)
#define UDPHS_INT_DMA(ch) (1 << ((ch)+24) /* DMA Channel ch Interrupt */
#define UDPHS_INT_DMA(ch) (1 << ((ch)+24)) /* DMA Channel ch Interrupt */
# define UDPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt */
# define UDPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt */
# define UDPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt */

52
arch/arm/src/sama5/sam_periphclks.h
View File

@ -54,6 +54,8 @@
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
#define sam_dbgu_enableclk() sam_enableperiph0(SAM_PID_DBGU)
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
@ -155,6 +157,56 @@
#define sam_fuse_disableclk() sam_disableperiph1(SAM_PID_FUSE)
#define sam_mpddrc_disableclk() sam_disableperiph1(SAM_PID_MPDDRC)
#define sam_dbgu_isenabled() sam_isenabled0(SAM_PID_DBGU)
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
#define sam_smd_isenabled() sam_isenabled0(SAM_PID_SMD)
#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0)
#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1)
#define sam_twi2_isenabled() sam_isenabled0(SAM_PID_TWI2)
#define sam_hsmci0_isenabled() sam_isenabled0(SAM_PID_HSMCI0)
#define sam_hsmci1_isenabled() sam_isenabled0(SAM_PID_HSMCI1)
#define sam_hsmci2_isenabled() sam_isenabled0(SAM_PID_HSMCI2)
#define sam_spi0_isenabled() sam_isenabled0(SAM_PID_SPI0)
#define sam_spi1_isenabled() sam_isenabled0(SAM_PID_SPI1)
#define sam_tc0_isenabled() sam_isenabled0(SAM_PID_TC0)
#define sam_tc1_isenabled() sam_isenabled0(SAM_PID_TC1)
#define sam_pwm_isenabled() sam_isenabled0(SAM_PID_PWM)
#define sam_adc_isenabled() sam_isenabled0(SAM_PID_ADC)
#define sam_dmac0_isenabled() sam_isenabled0(SAM_PID_DMAC0)
#define sam_dmac1_isenabled() sam_isenabled0(SAM_PID_DMAC1)
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
#define sam_gmac_isenabled() sam_isenabled1(SAM_PID_GMAC)
#define sam_emac_isenabled() sam_isenabled1(SAM_PID_EMAC)
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
#define sam_can0_isenabled() sam_isenabled1(SAM_PID_CAN0)
#define sam_can1_isenabled() sam_isenabled1(SAM_PID_CAN1)
#define sam_sha_isenabled() sam_isenabled1(SAM_PID_SHA)
#define sam_aes_isenabled() sam_isenabled1(SAM_PID_AES)
#define sam_tdes_isenabled() sam_isenabled1(SAM_PID_TDES)
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
#define sam_arm_isenabled() sam_isenabled1(SAM_PID_ARM)
#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC)
#define sam_fuse_isenabled() sam_isenabled1(SAM_PID_FUSE)
#define sam_mpddrc_isenabled() sam_isenabled1(SAM_PID_MPDDRC)
/************************************************************************************
* Public Types
************************************************************************************/

676
arch/arm/src/sama5/sam_udphs.c
View File

File diff suppressed because it is too large Load Diff

84
arch/arm/src/sama5/sam_udphs.h Normal file
View File

@ -0,0 +1,84 @@
/************************************************************************************
* arch/arm/src/sama5/sam_udphs.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H
#define __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/usb/usbdev.h>
#include <stdint.h>
#include "chip.h"
#include "chip/sam_udphs.h"
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Name: sam_usbsuspend
*
* Description:
* Board logic must provide the sam_usbsuspend logic if the USBDEV driver is
* used. This function is called whenever the USB enters or leaves suspend mode.
* This is an opportunity for the board logic to shutdown clocks, power, etc.
* while the USB is suspended.
*
************************************************************************************/
void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H */

25
configs/sama5d3x-ek/README.txt
View File

@ -1220,6 +1220,27 @@ Configurations
Application Configuration -> NSH Library
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
10) Support the USB high-speed EHCI host driver can be enabled by changing
the NuttX configuration file as follows. If EHCI is enabled by itself,
Device Drivers -> USB Device Driver Support
CONFIG_USBDEV=y : Enable USB device support
CONFIG_USBDEV_DMA=y : Device uses DMA
CONFIG_USBDEV_DUALSPEED=y : Device support High and Full Speed
System Type -> ATSAMA5 Peripheral Support
CONFIG_SAMA5_UDPHS=y : Enable UDPHS High Speed USB device
Application Configuration -> NSH Library
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
You also need to select a device-side class driver for the USB device,
This will select the CDC/ACM serial device. Defaults for the other
options should be okay.
Device Drivers -> USB Device Driver Support
CONFIG_CDCACM=y : Enable the CDC/ACM device
STATUS:
2013-7-19: This configuration (as do the others) run at 396MHz.
The SAMA5D3 can run at 536MHz. I still need to figure out the
@ -1293,6 +1314,10 @@ Configurations
2013-8-28: EHCI is partially functional. It is able to mount a high-
speed USB FLASH drive using the Mass Storage Class (MSC) interface.
2013-8-31: Added description to add UDPHS high-speed USB device
support. That function is still, however, a long way from being
functional.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.