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With these tweaks to the clocking, the Teensy-3.1 NSH configuration is fully functional

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This commit is contained in:
Gregory Nutt 2015-06-11 09:07:35 -06:00
parent 73f43354a5
commit f4e8a5fb1d
2 changed files with 34 additions and 42 deletions
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38
configs/teensy-3.x/README.txt
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@ -3,7 +3,7 @@ README
This is a README file for the port of NuttX to the Teensy-3.1 from PJRC
(https://www.pjrc.com/). The Teensy-3.1 features the Freescale
MK30DX256VLH7 chip (now NXP). The MK30DX256VLH7 is a 64-pin Cortex-M4
MK20DX256VLH7 chip (now NXP). The MK20DX256VLH7 is a 64-pin Cortex-M4
running at 72MHz. It has 256KiB of program FLASH memory and 64KiB of
SRAM. For more information about the Teensy 3.1, see
@ -14,7 +14,7 @@ README
Teensy-3.0 has the same schematic (although some pins are not used on the
Teensy-3.0). The primary difference is that the Teensy 3.0 has a
MK20DX128VLH5 with slightly less capability. There are many difference
between the MK30DX256VLH7 and the MK20DX128VLH5 but the basic differences
between the MK20DX256VLH7 and the MK20DX128VLH5 but the basic differences
that effect how you configure NuttX are:
--------------- -------------- -------------- ---------------------------
@ -40,33 +40,16 @@ Contents
o Serial Console
o LEDs
o Using the Halfkey Loader
o Debugging
o Teensy-3.1 Configuration settings
o Configurations
STATUS
======
2005-06-10:
The board does not boot. I suspect that it is hanging very early in the
boot sequence, perhaps in the clock configuration. I am afraid that I
might have been overly optimistic in the compatibility of the K20 with
the (working) K40 and K60.
And, at this point, I don't know how to debug the board. There is no
way to connect a debuggger, at least not without cutting leads to the
the MINI54TAN device:
See: http://mcuoneclipse.com/2014/08/09/hacking-the-teensy-v3-1-for-swd-debugging/
Jakob Odersky's original NuttX port does work:
https://github.com/jodersky/nuttx/tree/teensy31-7.6
I do not yet discovered anything fundamentally different between the two
ports.
Oddly, I have seen a couple of builds work correctly (with BAUD 57600
and overclocked at 96MHz). But I have been unable to replicate that.
2005-06-11:
After some extended tinkering with the PLL setup, the Teensy-3.1 is
fully functional using the basic NSH configuration.
Pin Configuration
=================
@ -145,6 +128,15 @@ Using the Halfkey Loader
See https://www.pjrc.com/teensy/first_use.html
https://www.pjrc.com/teensy/loader_cli.html
Debugging
=========
And, at this point, I don't know how to debug the board. There is no
way to connect a JTAG SWD debuggger, at least not without cutting leads
to the the MINI54TAN device:
See: http://mcuoneclipse.com/2014/08/09/hacking-the-teensy-v3-1-for-swd-debugging/
Teensy-3.1 Configuration settings
=================================

38
configs/teensy-3.x/include/board.h
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@ -64,29 +64,29 @@
* is 72MHz and 50MHz for the MK20DX128VLH5, but according to the PJRC website,
* both can be overclocked at 96MHz
*
* 48MHz (rated 50MHz)
* MK20DX128VLH5 Rated Frequency 50MHz
*
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/1 = 16MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 8Mhz*3 = 72MHz
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*25 = 50MHz
* MCG Frequency: PLLOUT = 48MHz
*
* 72MHz
* MK20DX256VLH7 Rated Frequency 72MHz
*
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/2 = 8MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 8Mhz*9 = 72MHz
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*36 = 72MHz
* MCG Frequency: PLLOUT = 72MHz
*
* 96MHz (Overclocked)
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/1 = 16MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = 16Mhz*6 = 96MHz
* Board can be overclocked at 96MHz (per PJRC.com)
* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/8 = 2MHz
* PLL Output frequency: PLLOUT = PLLIN*VDIV = Mhz*48 = 96MHz
* MCG Frequency: PLLOUT = 96MHz
*/
#if defined(CONFIG_TEENSY_3X_OVERCLOCK)
/* PLL Configuration */
# define BOARD_PRDIV 1 /* PLL External Reference Divider */
# define BOARD_VDIV 6 /* PLL VCO Divider (frequency multiplier) */
# define BOARD_PRDIV 8 /* PLL External Reference Divider */
# define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */
/* SIM CLKDIV1 dividers */
@ -99,8 +99,8 @@
/* PLL Configuration */
# define BOARD_PRDIV 2 /* PLL External Reference Divider */
# define BOARD_VDIV 9 /* PLL VCO Divider (frequency multiplier) */
# define BOARD_PRDIV 8 /* PLL External Reference Divider */
# define BOARD_VDIV 36 /* PLL VCO Divider (frequency multiplier) */
/* SIM CLKDIV1 dividers */
@ -112,15 +112,15 @@
#elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
/* PLL Configuration */
# define BOARD_PRDIV 1 /* PLL External Reference Divider */
# define BOARD_VDIV 3 /* PLL VCO Divider (frequency multiplier) */
# define BOARD_PRDIV 8 /* PLL External Reference Divider */
# define BOARD_VDIV 25 /* PLL VCO Divider (frequency multiplier) */
/* SIM CLKDIV1 dividers */
# define BOARD_OUTDIV1 1 /* Core = MCG, 48MHz */
# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 48MHz */
# define BOARD_OUTDIV3 1 /* FlexBus = MCG/1, 48MHz */
# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 24MHz */
# define BOARD_OUTDIV1 1 /* Core = MCG, 50MHz */
# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 50MHz */
# define BOARD_OUTDIV3 1 /* FlexBus = MCG/1, 20MHz */
# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 25MHz */
#endif
#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV)