sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merged in david_s5/nuttx/master_h7 (pull request #1058)

Browse Source 
STM32H7:Flash driver and Serious BUG fixes.

* arch/arm/Kconfig:Add ARCH_HAVE_PROGMEM for STM32H7

* stm32h7:Add FLASH progmem support

* stm32h7:pwr add CPUCR & D3CR

* stm32h7:syscfg Add PWRCR

* stm32h7:rcc Properly configure VOS and Flash

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane 2019-10-22 19:49:49 +00:00 committed by Gregory Nutt
parent 7389f86561
commit f506e2bd72
8 changed files with 1152 additions and 230 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -344,6 +344,7 @@ config ARCH_CHIP_STM32H7
select ARCH_CORTEXM7 select ARCH_CORTEXM7
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
select ARCH_HAVE_PROGMEM
# select ARCH_HAVE_HEAPCHECK # select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED

23
arch/arm/src/stm32h7/Kconfig
View File

@ -39,6 +39,14 @@ config STM32H7_STM32H7X3XX
bool bool
default n default n
config STM32H7_FLASH_CONFIG_B
bool
default n
config STM32H7_FLASH_CONFIG_G
bool
default n
config STM32H7_FLASH_CONFIG_I config STM32H7_FLASH_CONFIG_I
bool bool
default n default n
@ -52,6 +60,8 @@ choice
letter that designates the FLASH size. letter that designates the FLASH size.
Designator Size in KiB Designator Size in KiB
B 128
G 1024
I 2048 I 2048
This configuration option defaults to using the configuration based This configuration option defaults to using the configuration based
@ -70,6 +80,12 @@ choice
config STM32H7_FLASH_OVERRIDE_DEFAULT config STM32H7_FLASH_OVERRIDE_DEFAULT
bool "Default" bool "Default"
config STM32H7_FLASH_OVERRIDE_B
bool "B 128KiB"
config STM32H7_FLASH_OVERRIDE_G
bool "G 1048KiB"
config STM32H7_FLASH_OVERRIDE_I config STM32H7_FLASH_OVERRIDE_I
bool "I 2048KiB" bool "I 2048KiB"
@ -91,6 +107,13 @@ config STM32H7_AXI_SRAM_CORRUPTION_WAR
AXI_TARG7_FN_MOD register. This will reduce the read issuing capability AXI_TARG7_FN_MOD register. This will reduce the read issuing capability
of the SRAM to 1 at AXI interconnect level and avoid data corruption. of the SRAM to 1 at AXI interconnect level and avoid data corruption.
config STM32H7_PROGMEM
bool "Flash progmem support"
default n
---help---
Add progmem support, start block and end block options are provided to
obtain an uniform flash memory mapping.
menu "STM32H7 Peripheral Selection" menu "STM32H7 Peripheral Selection"
# These "hidden" settings determine is a peripheral option is available for the # These "hidden" settings determine is a peripheral option is available for the

4
arch/arm/src/stm32h7/Make.defs
View File

@ -88,6 +88,10 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_STM32H7_PROGMEM),y)
CMN_CSRCS += stm32_flash.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c CMN_CSRCS += up_signal_dispatch.c

468
arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /******************************************************************************
* arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h * arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
* *
* Copyright (C) 2018 Gregory Nutt. All rights reserved. * Copyright (C) 2018 Gregory Nutt. All rights reserved.
@ -31,234 +31,318 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ *****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H #ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H #define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
/************************************************************************************ /******************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ *****************************************************************************/
/* Register Offsets *****************************************************************/ /* Register Offsets *****************************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000 /* Access control register */ #define STM32_FLASH_ACR_OFFSET 0x0000 /* Access control register */
#define STM32_FLASH_KEYR_OFFSET 0x0004 /* Key register */ #define STM32_FLASH_KEYR1_OFFSET 0x0004 /* Key register for bank 1 */
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 /* Option key register */ #define STM32_FLASH_OPTKEYR_OFFSET 0x0008 /* Option key register */
#define STM32_FLASH_CR_OFFSET 0x000c /* Control register */ #define STM32_FLASH_CR1_OFFSET 0x000c /* Control register for bank 1 */
#define STM32_FLASH_SR_OFFSET 0x0010 /* Status register */ #define STM32_FLASH_SR1_OFFSET 0x0010 /* Status register for bank 1 */
#define STM32_FLASH_CCR_OFFSET 0x0014 /* Clear control register */ #define STM32_FLASH_CCR1_OFFSET 0x0014 /* Clear control register for bank 1 */
#define STM32_FLASH_OPTCR_OFFSET 0x0018 /* Option control register */ #define STM32_FLASH_OPTCR_OFFSET 0x0018 /* Option control register */
#define STM32_FLASH_OPTSRCUR_OFFSET 0x001c /* Option status register (CUR) */ #define STM32_FLASH_OPTSR_CUR_OFFSET 0x001c /* Option status register (CUR) */
#define STM32_FLASH_OPTSRPRG_OFFSET 0x0020 /* Option status register (PRG) */ #define STM32_FLASH_OPTSR_PRG_OFFSET 0x0020 /* Option status register (PRG) */
#define STM32_FLASH_OPTCCR_OFFSET 0x0024 /* Option clear control register */ #define STM32_FLASH_OPTCCR_OFFSET 0x0024 /* Option clear control register */
#define STM32_FLASH_PRARCUR_OFFSET 0x0028 /* Protection address (CUR) */ #define STM32_FLASH_PRAR_CUR1_OFFSET 0x0028 /* Protection address for bank 1 */
#define STM32_FLASH_PRARPRG_OFFSET 0x002C /* Protection address (PRG) */ #define STM32_FLASH_PRAR_PRG1_OFFSET 0x002C /* Protection address for bank 1 */
#define STM32_FLASH_SCARCUR_OFFSET 0x0030 /* Secure address (CUR) */ #define STM32_FLASH_SCAR_CUR1_OFFSET 0x0030 /* Secure address for bank 1 (CUR) */
#define STM32_FLASH_SCARPRG_OFFSET 0x0034 /* Secure address (PRG) */ #define STM32_FLASH_SCAR_PRG1_OFFSET 0x0034 /* Secure address for bank 1 (PRG) */
#define STM32_FLASH_WPSNCUR_OFFSET 0x0038 /* Write sector protection (CUR) */ #define STM32_FLASH_WPSN_CUR1R_OFFSET 0x0038 /* Write sector protection for bank 1 (CUR) */
#define STM32_FLASH_WPSNPRG_OFFSET 0x003C /* Write sector protection (PRG) */ #define STM32_FLASH_WPSN_PRG1R_OFFSET 0x003C /* Write sector protection for bank 1 (PRG) */
#define STM32_FLASH_BOOTCUR_OFFSET 0x0040 /* Boot address (CUR) */ #define STM32_FLASH_BOOT_CUR_OFFSET 0x0040 /* Boot address (CUR) */
#define STM32_FLASH_BOOTPRGR_OFFSET 0x0044 /* Boot address (PRG) */ #define STM32_FLASH_BOOT_PRGR_OFFSET 0x0044 /* Boot address (PRG) */
#define STM32_FLASH_CRCCR_OFFSET 0x0050 /* CRC control register */ #define STM32_FLASH_CRCCR1_OFFSET 0x0050 /* CRC control register for bank 1 */
#define STM32_FLASH_CRCSADDR_OFFSET 0x0054 /* CRC start address register */ #define STM32_FLASH_CRCSADD1R_OFFSET 0x0054 /* CRC start address register for bank 1 */
#define STM32_FLASH_CRCEADDR_OFFSET 0x0058 /* CRC end address register */ #define STM32_FLASH_CRCEADD1R_OFFSET 0x0058 /* CRC end address register for bank 1 */
#define STM32_FLASH_CRCDATAR_OFFSET 0x005C /* CRC data register */ #define STM32_FLASH_CRCDATAR_OFFSET 0x005C /* CRC data register */
#define STM32_FLASH_ECCFAR_OFFSET 0x0060 /* ECC fail address */ #define STM32_FLASH_ECC_FA1R_OFFSET 0x0060 /* ECC fail address register for bank 1 */
#define STM32_FLASH_BANK1_OFFSET 0x0000 /* Bank 1 registers offset */ #define STM32_FLASH_KEYR2_OFFSET 0x0104 /* Key register for bank 2 */
#define STM32_FLASH_BANK2_OFFSET 0x0100 /* Bank 2 registers offset */ #define STM32_FLASH_CR2_OFFSET 0x010c /* Control register for bank 2 */
#define STM32_FLASH_SR2_OFFSET 0x0110 /* Status register for bank 2 */
#define STM32_FLASH_CCR2_OFFSET 0x0114 /* Clear control register for bank 2 */
#define STM32_FLASH_PRAR_CUR2_OFFSET 0x0128 /* Protection address for bank 2 */
#define STM32_FLASH_PRAR_PRG2_OFFSET 0x012C /* Protection address for bank 2 */
#define STM32_FLASH_SCAR_CUR2_OFFSET 0x0130 /* Secure address for bank 2 (CUR) */
#define STM32_FLASH_SCAR_PRG2_OFFSET 0x0134 /* Secure address for bank 2 (PRG) */
#define STM32_FLASH_WPSN_CUR2R_OFFSET 0x0138 /* Write sector protection for bank 2 (CUR) */
#define STM32_FLASH_WPSN_PRG2R_OFFSET 0x013C /* Write sector protection for bank 2 (PRG) */
#define STM32_FLASH_CRCCR2_OFFSET 0x0150 /* CRC control register for bank 2 */
#define STM32_FLASH_CRCSADD2R_OFFSET 0x0154 /* CRC start address register for bank 2 */
#define STM32_FLASH_CRCEADD2R_OFFSET 0x0158 /* CRC end address register for bank 2 */
#define STM32_FLASH_ECC_FA2R_OFFSET 0x0160 /* ECC fail address register for bank 2 */
#define STM32_FLASH_BANK1_OFFSET 0x0000 /* Bank 1 registers offset */
#define STM32_FLASH_BANK2_OFFSET 0x0100 /* Bank 2 registers offset */
/* Register Addresses ***************************************************************/ /* Register Addresses ***************************************************************/
#define STM32_FLASH_ACR (STM32_FLASH_BASE+STM32_FLASH_ACR_OFFSET) #define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_KEYR (STM32_FLASH_BASE+STM32_FLASH_KEYR_OFFSET) #define STM32_FLASH_KEYR1 (STM32_FLASHIF_BASE + STM32_FLASH_KEYR1_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASH_BASE+STM32_FLASH_OPTKEYR_OFFSET) #define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_CR (STM32_FLASH_BASE+STM32_FLASH_CR_OFFSET) #define STM32_FLASH_CR1 (STM32_FLASHIF_BASE + STM32_FLASH_CR1_OFFSET)
#define STM32_FLASH_SR (STM32_FLASH_BASE+STM32_FLASH_SR_OFFSET) #define STM32_FLASH_SR1 (STM32_FLASHIF_BASE + STM32_FLASH_SR1_OFFSET)
#define STM32_FLASH_CCR (STM32_FLASH_BASE+STM32_FLASH_CCR_OFFSET) #define STM32_FLASH_CCR1 (STM32_FLASHIF_BASE + STM32_FLASH_CCR1_OFFSET)
#define STM32_FLASH_OPTCR (STM32_FLASH_BASE+STM32_FLASH_OPTCR_OFFSET) #define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCR_OFFSET)
#define STM32_FLASH_OPTSRCUR (STM32_FLASH_BASE+STM32_FLASH_OPTSRCUR_OFFSET) #define STM32_FLASH_OPTSR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_CUR_OFFSET)
#define STM32_FLASH_OPTSRPRG (STM32_FLASH_BASE+STM32_FLASH_OPTSRPRG_OFFSET) #define STM32_FLASH_OPTSR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_PRG_OFFSET)
#define STM32_FLASH_OPTCCR (STM32_FLASH_BASE+STM32_FLASH_OPTCCR_OFFSET) #define STM32_FLASH_OPTCCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCCR_OFFSET)
#define STM32_FLASH_PRARCUR (STM32_FLASH_BASE+STM32_FLASH_PRARCUR_OFFSET) #define STM32_FLASH_PRAR_CUR1 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_CUR1_OFFSET)
#define STM32_FLASH_PRARPRG (STM32_FLASH_BASE+STM32_FLASH_PRARPRG_OFFSET) #define STM32_FLASH_PRAR_PRG1 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_PRG1_OFFSET)
#define STM32_FLASH_SCARCUR (STM32_FLASH_BASE+STM32_FLASH_SCARCUR_OFFSET) #define STM32_FLASH_SCAR_CUR1 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_CUR1_OFFSET)
#define STM32_FLASH_SCARPRG (STM32_FLASH_BASE+STM32_FLASH_SCARPRG_OFFSET) #define STM32_FLASH_SCAR_PRG1 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_PRG1_OFFSET)
#define STM32_FLASH_WPSNCUR (STM32_FLASH_BASE+STM32_FLASH_WPSNCUR_OFFSET) #define STM32_FLASH_WPSN_CUR1R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_CUR1R_OFFSET)
#define STM32_FLASH_BOOTCUR (STM32_FLASH_BASE+STM32_FLASH_BOOTCUR_OFFSET) #define STM32_FLASH_WPSN_PRG1R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_PRG1R_OFFSET)
#define STM32_FLASH_BOOTPRGR (STM32_FLASH_BASE+STM32_FLASH_BOOTPRGR_OFFSET) #define STM32_FLASH_BOOT_CUR (STM32_FLASHIF_BASE + STM32_FLASH_BOOT_CUR_OFFSET)
#define STM32_FLASH_CRCCR (STM32_FLASH_BASE+STM32_FLASH_CRCCR_OFFSET) #define STM32_FLASH_BOOT_PRGR (STM32_FLASHIF_BASE + STM32_FLASH_BOOT_PRGR_OFFSET)
#define STM32_FLASH_CRCSADDR (STM32_FLASH_BASE+STM32_FLASH_CRCSADDR_OFFSET) #define STM32_FLASH_CRCCR1 (STM32_FLASHIF_BASE + STM32_FLASH_CRCCR1_OFFSET)
#define STM32_FLASH_CRCEADDR (STM32_FLASH_BASE+STM32_FLASH_CRCEADDR_OFFSET) #define STM32_FLASH_CRCSADD1R (STM32_FLASHIF_BASE + STM32_FLASH_CRCSADD1R_OFFSET)
#define STM32_FLASH_CRCDATAR (STM32_FLASH_BASE+STM32_FLASH_CRCDATAR_OFFSET) #define STM32_FLASH_CRCEADD1R (STM32_FLASHIF_BASE + STM32_FLASH_CRCEADD1R_OFFSET)
#define STM32_FLASH_ECCFAR (STM32_FLASH_BASE+STM32_FLASH_ECCFAR_OFFSET) #define STM32_FLASH_CRCDATAR (STM32_FLASHIF_BASE + STM32_FLASH_CRCDATAR_OFFSET)
#define STM32_FLASH_ECC_FA1R (STM32_FLASHIF_BASE + STM32_FLASH_ECC_FA1R_OFFSET)
#define STM32_FLASH_KEYR2 (STM32_FLASHIF_BASE + STM32_FLASH_KEYR2_OFFSET)
#define STM32_FLASH_CR2 (STM32_FLASHIF_BASE + STM32_FLASH_CR2_OFFSET)
#define STM32_FLASH_SR2 (STM32_FLASHIF_BASE + STM32_FLASH_SR2_OFFSET)
#define STM32_FLASH_CCR2 (STM32_FLASHIF_BASE + STM32_FLASH_CCR2_OFFSET)
#define STM32_FLASH_PRAR_CUR2 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_CUR2_OFFSET)
#define STM32_FLASH_PRAR_PRG2 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_PRG2_OFFSET)
#define STM32_FLASH_SCAR_CUR2 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_CUR2_OFFSET)
#define STM32_FLASH_SCAR_PRG2 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_PRG2_OFFSET)
#define STM32_FLASH_WPSN_CUR2R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_CUR2R_OFFSET)
#define STM32_FLASH_WPSN_PRG2R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_PRG2R_OFFSET)
#define STM32_FLASH_CRCCR2 (STM32_FLASHIF_BASE + STM32_FLASH_CRCCR2_OFFSET)
#define STM32_FLASH_CRCSADD2R (STM32_FLASHIF_BASE + STM32_FLASH_CRCSADD2R_OFFSET)
#define STM32_FLASH_CRCEADD2R (STM32_FLASHIF_BASE + STM32_FLASH_CRCEADD2R_OFFSET)
#define STM32_FLASH_ECC_FA2R (STM32_FLASHIF_BASE + STM32_FLASH_ECC_FA2R_OFFSET)
/* Register Bitfield Definitions ****************************************************/ /* Register Bitfield Definitions ****************************************************/
/* Flash Access Control Register (ACR) */
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */ /* Flash Access Control Register (ACR) Bank 1 or 2 */
#define FLASH_ACR_LATENCY_MASK (15 << FLASH_ACR_LATENCY_SHIFT)
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */
# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */
# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
#define FLASH_ACR_WRHIGHFREQ_SHIFT (4) /* Bitd 4-5: Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_MASK (3 << FLASH_ACR_WRHIGHFREQ_SHIFT)
# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT)
/* Flash Control Register (CR) */ #define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */
#define FLASH_ACR_LATENCY_MASK (15 << FLASH_ACR_LATENCY_SHIFT)
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */
# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */
# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
#define FLASH_ACR_WRHIGHFREQ_SHIFT (4) /* Bitd 4-5: Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_MASK (3 << FLASH_ACR_WRHIGHFREQ_SHIFT)
# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT)
#define FLASH_CR_LOCK (1 << 0) /* Bit 0: Lock */ /* Flash Control Register (CR) Bank 1 or 2 (if different) */
#define FLASH_CR_PG (1 << 1) /* Bit 1: Progrramming */
#define FLASH_CR_SER (1 << 2) /* Bit 2: Sector erase */
#define FLASH_CR_BER (1 << 3) /* Bit 3: Bank erase */
#define FLASH_CR_PSIZE_SHIFT (4) /* Bits 4-5: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00: x8 */
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01: x16 */
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10: x32 */
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11: x64 */
#define FLASH_CR_FW (1 << 6) /* Bit 6: Force write */
#define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */
#define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */
#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..7 */
/* Bits 11-14: Reserved */
#define FLASH_CR_CRCEN (1 << 15) /* Bit 15: CRC control enable */
#define FLASH_CR_EOPIE (1 << 16) /* Bit 16: End-of-program interrupt enable */
#define FLASH_CR_WRPERRIE (1 << 17) /* Bit 17: Write protection error interrupt enable */
#define FLASH_CR_PGSERRIE (1 << 18) /* Bit 18: Programming sequence error interrupt enable */
#define FLASH_CR_STRBERRIE (1 << 19) /* Bit 19: Strobe error interrupt enable */
/* Bit 20: Reserver */
#define FLASH_CR_INCERRIE (1 << 21) /* Bit 21: Inconsistency error interrupt enbale */
#define FLASH_CR_OPERRIE (1 << 22) /* Bit 22: Write/erase error interrupt enable */
#define FLASH_CR_RDPERRIE (1 << 23) /* Bit 23: Read protection error interrupt enable */
#define FLASH_CR_RDSERRIE (1 << 24) /* Bit 24: Secure error interrupt enable */
#define FLASH_CR_SNECCERRIE (1 << 25) /* Bit 25: ECC single correction error interrupt enable */
#define FLASH_CR_DBECCERRIE (1 << 26) /* Bit 26: ECC double detection error interrupt enable */
#define FLASH_CR_CRCENDIE (1 << 27) /* Bit 27: CRC end of calculation interrupt enable */
/* Bits 28-31: Reserverd */
/* Flash Status Register (SR) */ #define FLASH_CR_LOCK (1 << 0) /* Bit 0: Lock */
#define FLASH_CR_PG (1 << 1) /* Bit 1: Programming */
#define FLASH_CR_SER (1 << 2) /* Bit 2: Sector erase */
#define FLASH_CR_BER (1 << 3) /* Bit 3: Bank erase */
#define FLASH_CR_PSIZE_SHIFT (4) /* Bits 4-5: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00: x8 */
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01: x16 */
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10: x32 */
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11: x64 */
#define FLASH_CR_FW (1 << 6) /* Bit 6: Force write */
#define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */
#define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */
#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..7 */
/* Bits 11-13: Reserved */
#define FLASH_CR_SPSS2 (1 << 14) /* Bit 14: Bank1 Reserved, Bank 2 special sector selection bit */
#define FLASH_CR_CRCEN (1 << 15) /* Bit 15: CRC control enable */
#define FLASH_CR_EOPIE (1 << 16) /* Bit 16: End-of-program interrupt enable */
#define FLASH_CR_WRPERRIE (1 << 17) /* Bit 17: Write protection error interrupt enable */
#define FLASH_CR_PGSERRIE (1 << 18) /* Bit 18: Programming sequence error interrupt enable */
#define FLASH_CR_STRBERRIE (1 << 19) /* Bit 19: Strobe error interrupt enable */
/* Bit 20: Reserved */
#define FLASH_CR_INCERRIE (1 << 21) /* Bit 21: Inconsistency error interrupt enbale */
#define FLASH_CR_OPERRIE (1 << 22) /* Bit 22: Write/erase error interrupt enable */
#define FLASH_CR_RDPERRIE (1 << 23) /* Bit 23: Read protection error interrupt enable */
#define FLASH_CR_RDSERRIE (1 << 24) /* Bit 24: Secure error interrupt enable */
#define FLASH_CR_SNECCERRIE (1 << 25) /* Bit 25: ECC single correction error interrupt enable */
#define FLASH_CR_DBECCERRIE (1 << 26) /* Bit 26: ECC double detection error interrupt enable */
#define FLASH_CR_CRCENDIE (1 << 27) /* Bit 27: CRC end of calculation interrupt enable */
/* Bits 28-31: Reserverd */
#define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */ /* Flash Status Register (SR) Bank 1 or 2 */
#define FLASH_SR_WBNE (1 << 1) /* Bit 1: write buffer not empty */
#define FLASH_SR_QW (1 << 2) /* Bit 2: wait queue flag */
#define FLASH_SR_CRCBUSY (1 << 3) /* Bit 3: CRC busy flag */
/* Bits 4-15: Reserved */
#define FLASH_SR_EOP (1 << 16) /* Bit 16: End of program */
#define FLASH_SR_WROERR (1 << 17) /* Bit 17: Write protection error */
#define FLASH_SR_PGSERR (1 << 18) /* Bit 18: Programming sequence error */
#define FLASH_SR_STRBERR (1 << 19) /* Bit 19: Strobe error */
/* Bit 20: Reserved */
#define FLASH_SR_INCERR (1 << 21) /* Bit 21: Inconsistency error */
#define FLASH_SR_OPERR (1 << 22) /* Bit 22: Write/erase error */
#define FLASH_SR_RDPERR (1 << 23) /* Bit 23: Read protection error */
#define FLASH_SR_RDSERR (1 << 24) /* Bit 24: Secure error */
#define FLASH_SR_SNECCERR (1 << 25) /* Bit 25: ECC single error */
#define FLASH_SR_DBECCERR (1 << 26) /* Bit 26: ECC double detection error */
#define FLASH_SR_CRCEND (1 << 27) /* Bit 27: CRC end of calculation */
/* Bits 28-31: Reserved */
/* Flash Clear control register */ #define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */
#define FLASH_SR_WBNE (1 << 1) /* Bit 1: write buffer not empty */
#define FLASH_SR_QW (1 << 2) /* Bit 2: wait queue flag */
#define FLASH_SR_CRCBUSY (1 << 3) /* Bit 3: CRC busy flag */
/* Bits 4-15: Reserved */
#define FLASH_SR_EOP (1 << 16) /* Bit 16: End of program */
#define FLASH_SR_WROERR (1 << 17) /* Bit 17: Write protection error */
#define FLASH_SR_PGSERR (1 << 18) /* Bit 18: Programming sequence error */
#define FLASH_SR_STRBERR (1 << 19) /* Bit 19: Strobe error */
/* Bit 20: Reserved */
#define FLASH_SR_INCERR (1 << 21) /* Bit 21: Inconsistency error */
#define FLASH_SR_OPERR (1 << 22) /* Bit 22: Write/erase error */
#define FLASH_SR_RDPERR (1 << 23) /* Bit 23: Read protection error */
#define FLASH_SR_RDSERR (1 << 24) /* Bit 24: Secure error */
#define FLASH_SR_SNECCERR (1 << 25) /* Bit 25: ECC single error */
#define FLASH_SR_DBECCERR (1 << 26) /* Bit 26: ECC double detection error */
#define FLASH_SR_CRCEND (1 << 27) /* Bit 27: CRC end of calculation */
/* Bits 28-31: Reserved */
/* Bits 0-15: Reserved */ /* Flash Clear control register Bank 1 or 2 */
#define FLASH_CLR_EOP (1 << 16) /* Bit 16: Clear end of program */
#define FLASH_CLR_WROERR (1 << 17) /* Bit 17: Clear write protection error */
#define FLASH_CLR_PGSERR (1 << 18) /* Bit 18: Clear programming sequence error */
#define FLASH_CLR_STRBERR (1 << 19) /* Bit 19: Clear strobe error */
/* Bit 20: Reserved */
#define FLASH_CLR_INCERR (1 << 21) /* Bit 21: Clear inconsistency error */
#define FLASH_CLR_OPERR (1 << 22) /* Bit 22: Clear write/erase error */
#define FLASH_CLR_RDPERR (1 << 23) /* Bit 23: Clear read protection error */
#define FLASH_CLR_RDSERR (1 << 24) /* Bit 24: Clear secure error */
#define FLASH_CLR_SNECCERR (1 << 25) /* Bit 25: Clear ECC single error */
#define FLASH_CLR_DBECCERR (1 << 26) /* Bit 26: Clear ECC double detection error */
#define FLASH_CLR_CRCEND (1 << 27) /* Bit 27: Clear CRC end of calculation */
/* Bits 28-31: Reserved */
/* Flash Option Control Register (OPTCR) */ /* Bits 0-15: Reserved */
#define FLASH_CLR_EOP (1 << 16) /* Bit 16: Clear end of program */
#define FLASH_CLR_WROERR (1 << 17) /* Bit 17: Clear write protection error */
#define FLASH_CLR_PGSERR (1 << 18) /* Bit 18: Clear programming sequence error */
#define FLASH_CLR_STRBERR (1 << 19) /* Bit 19: Clear strobe error */
/* Bit 20: Reserved */
#define FLASH_CLR_INCERR (1 << 21) /* Bit 21: Clear inconsistency error */
#define FLASH_CLR_OPERR (1 << 22) /* Bit 22: Clear write/erase error */
#define FLASH_CLR_RDPERR (1 << 23) /* Bit 23: Clear read protection error */
#define FLASH_CLR_RDSERR (1 << 24) /* Bit 24: Clear secure error */
#define FLASH_CLR_SNECCERR (1 << 25) /* Bit 25: Clear ECC single error */
#define FLASH_CLR_DBECCERR (1 << 26) /* Bit 26: Clear ECC double detection error */
#define FLASH_CLR_CRCEND (1 << 27) /* Bit 27: Clear CRC end of calculation */
/* Bits 28-31: Reserved */
#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ /* Flash Option Control Register (OPTCR) Bank 1 or 2 */
#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
/* Bits 2-3: Reserved */ #define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
#define FLASH_OPTCR_MER (1 << 4) /* Bit 4: Mass erase */ #define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
/* Bits 5-29: Reserved */ /* Bits 2-3: Reserved */
#define FLASH_OPTCR_CHANGEERRIE (1 << 30) /* Bit 30: Option byte change error interrupt enable */ #define FLASH_OPTCR_MER (1 << 4) /* Bit 4: Mass erase */
#define FLASH_OPTCR_SWAPBANK (1 << 31) /* Bit 31: Bank swapping */ /* Bits 5-29: Reserved */
#define FLASH_OPTCR_CHANGEERRIE (1 << 30) /* Bit 30: Option byte change error interrupt enable */
#define FLASH_OPTCR_SWAPBANK (1 << 31) /* Bit 31: Bank swapping */
/* Flash Option Status Register (OPTSR) */ /* Flash Option Status Register (OPTSR) */
#define FLASH_OPTSR_BUSYV (1 << 0) /* Bit 0: Option byte change busy */ #define FLASH_OPTSR_BUSYV (1 << 0) /* Bit 0: Option byte change busy */
/* Bit 1: Reserved */ /* Bit 1: Reserved */
#define FLASH_OPTSR_BORLEV_SHIFT (2) /* Bits 2-3: Brownout level option */ #define FLASH_OPTSR_BORLEV_SHIFT (2) /* Bits 2-3: Brownout level option */
#define FLASH_OPTSR_BORLEV_MASK (3 << FLASH_OPTSR_BORLEV_SHIFT) #define FLASH_OPTSR_BORLEV_MASK (3 << FLASH_OPTSR_BORLEV_SHIFT)
# define FLASH_OPTSR_BORLEV_0 (0 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_0 (0 << FLASH_OPTSR_BORLEV_SHIFT)
# define FLASH_OPTSR_BORLEV_1 (1 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_1 (1 << FLASH_OPTSR_BORLEV_SHIFT)
# define FLASH_OPTSR_BORLEV_2 (2 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_2 (2 << FLASH_OPTSR_BORLEV_SHIFT)
# define FLASH_OPTSR_BORLEV_3 (3 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_3 (3 << FLASH_OPTSR_BORLEV_SHIFT)
#define FLASH_OPTSR_IWDGSW (1 << 4) /* Bit 4: IWDG control mode */ #define FLASH_OPTSR_IWDGSW (1 << 4) /* Bit 4: IWDG control mode */
/* Bit 5: Reserved */ /* Bit 5: Reserved */
#define FLASH_OPTSR_NRSTSTOP (1 << 6) /* Bit 6: DStop entry reset */ #define FLASH_OPTSR_NRSTSTOP (1 << 6) /* Bit 6: DStop entry reset */
#define FLASH_OPTSR_NRSTSTDY (1 << 7) /* Bit 7: DStandby entry reset */ #define FLASH_OPTSR_NRSTSTDY (1 << 7) /* Bit 7: DStandby entry reset */
#define FLASH_OPTSR_RDP_SHIFT (8) /* Bits 8-15: Readout protection level */ #define FLASH_OPTSR_RDP_SHIFT (8) /* Bits 8-15: Readout protection level */
#define FLASH_OPTSR_RDP_MASK (0xff << FLASH_OPTSR_RDP_SHIFT) #define FLASH_OPTSR_RDP_MASK (0xff << FLASH_OPTSR_RDP_SHIFT)
# define FLASH_OPTSR_RDP(n) ((uint32_t)(n) << FLASH_OPTSR_RDP_SHIFT) # define FLASH_OPTSR_RDP(n) ((uint32_t)(n) << FLASH_OPTSR_RDP_SHIFT)
#define FLASH_OPTSR_IWDGFZSTOP (1 << 17) /* Bit 17: IWDG Stop mode freeze */ /* Bit 16: Reserved */
#define FLASH_OPTSR_IWDGFZSTBY (1 << 18) /* Bit 18: IWDG Standby mode freeze */ #define FLASH_OPTSR_IWDGFZSTOP (1 << 17) /* Bit 17: IWDG Stop mode freeze */
#define FLASH_OPTSR_STRAMSIZE_SHIFT (19) /* Bits 19-20: ST RAM size */ #define FLASH_OPTSR_IWDGFZSTBY (1 << 18) /* Bit 18: IWDG Standby mode freeze */
#define FLASH_OPTSR_STRAMSIZE_MASK (3 << FLASH_OPTSR_STRAMSIZE_SHIFT) #define FLASH_OPTSR_STRAMSIZE_SHIFT (19) /* Bits 19-20: ST RAM size */
# define FLASH_OPTSR_STRAMSIZE_2 (0 << FLASH_OPTSR_STRAMSIZE_SHIFT) #define FLASH_OPTSR_STRAMSIZE_MASK (3 << FLASH_OPTSR_STRAMSIZE_SHIFT)
# define FLASH_OPTSR_STRAMSIZE_4 (1 << FLASH_OPTSR_STRAMSIZE_SHIFT) # define FLASH_OPTSR_STRAMSIZE_2 (0 << FLASH_OPTSR_STRAMSIZE_SHIFT)
# define FLASH_OPTSR_STRAMSIZE_8 (2 << FLASH_OPTSR_STRAMSIZE_SHIFT) # define FLASH_OPTSR_STRAMSIZE_4 (1 << FLASH_OPTSR_STRAMSIZE_SHIFT)
# define FLASH_OPTSR_STRAMSIZE_16 (3 << FLASH_OPTSR_STRAMSIZE_SHIFT) # define FLASH_OPTSR_STRAMSIZE_8 (2 << FLASH_OPTSR_STRAMSIZE_SHIFT)
#define FLASH_OPTSR_SECURITY (1 << 21) /* Bit 21: Security enable*/ # define FLASH_OPTSR_STRAMSIZE_16 (3 << FLASH_OPTSR_STRAMSIZE_SHIFT)
/* Bits 22-28: Reserved */ #define FLASH_OPTSR_SECURITY (1 << 21) /* Bit 21: Security enable*/
#define FLASH_OPTSR_IOHSLV (1 << 29) /* Bit 29: IO high-speed at low-volateg */ /* Bits 22-28: Reserved */
#define FLASH_OPTSR_CHANGEERR (1 << 30) /* Bit 30: Option byte change error */ #define FLASH_OPTSR_IOHSLV (1 << 29) /* Bit 29: IO high-speed at low-volateg */
#define FLASH_OPTSR_SWAPBANK (1 << 31) /* Bit 31: Bank swapping status */ #define FLASH_OPTSR_CHANGEERR (1 << 30) /* Bit 30: Option byte change error */
#define FLASH_OPTSR_SWAPBANK (1 << 31) /* Bit 31: Bank swapping status */
/* Flash Option Clear Control Register (OPTCCR) */ /* Flash Option Clear Control Register (OPTCCR) */
/* Bits 0-29: Reserved */ /* Bits 0-29: Reserved */
#define FLASH_OPTCCR_OPTLOCK (1 << 30) /* Bit 30: OPTCHANGEERR reset */ #define FLASH_OPTCCR_OPTCHANGEERR (1 << 30) /* Bit 30: OPTCHANGEERR reset */
/* Bit 31: Reserved */ /* Bit 31: Reserved */
/* TODO: Flash Protection Address (PRAR) */ /* Flash Protection Address (PRAR) Bank 1 or 2 */
/* TODO: Flash Secure Address (SCAR) */ #define FLASH_PRAR_START_SHIFT (0) /* Bits 0-11 Bank PCROP area start status bits */
#define FLASH_PRAR_START_MASK (0xfff << FLASH_PRAR_START_SHIFT)
/* Bits 12-15: Reserved */
#define FLASH_PRAR_END_SHIFT (16) /* Bits 16-27 Bank PCROP area end configuration bits */
#define FLASH_PRAR_END_MASK (0xfff << FLASH_PRAR_END_SHIFT)
/* Bits 28-30: Reserved */
#define FLASH_PRAR_DMEP (1 << 31) /* Bit 31: Bank PCROP protected erase enable option configuration bit */
/* Flash Write Sector Protection (WPSN) */ /* Flash Secure Address (SCAR) Bank 1 or 2 */
#define FLASH_WPSN_WRPSN_SHIFT (0) /* Bits 0-7L Sector write protection option */ #define FLASH_SCAR_START_SHIFT (0) /* Bits 0-11 Bank secure-only area start status bits */
#define FLASH_WPSN_WRPSN_MASK (15 << FLASH_WPSN_WRPSN_SHIFT) #define FLASH_SCAR_START_MASK (0xfff << FLASH_SCAR_START_SHIFT)
/* Bits 8-31: Reserved */ /* Bits 12-15: Reserved */
#define FLASH_SCAR_END_SHIFT (16) /* Bits 16-27 Bank secure-only area end configuration bits */
#define FLASH_SCAR_END_MASK (0xfff << FLASH_SCAR_END_SHIFT)
/* Bits 28-30: Reserved */
#define FLASH_SCAR_DMES (1 << 31) /* Bit 31: Bank secure access protected erase enable option status bit */
/* Flash Register Boot Address (BOOT) */ /* Flash Write Sector Protection (WPSN) Bank 1 or 2 */
#define FLASH_BOOT_ADD0_SHIFT (0) /* Bits 0-15: Boot addres 0 */ #define FLASH_WPSN_WRPSN_SHIFT (0) /* Bits 0-7: Sector write protection option */
#define FLASH_BOOT_ADD0_MASK (0xff << FLASH_BOOT_ADD0_SHIFT) #define FLASH_WPSN_WRPSN_MASK (15 << FLASH_WPSN_WRPSN_SHIFT)
#define FLASH_BOOT_ADD1_SHIFT (16) /* Bits 16-31: Boot addres 1 */ /* Bits 8-31: Reserved */
#define FLASH_BOOT_ADD2_MASK (0xff << FLASH_BOOT_ADD2_SHIFT)
/* TODO: Flash CRC Control Register (CRCCR) */ /* Flash Register Boot Address (BOOT) Bank 1 or 2 */
/* TODO: Flash CRC Start Address Register (CRCSADDR) */ #define FLASH_BOOT_ADD0_SHIFT (0) /* Bits 0-15: Boot address 0 */
#define FLASH_BOOT_ADD0_MASK (0xffff << FLASH_BOOT_ADD0_SHIFT)
#define FLASH_BOOT_ADD1_SHIFT (16) /* Bits 16-31: Boot address 1 */
#define FLASH_BOOT_ADD1_MASK (0xffff << FLASH_BOOT_ADD1_SHIFT)
/* TODO: Flash CRC End Address Register (CRCSEDDR) */ /* Flash CRC Control Register (CRCCR) Bank 1 or 2 */
#define FLASH_CRCCR_CRC_SEC_SHIFT (0) /* Bits 0-2: Bank 1 CRC sector number */
#define FLASH_CRCCR_CRC_SEC_MASK (7 << FLASH_CRCCR_CRC_SEC_SHIFT)
/* Bits 3-6: Reserved */
#define FLASH_CRCCR_ALL_BANK (1 << 7) /* Bit 7: Bank CRC select bit */
#define FLASH_CRCCR_CRC_BY_SECT (1 << 8) /* Bit 9: Bank CRC sector mode select bit */
#define FLASH_CRCCR_ADD_SECT (1 << 9) /* Bit 9: Bank CRC sector select bit */
#define FLASH_CRCCR_CLEAN_SECT (1 << 10) /* Bit 10: Bank CRC sector list clear bit */
/* Bits 11-15: Reserved */
#define FLASH_CRCCR_START_CRC (1 << 16) /* Bit 16: Bank CRC start bit */
#define FLASH_CRCCR_CLEAN_CRC (1 << 17) /* Bit 16: Bank CRC clean bit */
#define FLASH_CRCCR_BURST_SHIFT (20) /* Bits 20-21: Bank CRC burst size */
#define FLASH_CRCCR_BURST_MASK (3 << FLASH_CRCCR_BURST_SHIFT)
# define FLASH_CRCCR_BURST_4 (0 << FLASH_CRCCR_BURST_SHIFT)
# define FLASH_CRCCR_BURST_16 (1 << FLASH_CRCCR_BURST_SHIFT)
# define FLASH_CRCCR_BURST_64 (2 << FLASH_CRCCR_BURST_SHIFT)
# define FLASH_CRCCR_BURST_256 (3 << FLASH_CRCCR_BURST_SHIFT)
/* Bits 22-31: Reserved */
/* Flash CRC Start Address Register (CRCSADDR) Bank 1 or 2 */
/* Bits 0-1: Reserved */
#define FLASH_CRCSADDR_START_SHIFT (2) /* Bits 2-19 CRC start address on bank */
#define FLASH_CRCSADDR_START_MASK (0x3ffff << FLASH_CRCSADDR_START_SHIFT)
/* Bits 20-31: Reserved */
/* Flash CRC End Address Register (CRCSEDDR) Bank 1 or 2 */
/* Bits 0-1: Reserved */
#define FLASH_CRCSEDDR_START_SHIFT (2) /* Bits 2-19 CRC end address on bank */
#define FLASH_CRCSEDDR_START_MASK (0x3ffff << FLASH_CRCSEDDR_START_SHIFT)
/* Bits 20-31: Reserved */
/* Flash ECC fail Address(FAnR) Bank 1 or 2 */
#define FLASH_ECC_FAR_SHIFT (0) /* Bits 0-14 Bank 1 ECC error add */
#define FLASH_ECC_FAR_MASK (0x7fff << FLASH_CRCSEDDR_START_SHIFT)
/* Bits 15-31: Reserved */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H */

72
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
View File

@ -1,8 +1,9 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h * arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
* *
* Copyright (C) 2018 Gregory Nutt. All rights reserved. * Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
* Authors: Mateusz Szafoni <raiden00@railab.me> * Authors: Mateusz Szafoni <raiden00@railab.me>
* David Sidrane <david.sidrane@nscdg.com>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -70,12 +71,12 @@
/* Power control register 1 (CR1) */ /* Power control register 1 (CR1) */
#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-power Deepsleep with SVOS3 */ #define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-power Deepsleep with SVOS3 */
/* Bits 1-3: Reserved */ /* Bits 1-3: Reserved */
#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Programmable voltage detector enable */ #define PWR_CR1_PVDE (1 << 4) /* Bit 4: Programmable voltage detector enable */
#define PWR_CR1_PLS_SHIFT (5) /* Bits 5-7: Programmable voltage detector level */ #define PWR_CR1_PLS_SHIFT (5) /* Bits 5-7: Programmable voltage detector level */
#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT) #define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT)
# define PWR_CR1_PLS_1V95 (0 << PWR_CR1_PLS_SHIFT) /* 000: */ # define PWR_CR1_PLS_1V95 (0 << PWR_CR1_PLS_SHIFT) /* 000: */
# define PWR_CR1_PLS_2V1 (1 << PWR_CR1_PLS_SHIFT) /* 001: */ # define PWR_CR1_PLS_2V1 (1 << PWR_CR1_PLS_SHIFT) /* 001: */
@ -85,39 +86,39 @@
# define PWR_CR1_PLS_2V7 (5 << PWR_CR1_PLS_SHIFT) /* 101: */ # define PWR_CR1_PLS_2V7 (5 << PWR_CR1_PLS_SHIFT) /* 101: */
# define PWR_CR1_PLS_2V85 (6 << PWR_CR1_PLS_SHIFT) /* 110: */ # define PWR_CR1_PLS_2V85 (6 << PWR_CR1_PLS_SHIFT) /* 110: */
# define PWR_CR1_PLS_EXT (7 << PWR_CR1_PLS_SHIFT) /* 111: */ # define PWR_CR1_PLS_EXT (7 << PWR_CR1_PLS_SHIFT) /* 111: */
#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable backup domain write protection */ #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable backup domain write protection */
#define PWR_CR1_FLPS (1 << 9) /* Bit 9: */ #define PWR_CR1_FLPS (1 << 9) /* Bit 9: */
/* Bits 10-13: Reserved */ /* Bits 10-13: Reserved */
#define PWR_CR1_SVOS_SHIFT (1 << 14) /* Bits 14-15: */ #define PWR_CR1_SVOS_SHIFT (1 << 14) /* Bits 14-15: */
#define PWR_CR1_SVOS_MASK (3 << PWR_CR1_SVOS_SHIFT) #define PWR_CR1_SVOS_MASK (3 << PWR_CR1_SVOS_SHIFT)
/* 00: Reserved */ /* 00: Reserved */
# define PWR_CR1_SVOS_S5 (1 << PWR_CR1_SVOS_SHIFT) /* 01: */ # define PWR_CR1_SVOS_S5 (1 << PWR_CR1_SVOS_SHIFT) /* 01: */
# define PWR_CR1_SVOS_S4 (2 << PWR_CR1_SVOS_SHIFT) /* 10: */ # define PWR_CR1_SVOS_S4 (2 << PWR_CR1_SVOS_SHIFT) /* 10: */
# define PWR_CR1_SVOS_S3 (3 << PWR_CR1_SVOS_SHIFT) /* 11: */ # define PWR_CR1_SVOS_S3 (3 << PWR_CR1_SVOS_SHIFT) /* 11: */
#define PWR_CR1_AVDEN (1 << 16) /* Bit 16: */ #define PWR_CR1_AVDEN (1 << 16) /* Bit 16: */
#define PWR_CR1_ALS_SHIFT (17) /* Bits 17-18: Analog voltage detector level selection */ #define PWR_CR1_ALS_SHIFT (17) /* Bits 17-18: Analog voltage detector level selection */
#define PWR_CR1_ALS_MASK (3 << PWR_CR1_ALS_SHIFT) #define PWR_CR1_ALS_MASK (3 << PWR_CR1_ALS_SHIFT)
# define PWR_CR1_ALS_1V7 (0 << PWR_CR1_ALS_SHIFT) /* 00: */ # define PWR_CR1_ALS_1V7 (0 << PWR_CR1_ALS_SHIFT) /* 00: */
# define PWR_CR1_ALS_2V1 (1 << PWR_CR1_ALS_SHIFT) /* 01 */ # define PWR_CR1_ALS_2V1 (1 << PWR_CR1_ALS_SHIFT) /* 01 */
# define PWR_CR1_ALS_2V5 (2 << PWR_CR1_ALS_SHIFT) /* 10: */ # define PWR_CR1_ALS_2V5 (2 << PWR_CR1_ALS_SHIFT) /* 10: */
# define PWR_CR1_ALS_2V8 (3 << PWR_CR1_ALS_SHIFT) /* 11: */ # define PWR_CR1_ALS_2V8 (3 << PWR_CR1_ALS_SHIFT) /* 11: */
/* Bits 19-31: Reserved */ /* Bits 19-31: Reserved */
/* Power control/status register 1 (CRS1) */ /* Power control/status register 1 (CRS1) */
/* Power control register 2 (CR2) */ /* Power control register 2 (CR2) */
#define PWR_CR2_BREN (1 << 0) /* Bit 0: Backup regulator enable */ #define PWR_CR2_BREN (1 << 0) /* Bit 0: Backup regulator enable */
/* Bits 1-3: Reserved */ /* Bits 1-3: Reserved */
#define PWR_CR2_MONEN (1 << 4) /* Bit 4: VBAT and temperature monitoring enable */ #define PWR_CR2_MONEN (1 << 4) /* Bit 4: VBAT and temperature monitoring enable */
/* Bits 5-15: Reserved */ /* Bits 5-15: Reserved */
#define PWR_CR2_BRRDY (1 << 16) /* Bit 16: Backup regulator ready */ #define PWR_CR2_BRRDY (1 << 16) /* Bit 16: Backup regulator ready */
/* Bits 17-19: Reserved */ /* Bits 17-19: Reserved */
#define PWR_CR2_VBATL (1 << 20) /* Bit 20: VBAT level monitoring versus low threshold */ #define PWR_CR2_VBATL (1 << 20) /* Bit 20: VBAT level monitoring versus low threshold */
#define PWR_CR2_VBATH (1 << 21) /* Bit 21: VBAT level monitoring versus high threshold */ #define PWR_CR2_VBATH (1 << 21) /* Bit 21: VBAT level monitoring versus high threshold */
#define PWR_CR2_TEMPL (1 << 22) /* Bit 22: Temperature level monitoring versus low threshold */ #define PWR_CR2_TEMPL (1 << 22) /* Bit 22: Temperature level monitoring versus low threshold */
#define PWR_CR2_TEMPH (1 << 23) /* Bit 23: Temperature level monitoring versus high threshold */ #define PWR_CR2_TEMPH (1 << 23) /* Bit 23: Temperature level monitoring versus high threshold */
/* Bits 24-31: Reserved */ /* Bits 24-31: Reserved */
/* Power control register 3 (CR3) */ /* Power control register 3 (CR3) */
@ -134,8 +135,33 @@
/* Power CPU control register (CPUCR) */ /* Power CPU control register (CPUCR) */
#define STM32_PWR_CPUCR_PDDS_D1 (1 << 0) /* Bit 0: D1 domain Power Down Deepsleep selection */
#define STM32_PWR_CPUCR_PDDS_D2 (1 << 1) /* Bit 1: D2 domain Power Down Deepsleep */
#define STM32_PWR_CPUCR_PDDS_D3 (1 << 2) /* Bit 2: System D3 domain Power Down Deepsleep */
/* Bits 3-4: Reserved */
#define STM32_PWR_CPUCR_STOPF (1 << 5) /* Bit 5: STOP flag */
#define STM32_PWR_CPUCR_SBF (1 << 6) /* Bit 6: System Standby flag */
#define STM32_PWR_CPUCR_SBF_D1 (1 << 7) /* Bit 7: D1 domain DStandby flag */
#define STM32_PWR_CPUCR_SBF_D2 (1 << 8) /* Bit 8: D2 domain DStandby flag */
#define STM32_PWR_CPUCR_CSSF (1 << 9) /* Bit 9: Clear Standby and Stop flags (always read as 0) */
/* Bit 10: Reserved */
#define STM32_PWR_CPUCR_RUN_D3 (1 << 11) /* Bit 11: Keep system D3 domain in Run mode regardless of the CPU subsystem modes */
/* Bits 12-31: Reserved */
/* Power D3 domain control register (D3CR) */ /* Power D3 domain control register (D3CR) */
/* Bits 0-12: Reserved */
#define STM32_PWR_D3CR_VOSRDY (1 << 13) /* Bit 13: */
#define STM32_PWR_D3CR_VOS_SHIFT (14) /* Bits 14-15: Voltage scaling selection according to performance */
#define STM32_PWR_D3CR_VOS_MASK (3 << STM32_PWR_D3CR_VOS_SHIFT)
# define PWR_D3CR_VOS_SCALE_3R (0 << STM32_PWR_D3CR_VOS_SHIFT) /* Fmax = 200MHz */
# define PWR_D3CR_VOS_SCALE_3 (1 << STM32_PWR_D3CR_VOS_SHIFT) /* Fmax = 200MHz */
# define PWR_D3CR_VOS_SCALE_2 (2 << STM32_PWR_D3CR_VOS_SHIFT) /* Fmax = 300MHz */
# define PWR_D3CR_VOS_SCALE_1 (3 << STM32_PWR_D3CR_VOS_SHIFT) /* Fmax = 400MHz */
# define PWR_D3CR_VOS_SCALE_0 (3 << STM32_PWR_D3CR_VOS_SHIFT) /* Fmax = 480MHz with ODN */
/* Bits 15-31: Reserved */
/* Power wakeup clear register (WKUPCR) */ /* Power wakeup clear register (WKUPCR) */
/* Power wakeup flag register (WKUPFR) */ /* Power wakeup flag register (WKUPFR) */

17
arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
View File

@ -1,9 +1,9 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h * arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
* *
* Copyright (C) 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org> * Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com> * David Sidrane <david.sidrane@nscdg.com>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -45,8 +45,6 @@
#include "chip.h" #include "chip.h"
#include "hardware/stm32_memorymap.h" #include "hardware/stm32_memorymap.h"
#if defined(CONFIG_STM32H7_STM32H7X3XX)
/**************************************************************************************************** /****************************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************************************/ ****************************************************************************************************/
@ -64,6 +62,7 @@
#define STM32_SYSCFG_CCSR_OFFSET 0x0020 /* Compensation cell control/status register */ #define STM32_SYSCFG_CCSR_OFFSET 0x0020 /* Compensation cell control/status register */
#define STM32_SYSCFG_CCVR_OFFSET 0x0024 /* Compensation cell value register */ #define STM32_SYSCFG_CCVR_OFFSET 0x0024 /* Compensation cell value register */
#define STM32_SYSCFG_CCCR_OFFSET 0x0028 /* Compensation cell code register */ #define STM32_SYSCFG_CCCR_OFFSET 0x0028 /* Compensation cell code register */
#define STM32_SYSCFG_PWRCR_OFFSET 0x002c /* Power Control register */
#define STM32_SYSCFG_PKGR_OFFSET 0x0124 /* Compensation cell code register */ #define STM32_SYSCFG_PKGR_OFFSET 0x0124 /* Compensation cell code register */
@ -99,6 +98,7 @@
#define STM32_SYSCFG_CCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCSR_OFFSET) #define STM32_SYSCFG_CCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCSR_OFFSET)
#define STM32_SYSCFG_CCVR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCVR_OFFSET) #define STM32_SYSCFG_CCVR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCVR_OFFSET)
#define STM32_SYSCFG_CCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCCR_OFFSET) #define STM32_SYSCFG_CCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_CCCR_OFFSET)
#define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/ /* Register Bitfield Definitions ********************************************************************/
@ -179,18 +179,26 @@
/* Compensation cell control/status register */ /* Compensation cell control/status register */
/* REVISIT: Missing bitfield definitions */ /* REVISIT: Missing bitfield definitions */
#define SYSCFG_CCSR_ #define SYSCFG_CCSR_
/* Compensation cell value register */ /* Compensation cell value register */
/* REVISIT: Missing bitfield definitions */ /* REVISIT: Missing bitfield definitions */
#define SYSCFG_CCVR_ #define SYSCFG_CCVR_
/* Compensation cell code register */ /* Compensation cell code register */
/* REVISIT: Missing bitfield definitions */ /* REVISIT: Missing bitfield definitions */
#define SYSCFG_CCCR_ #define SYSCFG_CCCR_
/* Power control register */
#define SYSCFG_PWRCR_ODEN (1 << 0) /* Bit 0: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode */
/* User registers 0-17 */ /* User registers 0-17 */
/* REVISIT: Missing bitfield definitions */ /* REVISIT: Missing bitfield definitions */
#define SYSCFG_UR0_ #define SYSCFG_UR0_
#define SYSCFG_UR2_ #define SYSCFG_UR2_
#define SYSCFG_UR3_ #define SYSCFG_UR3_
@ -209,5 +217,4 @@
#define SYSCFG_UR16_ #define SYSCFG_UR16_
#define SYSCFG_UR17_ #define SYSCFG_UR17_
#endif /* CONFIG_STM32H7_STM32H7X3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H */

703
arch/arm/src/stm32h7/stm32_flash.c Normal file
View File

@ -0,0 +1,703 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32h7_flash.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david.sidrane@nscdg.com>
*
* Ported from stm32f7_flash.c, this is the original license:
*
* Copyright (C) 2018 Wolpike LLC. All rights reserved.
* Author: Evgeniy Bobkov <evgen@wolpike.com>
*
* Ported from stm32f20xxf40xx_flash.c, this is the original license:
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*
* Requirements during write/erase operations on FLASH:
* - HSI must be ON.
* - Low Power Modes are not permitted during write/erase
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdbool.h>
#include <semaphore.h>
#include <assert.h>
#include <errno.h>
#include "barriers.h"
#include "hardware/stm32_flash.h"
#include "up_arch.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on the
* chip part number. This value can be overridden with
* CONFIG_STM32H7_FLASH_OVERRIDE_x
*
* Parts STM32H74xxE have 512Kb of FLASH
* Parts STM32H74xxG have 1024Kb of FLASH
* Parts STM32H74xxI have 2048Kb of FLASH
*
* N.B. Only Single bank mode is supported
*/
#define _K(x) ((x)*1024)
#define FLASH_SECTOR_SIZE _K(128)
#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \
!defined(CONFIG_STM32H7_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \
!defined(CONFIG_STM32H7_FLASH_CONFIG_I)
# define CONFIG_STM32H7_FLASH_OVERRIDE_B
# warning "Flash size not defined defaulting to 128KiB (B)"
#endif
#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32H7_FLASH_CONFIG_B
# undef CONFIG_STM32H7_FLASH_CONFIG_G
# undef CONFIG_STM32H7_FLASH_CONFIG_I
# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_B)
# define CONFIG_STM32H7_FLASH_CONFIG_B
# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_G)
# define CONFIG_STM32H7_FLASH_CONFIG_G
# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I)
# define CONFIG_STM32H7_FLASH_CONFIG_I
# endif
#endif
#if defined(CONFIG_STM32H7_FLASH_CONFIG_B)
# define STM32_FLASH_NPAGES 1
# define STM32_FLASH_SIZE _K(1 * 128)
#elif defined(CONFIG_STM32H7_FLASH_CONFIG_G)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_SIZE _K(8 * 128)
#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I)
# define STM32_FLASH_NPAGES 16
# define STM32_FLASH_SIZE _K(16 * 128)
#endif
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xcdef89ab
#define FLASH_OPTKEY1 0x08192a3b
#define FLASH_OPTKEY2 0x4c5d6e7f
#define FLASH_ERASEDVALUE 0xff
#define PROGMEM_NBLOCKS STM32_FLASH_NPAGES
/*****************************************************************************
* Private Types
****************************************************************************/
struct stm32h7_flash_priv_s
{
sem_t sem; /* Bank exclusive */
uint32_t ifbase; /* FLASHIF interface base address */
uint32_t base; /* FLASH base address */
uint32_t stblock; /* The first Block Number */
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct stm32h7_flash_priv_s stm32h7_flash_bank1_priv =
{
.sem = SEM_INITIALIZER(1),
.ifbase = STM32_FLASHIF_BASE + STM32_FLASH_BANK1_OFFSET,
.base = STM32_FLASH_BANK1,
.stblock = 0,
};
#if STM32_FLASH_NPAGES > 1
static struct stm32h7_flash_priv_s stm32h7_flash_bank2_priv =
{
.sem = SEM_INITIALIZER(1),
.ifbase = STM32_FLASHIF_BASE + STM32_FLASH_BANK2_OFFSET,
.base = STM32_FLASH_BANK2,
.stblock = PROGMEM_NBLOCKS / 2,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/*****************************************************************************
* Name: stm32h7_flash_getreg32
*
* Description:
* Get a 32-bit register value by offset
*
*****************************************************************************/
static inline uint32_t stm32h7_flash_getreg32(FAR struct stm32h7_flash_priv_s
*priv, uint8_t offset)
{
return getreg32(priv->ifbase + offset);
}
/*****************************************************************************
* Name: stm32h7_flash_putreg32
*
* Description:
* Put a 32-bit register value by offset
*
****************************************************************************/
static inline void stm32h7_flash_putreg32(FAR struct stm32h7_flash_priv_s
*priv, uint8_t offset,
uint32_t value)
{
putreg32(value, priv->ifbase + offset);
}
/*****************************************************************************
* Name: stm32h7_flash_modifyreg32
*
* Description:
* Modify a 32-bit register value by offset
*
*****************************************************************************/
static inline void stm32h7_flash_modifyreg32(FAR struct stm32h7_flash_priv_s
*priv, uint8_t offset,
uint32_t clearbits,
uint32_t setbits)
{
modifyreg32(priv->ifbase + offset, clearbits, setbits);
}
/*****************************************************************************
* Name: stm32h7_flash_sem_lock
*
* Description:
* Take the Bank exclusive access semaphore
*
*****************************************************************************/
static void stm32h7_flash_sem_lock(FAR struct stm32h7_flash_priv_s *priv)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = sem_wait(&priv->sem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
}
/*****************************************************************************
* Name: stm32h7_flash_sem_unlock
*
* Description:
* Release the Bank exclusive access semaphore
*
*****************************************************************************/
static inline void stm32h7_flash_sem_unlock(FAR struct stm32h7_flash_priv_s
*priv)
{
sem_post(&priv->sem);
}
/*****************************************************************************
* Name: stm32h7_unlock_flash
*
* Description:
* Unlock the Bank
*
*****************************************************************************/
static void stm32h7_unlock_flash(FAR struct stm32h7_flash_priv_s *priv)
{
while (stm32h7_flash_getreg32(priv, STM32_FLASH_SR1_OFFSET) & FLASH_SR_BSY)
{
}
if (stm32h7_flash_getreg32(priv, STM32_FLASH_CR1_OFFSET) & FLASH_CR_LOCK)
{
/* Unlock sequence */
stm32h7_flash_putreg32(priv, STM32_FLASH_KEYR1_OFFSET, FLASH_KEY1);
stm32h7_flash_putreg32(priv, STM32_FLASH_KEYR1_OFFSET, FLASH_KEY2);
}
}
/*****************************************************************************
* Name: stm32h7_lock_flash
*
* Description:
* Lock the Bank
*
*****************************************************************************/
static void stm32h7_lock_flash(FAR struct stm32h7_flash_priv_s *priv)
{
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, 0, FLASH_CR_LOCK);
}
/*****************************************************************************
* Name: stm32h7_flash_size
*
* Description:
* Returns the size in bytes of FLASH
*
*****************************************************************************/
static inline uint32_t stm32h7_flash_size(FAR struct stm32h7_flash_priv_s *priv)
{
return FLASH_SECTOR_SIZE * PROGMEM_NBLOCKS;
}
/*****************************************************************************
* Name: stm32h7_flash_bank
*
* Description:
* Returns the priv pointer to the correct bank
*
*****************************************************************************/
static inline
FAR struct stm32h7_flash_priv_s * stm32h7_flash_bank(size_t address)
{
struct stm32h7_flash_priv_s *priv = &stm32h7_flash_bank1_priv;
if (address < priv->base || address >= priv->base + stm32h7_flash_size(priv))
{
return NULL;
}
#if STM32_FLASH_NPAGES > 1
if (address >= stm32h7_flash_bank2_priv.base)
{
priv = &stm32h7_flash_bank2_priv;
}
#endif
return priv;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/*****************************************************************************
* Name: stm32h7_flash_unlock
*
* Description:
* Unlocks a bank
*
*****************************************************************************/
int stm32h7_flash_unlock(size_t addr)
{
int rv = -ENODEV;
struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr);
if (priv)
{
rv = OK;
stm32h7_flash_sem_lock(priv);
stm32h7_unlock_flash(priv);
stm32h7_flash_sem_unlock(priv);
}
return rv;
}
/*****************************************************************************
* Name: stm32h7_flash_lock
*
* Description:
* Locks a bank
*
*****************************************************************************/
int stm32h7_flash_lock(size_t addr)
{
int rv = -ENODEV;
struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr);
if (priv)
{
rv = OK;
stm32h7_flash_sem_lock(priv);
stm32h7_lock_flash(priv);
stm32h7_flash_sem_unlock(priv);
}
return rv;
}
/****************************************************************************
* Name: stm32h7_flash_writeprotect
*
* Description:
* Enable or disable the write protection of a flash sector.
*
****************************************************************************/
int stm32h7_flash_writeprotect(size_t block, bool enabled)
{
struct stm32h7_flash_priv_s *priv;
uint32_t setbits = 0;
uint32_t clearbits = 0;
int rv = -ENODEV;
if (block >= PROGMEM_NBLOCKS)
{
return -EFAULT;
}
priv = stm32h7_flash_bank(STM32_FLASH_BANK1 + (block * FLASH_SECTOR_SIZE));
if (priv)
{
if (enabled)
{
clearbits = 1 << block % (STM32_FLASH_NPAGES / 2);
}
else
{
setbits = 1 << block % (STM32_FLASH_NPAGES / 2);
}
stm32h7_flash_modifyreg32(priv, STM32_FLASH_WPSN_PRG1R_OFFSET,
clearbits, setbits);
rv = OK;
}
return rv;
}
size_t up_progmem_pagesize(size_t page)
{
return FLASH_SECTOR_SIZE;
}
ssize_t up_progmem_getpage(size_t addr)
{
struct stm32h7_flash_priv_s *priv;
priv = stm32h7_flash_bank(addr);
if (priv == NULL)
{
return -EFAULT;
}
return priv->stblock + ((addr - priv->base) / FLASH_SECTOR_SIZE);
}
size_t up_progmem_getaddress(size_t page)
{
struct stm32h7_flash_priv_s *priv;
if (page >= STM32_FLASH_NPAGES)
{
return SIZE_MAX;
}
priv = stm32h7_flash_bank(STM32_FLASH_BANK1 + (page * FLASH_SECTOR_SIZE));
return priv->base + (page - priv->stblock) * FLASH_SECTOR_SIZE;
}
size_t up_progmem_neraseblocks(void)
{
return PROGMEM_NBLOCKS;
}
bool up_progmem_isuniform(void)
{
return true;
}
ssize_t up_progmem_ispageerased(size_t page)
{
size_t addr;
size_t count;
size_t bwritten = 0;
if (page >= STM32_FLASH_NPAGES)
{
return -EFAULT;
}
/* Verify */
for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
count; count--, addr++)
{
if (getreg8(addr) != FLASH_ERASEDVALUE)
{
bwritten++;
}
}
return bwritten;
}
ssize_t up_progmem_eraseblock(size_t block)
{
struct stm32h7_flash_priv_s *priv;
if (block >= PROGMEM_NBLOCKS)
{
return -EFAULT;
}
priv = stm32h7_flash_bank(STM32_FLASH_BANK1 + (block * FLASH_SECTOR_SIZE));
stm32h7_flash_sem_lock(priv);
/* Get flash ready and begin erasing single block */
stm32h7_unlock_flash(priv);
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, 0, FLASH_CR_SER);
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, FLASH_CR_SNB_MASK,
FLASH_CR_SNB((block +
CONFIG_STM32H7_PROGMEM_STARTBLOCK)));
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, 0, FLASH_CR_START);
while (stm32h7_flash_getreg32(priv, STM32_FLASH_CR1_OFFSET) & FLASH_SR_BSY)
{
}
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, FLASH_CR_SER, 0);
stm32h7_flash_sem_unlock(priv);
/* Verify */
if (up_progmem_ispageerased(block) == 0)
{
return up_progmem_pagesize(block); /* success */
}
else
{
return -EIO; /* failure */
}
}
size_t up_progmem_erasesize(size_t block)
{
return FLASH_SECTOR_SIZE;
}
ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
{
struct stm32h7_flash_priv_s *priv;
uint64_t *fp;
uint64_t *rp;
uint8_t *byte = (uint8_t *) buf;
uint64_t *ll = (uint64_t *) buf;
size_t written = count;
const size_t blocksize = 32; /* 256 bit, 32 bytes per block */
const size_t llperblock = blocksize / sizeof(uint64_t);
size_t bcount = count / blocksize;
size_t remaining = count % blocksize;
priv = stm32h7_flash_bank(addr);
if (priv == NULL)
{
return -EFAULT;
}
/* Check for valid address range */
if (addr < priv->base ||
addr + count > priv->base + (STM32_FLASH_SIZE / 2))
{
return -EFAULT;
}
stm32h7_flash_sem_lock(priv);
/* Get flash ready and begin flashing */
stm32h7_unlock_flash(priv);
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, 0, FLASH_CR_PG);
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, FLASH_CR_PSIZE_MASK,
FLASH_CR_PSIZE_X64);
ARM_DSB();
ARM_ISB();
for (ll = (uint64_t *) buf; bcount;
bcount -= 1, ll += llperblock, addr += blocksize)
{
fp = (uint64_t *) addr;
rp = ll;
/* Write 4 64 bit word and wait to complete */
*fp++ = *rp++;
*fp++ = *rp++;
*fp++ = *rp++;
*fp++ = *rp++;
/* Data synchronous Barrier (DSB) just after the write operation. This
* will force the CPU to respect the sequence of instruction (no
* optimization).
*/
ARM_DSB();
ARM_ISB();
while (stm32h7_flash_getreg32(priv, STM32_FLASH_SR1_OFFSET) &
FLASH_SR_BSY)
{
}
/* Verify */
if (stm32h7_flash_getreg32(priv, STM32_FLASH_SR1_OFFSET) & FLASH_CR_SER)
{
written = -EROFS;
break;
}
else
{
fp = (uint64_t *) addr;
rp = ll;
if (*fp++ != *rp++ ||
*fp++ != *rp++ ||
*fp++ != *rp++ ||
*fp++ != *rp++)
{
written = -EIO;
break;
}
}
}
if (remaining)
{
for (byte = (uint8_t *) ll, count = remaining; count;
count -= 1, byte++, addr += 1)
{
/* Write the remaining */
putreg8(*byte, addr);
}
/* Data synchronous Barrier (DSB) just after the write operation. This
* will force the CPU to respect the sequence of instruction (no
* optimization).
*/
ARM_DSB();
ARM_ISB();
/* Force the fractional write */
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, 0, FLASH_CR_FW);
ARM_DSB();
ARM_ISB();
while (stm32h7_flash_getreg32(priv, STM32_FLASH_CR1_OFFSET) &
FLASH_CR_FW)
{
}
while (stm32h7_flash_getreg32(priv, STM32_FLASH_SR1_OFFSET) &
FLASH_SR_BSY)
{
}
/* Verify */
if (stm32h7_flash_getreg32(priv, STM32_FLASH_SR1_OFFSET) & FLASH_CR_SER)
{
written = -EROFS;
}
else
{
addr -= remaining;
for (byte = (uint8_t *) ll, count = remaining; count;
count -= 1, byte++, addr += 1)
{
if (getreg8(addr) != *byte)
{
written = -EIO;
break;
}
}
}
}
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, FLASH_CR_PG, 0);
stm32h7_flash_sem_unlock(priv);
return written;
}

94
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
View File

@ -41,6 +41,7 @@
#include "stm32_pwr.h" #include "stm32_pwr.h"
#include "hardware/stm32_axi.h" #include "hardware/stm32_axi.h"
#include "hardware/stm32_syscfg.h"
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@ -70,6 +71,31 @@
# error BOARD_FLASH_WAITSTATES is out of range # error BOARD_FLASH_WAITSTATES is out of range
#endif #endif
/* Voltage output scale (default to Scale 1 mode) */
#ifndef STM32_PWR_VOS_SCALE
# define STM32_PWR_VOS_SCALE PWR_D3CR_VOS_SCALE_1
#endif
#if !defined(BOARD_FLASH_PROGDELAY)
# if STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1
# if STM32_SYSCLK_FREQUENCY <= 70000000 && BOARD_FLASH_WAITSTATES == 0
# define BOARD_FLASH_PROGDELAY 0
# elif STM32_SYSCLK_FREQUENCY <= 140000000 && BOARD_FLASH_WAITSTATES == 1
# define BOARD_FLASH_PROGDELAY 10
# elif STM32_SYSCLK_FREQUENCY <= 185000000 && BOARD_FLASH_WAITSTATES == 2
# define BOARD_FLASH_PROGDELAY 1
# elif STM32_SYSCLK_FREQUENCY <= 210000000 && BOARD_FLASH_WAITSTATES == 2
# define BOARD_FLASH_PROGDELAY 2
# elif STM32_SYSCLK_FREQUENCY <= 225000000 && BOARD_FLASH_WAITSTATES == 3
# define BOARD_FLASH_PROGDELAY 2
# else
# define BOARD_FLASH_PROGDELAY 2
# endif
# endif
#endif
/* PLL are only enabled if the P,Q or R outputs are enabled. */ /* PLL are only enabled if the P,Q or R outputs are enabled. */
#undef USE_PLL1 #undef USE_PLL1
@ -748,19 +774,67 @@ static void stm32_stdclockconfig(void)
{ {
} }
#endif #endif
/* Configure FLASH wait states */
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); /* Ww must write the lower byte of the PWR_CR3 register is written once
* after POR and it shall be written before changing VOS level or ck_sys
#ifdef CONFIG_STM32H7_FLASH_ART_ACCELERATOR * clock frequency. No limitation applies to the upper bytes.
/* The Flash memory interface accelerates code execution with a system of *
* instruction prefetch and cache lines on ITCM interface (ART * Programming data corresponding to an invalid combination of
* Accelerator™). * LDOEN and BYPASS bits will be ignored: data will not be written,
* the written-once mechanism will lock the register and any further
* write access will be ignored. The default supply configuration will
* be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
* will go on indicating invalid voltage levels.
*
* N.B. The system shall be power cycled before writing a new value.
*/ */
regval |= FLASH_ACR_ARTEN; regval = getreg32(STM32_PWR_CR3);
regval |= FLASH_ACR_PRFTEN; regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_LDOESCUEN;
#endif putreg32(regval, STM32_PWR_CR3);
/* Set the voltage output scale */
regval = getreg32(STM32_PWR_D3CR);
regval &= ~STM32_PWR_D3CR_VOS_MASK;
regval |= STM32_PWR_VOS_SCALE;
putreg32(regval, STM32_PWR_D3CR);
while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0)
{
}
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
* over 400 Mhz.
*/
if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
STM32_SYSCLK_FREQUENCY > 400000000)
{
/* Enable System configuration controller clock to Enable ODEN */
regval = getreg32(STM32_RCC_APB4ENR);
regval |= RCC_APB4ENR_SYSCFGEN;
putreg32(regval, STM32_RCC_APB4ENR);
/* Enable Overdrive to extend the clock frequency up to 480 Mhz. */
regval = getreg32(STM32_SYSCFG_PWRCR);
regval |= SYSCFG_PWRCR_ODEN;
putreg32(regval, STM32_SYSCFG_PWRCR);
while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0)
{
}
}
/* Configure FLASH wait states */
regval = FLASH_ACR_WRHIGHFREQ(BOARD_FLASH_PROGDELAY) |
FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
putreg32(regval, STM32_FLASH_ACR); putreg32(regval, STM32_FLASH_ACR);