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FLASH waiting cycles are configured based on HCLK.

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This commit is contained in:
Fotis Panagiotopoulos 2020-10-30 14:24:24 +02:00 committed by David Sidrane
parent 32b49e6db8
commit f538839720
6 changed files with 136 additions and 40 deletions
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31
arch/arm/src/stm32/stm32f10xxx_rcc.c
View File

@ -49,6 +49,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* The FLASH latency depends on the system clock.
*
* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
#if (STM32_SYSCLK_FREQUENCY <= 24000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
#elif (STM32_SYSCLK_FREQUENCY <= 78000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
#else
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -522,16 +540,11 @@ static void stm32_stdclockconfig(void)
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Set flash wait states
* Sysclk runs with 72MHz -> 2 waitstates.
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
/* Enable prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set up PLL input scaling (with source = PLL2) */
@ -687,11 +700,11 @@ static void stm32_stdclockconfig(void)
#ifndef CONFIG_STM32_VALUELINE
/* Enable FLASH prefetch buffer and 2 wait states */
/* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif

25
arch/arm/src/stm32/stm32f20xxx_rcc.c
View File

@ -55,6 +55,27 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* The FLASH latency depends on the system clock.
*
* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
* 0WS from 0-30MHz
* 1WS from 30-60MHz
* 2WS from 60-90MHz
* 3WS from 90-120MHz
*/
#if (STM32_SYSCLK_FREQUENCY <= 30000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
#elif (STM32_SYSCLK_FREQUENCY <= 60000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
#elif (STM32_SYSCLK_FREQUENCY <= 90000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
#elif (STM32_SYSCLK_FREQUENCY <= 120000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_3
#else
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -646,10 +667,10 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
/* Enable FLASH prefetch, instruction cache, data cache,
* and 5 wait states.
* and set FLASH wait states.
*/
regval = (FLASH_ACR_LATENCY_5
regval = (FLASH_ACR_LATENCY_SETTING
#ifdef CONFIG_STM32_FLASH_ICACHE
| FLASH_ACR_ICEN
#endif

31
arch/arm/src/stm32/stm32f30xxx_rcc.c
View File

@ -49,6 +49,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* The FLASH latency depends on the system clock.
*
* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
#if (STM32_SYSCLK_FREQUENCY <= 24000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
#else
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -431,16 +449,11 @@ static void stm32_stdclockconfig(void)
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Set flash wait states
* Sysclk runs with 72MHz -> 2 waitstates.
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
/* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set up PLL input scaling (with source = PLL2) */
@ -594,11 +607,11 @@ static void stm32_stdclockconfig(void)
#ifndef CONFIG_STM32_VALUELINE
/* Value-line devices don't implement flash prefetch/waitstates */
/* Enable FLASH prefetch buffer and 2 wait states */
/* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif

36
arch/arm/src/stm32/stm32f33xxx_rcc.c
View File

@ -50,6 +50,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* The FLASH latency depends on the system clock.
*
* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
#if (STM32_SYSCLK_FREQUENCY <= 24000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
#else
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -435,25 +453,11 @@ static void stm32_stdclockconfig(void)
#endif
/* Set flash wait states according to sysclk:
*
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
/* Enable FLASH prefetch and wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~(FLASH_ACR_LATENCY_MASK);
#if STM32_SYSCLK_FREQUENCY <= 24000000
regval |= FLASH_ACR_LATENCY_0;
#elif STM32_SYSCLK_FREQUENCY <= 48000000
regval |= FLASH_ACR_LATENCY_1;
#else
regval |= FLASH_ACR_LATENCY_2;
#endif
regval |= FLASH_ACR_PRTFBE;
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Select the system clock source (probably the PLL) */

22
arch/arm/src/stm32/stm32f37xxx_rcc.c
View File

@ -50,6 +50,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* The FLASH latency depends on the system clock.
*
* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
#if (STM32_SYSCLK_FREQUENCY <= 24000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
#else
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -527,11 +545,11 @@ static void stm32_stdclockconfig(void)
# endif
/* Enable FLASH prefetch buffer and 2 wait states */
/* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set the HCLK source/divider */

31
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -68,6 +68,33 @@
#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
/* The FLASH latency depends on the system clock.
*
* Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
* 0WS from 0-30MHz
* 1WS from 30-60MHz
* 2WS from 60-90MHz
* 3WS from 90-120MHz
* 4WS from 120-150MHz
* 5WS from 150-180MHz
*/
#if (STM32_SYSCLK_FREQUENCY <= 30000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
#elif (STM32_SYSCLK_FREQUENCY <= 60000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
#elif (STM32_SYSCLK_FREQUENCY <= 90000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
#elif (STM32_SYSCLK_FREQUENCY <= 120000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_3
#elif (STM32_SYSCLK_FREQUENCY <= 150000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_4
#elif (STM32_SYSCLK_FREQUENCY <= 180000000)
# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_5
#else
# error "STM32_SYSCLK_FREQUENCY is out of range!"
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -778,10 +805,10 @@ static void stm32_stdclockconfig(void)
#endif
/* Enable FLASH prefetch, instruction cache, data cache,
* and 5 wait states.
* and set FLASH wait states.
*/
regval = (FLASH_ACR_LATENCY_5
regval = (FLASH_ACR_LATENCY_SETTING
#ifdef CONFIG_STM32_FLASH_ICACHE
| FLASH_ACR_ICEN
#endif