From f546801fb32bd5219cb856fd54fde36ade0036c1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 23 Jan 2019 11:48:50 -0600 Subject: [PATCH] Squashed commit of the following: arch/arm/src/tiva/hardware: Add CC13xx SMPH and AUX SMPH header files. Still need DDI0 OSC header file for CC13x0 compilation. arch/arm/src/tiva/cc13xx: A few changes toward getting the launchxl-cc1310/nsh configuration to build --- arch/arm/Kconfig | 1 - arch/arm/src/tiva/cc13xx/cc13x0_rom.h | 74 ++++- .../src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h | 4 +- .../src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h | 4 +- .../tiva/hardware/cc13x0/cc13x0_adi4_aux.h | 2 +- .../tiva/hardware/cc13x0/cc13x0_aux_smph.h | 104 +++++++ .../src/tiva/hardware/cc13x0/cc13x0_prcm.h | 1 + .../src/tiva/hardware/cc13x0/cc13x0_smph.h | 269 ++++++++++++++++++ .../cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h | 104 +++++++ .../cc13x2_cc26x2/cc13x2_cc26x2_smph.h | 269 ++++++++++++++++++ arch/arm/src/tiva/hardware/tiva_aux_smph.h | 73 +++++ arch/arm/src/tiva/hardware/tiva_smph.h | 73 +++++ configs/launchxl-cc1310/README.txt | 3 +- configs/launchxl-cc1310/nsh/defconfig | 3 +- configs/launchxl-cc1312r1/nsh/defconfig | 2 +- 15 files changed, 972 insertions(+), 14 deletions(-) create mode 100644 arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h create mode 100644 arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h create mode 100644 arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h create mode 100644 arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h create mode 100644 arch/arm/src/tiva/hardware/tiva_aux_smph.h create mode 100644 arch/arm/src/tiva/hardware/tiva_smph.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0c6f145467..8b8d3af60c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -285,7 +285,6 @@ config ARCH_CHIP_SIMPLELINK bool "TI SimpleLink" select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED - select ARCH_HAVE_FPU select ARCH_HAVE_FETCHADD depends on EXPERIMENTAL ---help--- diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_rom.h b/arch/arm/src/tiva/cc13xx/cc13x0_rom.h index c53ce3b6ef..b76141e293 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x0_rom.h @@ -41,11 +41,22 @@ #ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H #define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "hardware/tiva_aux_smph.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Start address of the ROM hard API access table (located after the ROM FW rev field) */ +/* Start address of the ROM hard API access table (located after the ROM FW rev + * field) + */ #define ROM_HAPI_TABLE_ADDR 0x10000048 @@ -65,11 +76,16 @@ /* REVISIT: In the TI Driverlib, the following go through a "Safe" layer */ -#define hapi_source_safeswitch() P_HARD_API->hf_source_safeswitch() -#define hapi_select_compa_input(a) P_HARD_API->select_compa_input(a) -#define hapi_select_compa_ref(a) P_HARD_API->select_compa_ref(a) -#define hapi_select_adc_compb_input(a) P_HARD_API->select_adc_compb_input(a) -#define hapi_select_adc_compb_ref(a) P_HARD_API->select_adc_compb_ref(a) +#define hapi_source_safeswitch() \ + rom_hapi_void(P_HARD_API->hf_source_safe_switch) +#define hapi_select_compa_input(a) \ + rom_hapi_auxadiselect(P_HARD_API->select_compa_input,(a)) +#define hapi_select_compa_ref(a) \ + rom_hapi_auxadiselect(P_HARD_API->select_compa_ref,(a)) +#define hapi_select_adc_compb_input(a) \ + rom_hapi_auxadiselect(P_HARD_API->select_adc_compb_input,(a)) +#define hapi_select_adc_compb_ref(a) \ + rom_hapi_auxadiselect(P_HARD_API->select_adc_compb_iref,(a)) /* Defines for input parameter to the hapi_select_compa_input function. * The define values can not be changed! @@ -643,6 +659,11 @@ typedef void (*fptr_adccompbin_t) (uint8_t /* signal */); typedef void (*fptr_compbref_t) (uint8_t /* signal */); +/* Types used in the "Safe" interfaces taken from the TI DriverLib hw_types.h */ + +typedef void (*fptr_void_void_t) (void); +typedef void (*fptr_void_uint8_t) (uint8_t); + /* ROM Hard-API access table type */ struct hard_api_s @@ -712,7 +733,7 @@ void rom_setup_aonrtc_subsecinc(uint32_t subsecinc); * vddrtrim - VDDR_TRIM setting * * Returned Value: - * Returns sign extended VDDR_TRIM setting. + * Returns sign extended VDDR_TRIM setting. * ************************************************************************************/ @@ -731,5 +752,44 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) return signed_vaddrtrim; } +/************************************************************************************ + * Name: rom_hapi_void and rom_hapi_auxadiselect + * + * Description: + * Work-arounds for bus arbitration issue. + * REVISIT: Originally for the adi.h header file in the TI DriverLib + * + * Input Parameters + * fptr - Function pointer + * + * Returned Value: + * None + * + ************************************************************************************/ + +inline static void rom_hapi_void(fptr_void_void_t fptr) +{ + irqstate_t flags = enter_critical_section(); + while (getreg32(TIVA_AUX_SMPH_SMPH0) == 0) + { + } + + fptr(); + putreg32(1, TIVA_AUX_SMPH_SMPH0); + leave_critical_section(flags); +} + +inline static void rom_hapi_auxadiselect(fptr_void_uint8_t fptr, uint8_t signal) +{ + irqstate_t flags = enter_critical_section(); + while (getreg32(TIVA_AUX_SMPH_SMPH0) == 0) + { + } + + fptr(signal); + putreg32(1, TIVA_AUX_SMPH_SMPH0); + leave_critical_section(flags); +} + #endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H */ diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h index 403d361485..e0f5fb37f8 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h @@ -45,7 +45,9 @@ * Pre-processor Definitions ************************************************************************************/ -/* Start address of the ROM hard API access table (located after the ROM FW rev field) */ +/* Start address of the ROM hard API access table (located after the ROM FW rev + * field) + */ #define ROM_HAPI_TABLE_ADDR 0x10000048 diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h index fc85b572f8..f2ef525839 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h @@ -45,7 +45,9 @@ * Pre-processor Definitions ************************************************************************************/ -/* Start address of the ROM hard API access table (located after the ROM FW rev field) */ +/* Start address of the ROM hard API access table (located after the ROM FW rev + * field) + */ #define ROM_HAPI_TABLE_ADDR 0x10000048 diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h index e0a89ee53e..0eef8d1dc6 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h @@ -114,7 +114,7 @@ # define ADI4_AUX_MUX1_COMPA_IN_AUXIO5 (4 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) # define ADI4_AUX_MUX1_COMPA_IN_AUXIO4 (8 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) # define ADI4_AUX_MUX1_COMPA_IN_AUXIO3 (16 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) -# define ADI4_AUX_MUX1_COMPA_IN_AUXIO1 (32 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) +# define ADI4_AUX_MUX1_COMPA_IN_AUXIO2 (32 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) # define ADI4_AUX_MUX1_COMPA_IN_AUXIO1 (64 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) # define ADI4_AUX_MUX1_COMPA_IN_AUXIO0 (128 << ADI4_AUX_MUX1_COMPA_IN_SHIFT) diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h new file mode 100644 index 0000000000..54bec0b455 --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_SMPH_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_SMPH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AUX SMPH Register Offsets ************************************************/ + +#define TIVA_AUX_SMPH_SMPH_OFFSET (0x0000 + ((n) << 2) +# define TIVA_AUX_SMPH_SMPH0_OFFSET 0x0000 /* Semaphore 0 */ +# define TIVA_AUX_SMPH_SMPH1_OFFSET 0x0004 /* Semaphore 1 */ +# define TIVA_AUX_SMPH_SMPH2_OFFSET 0x0008 /* Semaphore 2 */ +# define TIVA_AUX_SMPH_SMPH3_OFFSET 0x000c /* Semaphore 3 */ +# define TIVA_AUX_SMPH_SMPH4_OFFSET 0x0010 /* Semaphore 4 */ +# define TIVA_AUX_SMPH_SMPH5_OFFSET 0x0014 /* Semaphore 5 */ +# define TIVA_AUX_SMPH_SMPH6_OFFSET 0x0018 /* Semaphore 6 */ +# define TIVA_AUX_SMPH_SMPH7_OFFSET 0x001c /* Semaphore 7 */ +#define TIVA_AUX_SMPH_AUTOTAKE_OFFSET 0x0020 /* Auto Take */ + +/* AUX SMPH Register Addresses **********************************************/ + +#define TIVA_AUX_SMPH_SMPH(n) (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH_OFFSET(n)) +# define TIVA_AUX_SMPH_SMPH0 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH0_OFFSET) +# define TIVA_AUX_SMPH_SMPH1 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH1_OFFSET) +# define TIVA_AUX_SMPH_SMPH2 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH2_OFFSET) +# define TIVA_AUX_SMPH_SMPH3 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH3_OFFSET) +# define TIVA_AUX_SMPH_SMPH4 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH4_OFFSET) +# define TIVA_AUX_SMPH_SMPH5 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH5_OFFSET) +# define TIVA_AUX_SMPH_SMPH6 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH6_OFFSET) +# define TIVA_AUX_SMPH_SMPH7 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH7_OFFSET) +#define TIVA_AUX_SMPH_AUTOTAKE (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_AUTOTAKE_OFFSET) + +/* AUX SMPH Register Bitfield Definitions **(********************************/ + +/* TIVA_AUX_SMPH_SMPH0-TIVA_AUX_SMPH_SMPH7 */ + +#define AUX_SMPH_SMPH_STAT (1 << 0) /* Bit 0: Semaphore granted */ +# define AUX_SMPH_SMPH0_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH1_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH2_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH3_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH4_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH5_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH6_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH7_STAT AUX_SMPH_SMPH_STAT + +/* TIVA_AUX_SMPH_AUTOTAKE */ + +#define AUX_SMPH_AUTOTAKE_SMPH_ID_SHIFT (0) /* Bits 0-7: Write the semaphore + * ID 0-7 to SMPH_ID to request + * semaphore until AUX_EVCTL:EVSTAT3. + * AUX_SMPH_AUTOTAKE_DONE */ +#define AUX_SMPH_AUTOTAKE_SMPH_ID_MASK (7 << AUX_SMPH_AUTOTAKE_SMPH_ID_SHIFT) +# define AUX_SMPH_AUTOTAKE_SMPH_ID(n) ((uint32_t)(n) << AUX_SMPH_AUTOTAKE_SMPH_ID_SHIFT) + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h index 176d0052fd..6d3cc49489 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h @@ -46,6 +46,7 @@ ****************************************************************************************************/ #include +#include "hardware/tiva_memorymap.h" /**************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h new file mode 100644 index 0000000000..ce03aea264 --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h @@ -0,0 +1,269 @@ +/**************************************************************************** + * arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_SMPH_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_SMPH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SMPH Register Offsets ****************************************************/ + +#define TIVA_SMPH_SMPH_OFFSET(n) (0x0000 + ((n) << 2)) +# define TIVA_SMPH_SMPH0_OFFSET 0x0000 /* MCU SEMAPHORE 0 */ +# define TIVA_SMPH_SMPH1_OFFSET 0x0004 /* MCU SEMAPHORE 1 */ +# define TIVA_SMPH_SMPH2_OFFSET 0x0008 /* MCU SEMAPHORE 2 */ +# define TIVA_SMPH_SMPH3_OFFSET 0x000c /* MCU SEMAPHORE 3 */ +# define TIVA_SMPH_SMPH4_OFFSET 0x0010 /* MCU SEMAPHORE 4 */ +# define TIVA_SMPH_SMPH5_OFFSET 0x0014 /* MCU SEMAPHORE 5 */ +# define TIVA_SMPH_SMPH6_OFFSET 0x0018 /* MCU SEMAPHORE 6 */ +# define TIVA_SMPH_SMPH7_OFFSET 0x001c /* MCU SEMAPHORE 7 */ +# define TIVA_SMPH_SMPH8_OFFSET 0x0020 /* MCU SEMAPHORE 8 */ +# define TIVA_SMPH_SMPH9_OFFSET 0x0024 /* MCU SEMAPHORE 9 */ +# define TIVA_SMPH_SMPH10_OFFSET 0x0028 /* MCU SEMAPHORE 10 */ +# define TIVA_SMPH_SMPH11_OFFSET 0x002c /* MCU SEMAPHORE 11 */ +# define TIVA_SMPH_SMPH12_OFFSET 0x0030 /* MCU SEMAPHORE 12 */ +# define TIVA_SMPH_SMPH13_OFFSET 0x0034 /* MCU SEMAPHORE 13 */ +# define TIVA_SMPH_SMPH14_OFFSET 0x0038 /* MCU SEMAPHORE 14 */ +# define TIVA_SMPH_SMPH15_OFFSET 0x003c /* MCU SEMAPHORE 15 */ +# define TIVA_SMPH_SMPH16_OFFSET 0x0040 /* MCU SEMAPHORE 16 */ +# define TIVA_SMPH_SMPH17_OFFSET 0x0044 /* MCU SEMAPHORE 17 */ +# define TIVA_SMPH_SMPH18_OFFSET 0x0048 /* MCU SEMAPHORE 18 */ +# define TIVA_SMPH_SMPH19_OFFSET 0x004c /* MCU SEMAPHORE 19 */ +# define TIVA_SMPH_SMPH20_OFFSET 0x0050 /* MCU SEMAPHORE 20 */ +# define TIVA_SMPH_SMPH21_OFFSET 0x0054 /* MCU SEMAPHORE 21 */ +# define TIVA_SMPH_SMPH22_OFFSET 0x0058 /* MCU SEMAPHORE 22 */ +# define TIVA_SMPH_SMPH23_OFFSET 0x005c /* MCU SEMAPHORE 23 */ +# define TIVA_SMPH_SMPH24_OFFSET 0x0060 /* MCU SEMAPHORE 24 */ +# define TIVA_SMPH_SMPH25_OFFSET 0x0064 /* MCU SEMAPHORE 25 */ +# define TIVA_SMPH_SMPH26_OFFSET 0x0068 /* MCU SEMAPHORE 26 */ +# define TIVA_SMPH_SMPH27_OFFSET 0x006c /* MCU SEMAPHORE 27 */ +# define TIVA_SMPH_SMPH28_OFFSET 0x0070 /* MCU SEMAPHORE 28 */ +# define TIVA_SMPH_SMPH29_OFFSET 0x0074 /* MCU SEMAPHORE 29 */ +# define TIVA_SMPH_SMPH30_OFFSET 0x0078 /* MCU SEMAPHORE 30 */ +# define TIVA_SMPH_SMPH31_OFFSET 0x007c /* MCU SEMAPHORE 31 */ + +#define TIVA_SMPH_PEEK_OFFSET(n) (0x0800 + ((n) << 2)) +# define TIVA_SMPH_PEEK0_OFFSET 0x0800 /* MCU SEMAPHORE 0 ALIAS */ +# define TIVA_SMPH_PEEK1_OFFSET 0x0804 /* MCU SEMAPHORE 1 ALIAS */ +# define TIVA_SMPH_PEEK2_OFFSET 0x0808 /* MCU SEMAPHORE 2 ALIAS */ +# define TIVA_SMPH_PEEK3_OFFSET 0x080c /* MCU SEMAPHORE 3 ALIAS */ +# define TIVA_SMPH_PEEK4_OFFSET 0x0810 /* MCU SEMAPHORE 4 ALIAS */ +# define TIVA_SMPH_PEEK5_OFFSET 0x0814 /* MCU SEMAPHORE 5 ALIAS */ +# define TIVA_SMPH_PEEK6_OFFSET 0x0818 /* MCU SEMAPHORE 6 ALIAS */ +# define TIVA_SMPH_PEEK7_OFFSET 0x081c /* MCU SEMAPHORE 7 ALIAS */ +# define TIVA_SMPH_PEEK8_OFFSET 0x0820 /* MCU SEMAPHORE 8 ALIAS */ +# define TIVA_SMPH_PEEK9_OFFSET 0x0824 /* MCU SEMAPHORE 9 ALIAS */ +# define TIVA_SMPH_PEEK10_OFFSET 0x0828 /* MCU SEMAPHORE 10 ALIAS */ +# define TIVA_SMPH_PEEK11_OFFSET 0x082c /* MCU SEMAPHORE 11 ALIAS */ +# define TIVA_SMPH_PEEK12_OFFSET 0x0830 /* MCU SEMAPHORE 12 ALIAS */ +# define TIVA_SMPH_PEEK13_OFFSET 0x0834 /* MCU SEMAPHORE 13 ALIAS */ +# define TIVA_SMPH_PEEK14_OFFSET 0x0838 /* MCU SEMAPHORE 14 ALIAS */ +# define TIVA_SMPH_PEEK15_OFFSET 0x083c /* MCU SEMAPHORE 15 ALIAS */ +# define TIVA_SMPH_PEEK16_OFFSET 0x0840 /* MCU SEMAPHORE 16 ALIAS */ +# define TIVA_SMPH_PEEK17_OFFSET 0x0844 /* MCU SEMAPHORE 17 ALIAS */ +# define TIVA_SMPH_PEEK18_OFFSET 0x0848 /* MCU SEMAPHORE 18 ALIAS */ +# define TIVA_SMPH_PEEK19_OFFSET 0x084c /* MCU SEMAPHORE 19 ALIAS */ +# define TIVA_SMPH_PEEK20_OFFSET 0x0850 /* MCU SEMAPHORE 20 ALIAS */ +# define TIVA_SMPH_PEEK21_OFFSET 0x0854 /* MCU SEMAPHORE 21 ALIAS */ +# define TIVA_SMPH_PEEK22_OFFSET 0x0858 /* MCU SEMAPHORE 22 ALIAS */ +# define TIVA_SMPH_PEEK23_OFFSET 0x085c /* MCU SEMAPHORE 23 ALIAS */ +# define TIVA_SMPH_PEEK24_OFFSET 0x0860 /* MCU SEMAPHORE 24 ALIAS */ +# define TIVA_SMPH_PEEK25_OFFSET 0x0864 /* MCU SEMAPHORE 25 ALIAS */ +# define TIVA_SMPH_PEEK26_OFFSET 0x0868 /* MCU SEMAPHORE 26 ALIAS */ +# define TIVA_SMPH_PEEK27_OFFSET 0x086c /* MCU SEMAPHORE 27 ALIAS */ +# define TIVA_SMPH_PEEK28_OFFSET 0x0870 /* MCU SEMAPHORE 28 ALIAS */ +# define TIVA_SMPH_PEEK29_OFFSET 0x0874 /* MCU SEMAPHORE 29 ALIAS */ +# define TIVA_SMPH_PEEK30_OFFSET 0x0878 /* MCU SEMAPHORE 30 ALIAS */ +# define TIVA_SMPH_PEEK31_OFFSET 0x087c /* MCU SEMAPHORE 31 ALIAS */ + +/* SMPH Register Addresses **************************************************/ + +#define TIVA_SMPH_SMPH(n) (TIVA_SMPH_BASE + TIVA_SMPH_SMPH_OFFSET(n)) +# define TIVA_SMPH_SMPH0 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH0_OFFSET) +# define TIVA_SMPH_SMPH1 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH1_OFFSET) +# define TIVA_SMPH_SMPH2 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH2_OFFSET) +# define TIVA_SMPH_SMPH3 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH3_OFFSET) +# define TIVA_SMPH_SMPH4 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH4_OFFSET) +# define TIVA_SMPH_SMPH5 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH5_OFFSET) +# define TIVA_SMPH_SMPH6 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH6_OFFSET) +# define TIVA_SMPH_SMPH7 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH7_OFFSET) +# define TIVA_SMPH_SMPH8 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH8_OFFSET) +# define TIVA_SMPH_SMPH9 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH9_OFFSET) +# define TIVA_SMPH_SMPH10 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH10_OFFSET) +# define TIVA_SMPH_SMPH11 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH11_OFFSET) +# define TIVA_SMPH_SMPH12 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH12_OFFSET) +# define TIVA_SMPH_SMPH13 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH13_OFFSET) +# define TIVA_SMPH_SMPH14 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH14_OFFSET) +# define TIVA_SMPH_SMPH15 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH15_OFFSET) +# define TIVA_SMPH_SMPH16 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH16_OFFSET) +# define TIVA_SMPH_SMPH17 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH17_OFFSET) +# define TIVA_SMPH_SMPH18 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH18_OFFSET) +# define TIVA_SMPH_SMPH19 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH19_OFFSET) +# define TIVA_SMPH_SMPH20 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH20_OFFSET) +# define TIVA_SMPH_SMPH21 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH21_OFFSET) +# define TIVA_SMPH_SMPH22 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH22_OFFSET) +# define TIVA_SMPH_SMPH23 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH23_OFFSET) +# define TIVA_SMPH_SMPH24 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH24_OFFSET) +# define TIVA_SMPH_SMPH25 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH25_OFFSET) +# define TIVA_SMPH_SMPH26 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH26_OFFSET) +# define TIVA_SMPH_SMPH27 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH27_OFFSET) +# define TIVA_SMPH_SMPH28 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH28_OFFSET) +# define TIVA_SMPH_SMPH29 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH29_OFFSET) +# define TIVA_SMPH_SMPH30 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH30_OFFSET) +# define TIVA_SMPH_SMPH31 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH31_OFFSET) + +#define TIVA_SMPH_PEEK(n) (TIVA_SMPH_BASE + TIVA_SMPH_PEEK_OFFSET(n)) +# define TIVA_SMPH_PEEK0 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK0_OFFSET) +# define TIVA_SMPH_PEEK1 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK1_OFFSET) +# define TIVA_SMPH_PEEK2 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK2_OFFSET) +# define TIVA_SMPH_PEEK3 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK3_OFFSET) +# define TIVA_SMPH_PEEK4 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK4_OFFSET) +# define TIVA_SMPH_PEEK5 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK5_OFFSET) +# define TIVA_SMPH_PEEK6 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK6_OFFSET) +# define TIVA_SMPH_PEEK7 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK7_OFFSET) +# define TIVA_SMPH_PEEK8 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK8_OFFSET) +# define TIVA_SMPH_PEEK9 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK9_OFFSET) +# define TIVA_SMPH_PEEK10 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK10_OFFSET) +# define TIVA_SMPH_PEEK11 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK11_OFFSET) +# define TIVA_SMPH_PEEK12 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK12_OFFSET) +# define TIVA_SMPH_PEEK13 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK13_OFFSET) +# define TIVA_SMPH_PEEK14 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK14_OFFSET) +# define TIVA_SMPH_PEEK15 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK15_OFFSET) +# define TIVA_SMPH_PEEK16 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK16_OFFSET) +# define TIVA_SMPH_PEEK17 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK17_OFFSET) +# define TIVA_SMPH_PEEK18 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK18_OFFSET) +# define TIVA_SMPH_PEEK19 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK19_OFFSET) +# define TIVA_SMPH_PEEK20 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK20_OFFSET) +# define TIVA_SMPH_PEEK21 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK21_OFFSET) +# define TIVA_SMPH_PEEK22 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK22_OFFSET) +# define TIVA_SMPH_PEEK23 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK23_OFFSET) +# define TIVA_SMPH_PEEK24 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK24_OFFSET) +# define TIVA_SMPH_PEEK25 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK25_OFFSET) +# define TIVA_SMPH_PEEK26 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK26_OFFSET) +# define TIVA_SMPH_PEEK27 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK27_OFFSET) +# define TIVA_SMPH_PEEK28 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK28_OFFSET) +# define TIVA_SMPH_PEEK29 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK29_OFFSET) +# define TIVA_SMPH_PEEK30 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK30_OFFSET) +# define TIVA_SMPH_PEEK31 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK31_OFFSET) + +/* SMPH Register Bitfield Definitions ***************************************/ + +/* TIVA_SMPH_SMPH0-TIVA_SMPH_SMPH31 */ + +#define SMPH_SMPH_STAT (1 << 0) /* Bit 0: Semaphore is available */ +# define SMPH_SMPH0_STAT SMPH_SMPH_STAT +# define SMPH_SMPH1_STAT SMPH_SMPH_STAT +# define SMPH_SMPH2_STAT SMPH_SMPH_STAT +# define SMPH_SMPH3_STAT SMPH_SMPH_STAT +# define SMPH_SMPH4_STAT SMPH_SMPH_STAT +# define SMPH_SMPH5_STAT SMPH_SMPH_STAT +# define SMPH_SMPH6_STAT SMPH_SMPH_STAT +# define SMPH_SMPH7_STAT SMPH_SMPH_STAT +# define SMPH_SMPH8_STAT SMPH_SMPH_STAT +# define SMPH_SMPH9_STAT SMPH_SMPH_STAT +# define SMPH_SMPH10_STAT SMPH_SMPH_STAT +# define SMPH_SMPH11_STAT SMPH_SMPH_STAT +# define SMPH_SMPH12_STAT SMPH_SMPH_STAT +# define SMPH_SMPH13_STAT SMPH_SMPH_STAT +# define SMPH_SMPH14_STAT SMPH_SMPH_STAT +# define SMPH_SMPH15_STAT SMPH_SMPH_STAT +# define SMPH_SMPH16_STAT SMPH_SMPH_STAT +# define SMPH_SMPH17_STAT SMPH_SMPH_STAT +# define SMPH_SMPH18_STAT SMPH_SMPH_STAT +# define SMPH_SMPH19_STAT SMPH_SMPH_STAT +# define SMPH_SMPH20_STAT SMPH_SMPH_STAT +# define SMPH_SMPH21_STAT SMPH_SMPH_STAT +# define SMPH_SMPH22_STAT SMPH_SMPH_STAT +# define SMPH_SMPH23_STAT SMPH_SMPH_STAT +# define SMPH_SMPH24_STAT SMPH_SMPH_STAT +# define SMPH_SMPH25_STAT SMPH_SMPH_STAT +# define SMPH_SMPH26_STAT SMPH_SMPH_STAT +# define SMPH_SMPH27_STAT SMPH_SMPH_STAT +# define SMPH_SMPH28_STAT SMPH_SMPH_STAT +# define SMPH_SMPH29_STAT SMPH_SMPH_STAT +# define SMPH_SMPH30_STAT SMPH_SMPH_STAT +# define SMPH_SMPH31_STAT SMPH_SMPH_STAT + +/* TIVA_SMPH_PEEK0-TIVA_SMPH_PEEK31 */ + +#define SMPH_PEEK_STAT (1 << 0) /* Bit 0: Semaphore is available */ +# define SMPH_PEEK0_STAT SMPH_PEEK_STAT +# define SMPH_PEEK1_STAT SMPH_PEEK_STAT +# define SMPH_PEEK2_STAT SMPH_PEEK_STAT +# define SMPH_PEEK3_STAT SMPH_PEEK_STAT +# define SMPH_PEEK4_STAT SMPH_PEEK_STAT +# define SMPH_PEEK5_STAT SMPH_PEEK_STAT +# define SMPH_PEEK6_STAT SMPH_PEEK_STAT +# define SMPH_PEEK7_STAT SMPH_PEEK_STAT +# define SMPH_PEEK8_STAT SMPH_PEEK_STAT +# define SMPH_PEEK9_STAT SMPH_PEEK_STAT +# define SMPH_PEEK10_STAT SMPH_PEEK_STAT +# define SMPH_PEEK11_STAT SMPH_PEEK_STAT +# define SMPH_PEEK12_STAT SMPH_PEEK_STAT +# define SMPH_PEEK13_STAT SMPH_PEEK_STAT +# define SMPH_PEEK14_STAT SMPH_PEEK_STAT +# define SMPH_PEEK15_STAT SMPH_PEEK_STAT +# define SMPH_PEEK16_STAT SMPH_PEEK_STAT +# define SMPH_PEEK17_STAT SMPH_PEEK_STAT +# define SMPH_PEEK18_STAT SMPH_PEEK_STAT +# define SMPH_PEEK19_STAT SMPH_PEEK_STAT +# define SMPH_PEEK20_STAT SMPH_PEEK_STAT +# define SMPH_PEEK21_STAT SMPH_PEEK_STAT +# define SMPH_PEEK22_STAT SMPH_PEEK_STAT +# define SMPH_PEEK23_STAT SMPH_PEEK_STAT +# define SMPH_PEEK24_STAT SMPH_PEEK_STAT +# define SMPH_PEEK25_STAT SMPH_PEEK_STAT +# define SMPH_PEEK26_STAT SMPH_PEEK_STAT +# define SMPH_PEEK27_STAT SMPH_PEEK_STAT +# define SMPH_PEEK28_STAT SMPH_PEEK_STAT +# define SMPH_PEEK29_STAT SMPH_PEEK_STAT +# define SMPH_PEEK30_STAT SMPH_PEEK_STAT +# define SMPH_PEEK31_STAT SMPH_PEEK_STAT + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h new file mode 100644 index 0000000000..47716cb1b7 --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SMPH_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SMPH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AUX SMPH Register Offsets ************************************************/ + +#define TIVA_AUX_SMPH_SMPH_OFFSET (0x0000 + ((n) << 2) +# define TIVA_AUX_SMPH_SMPH0_OFFSET 0x0000 /* Semaphore 0 */ +# define TIVA_AUX_SMPH_SMPH1_OFFSET 0x0004 /* Semaphore 1 */ +# define TIVA_AUX_SMPH_SMPH2_OFFSET 0x0008 /* Semaphore 2 */ +# define TIVA_AUX_SMPH_SMPH3_OFFSET 0x000c /* Semaphore 3 */ +# define TIVA_AUX_SMPH_SMPH4_OFFSET 0x0010 /* Semaphore 4 */ +# define TIVA_AUX_SMPH_SMPH5_OFFSET 0x0014 /* Semaphore 5 */ +# define TIVA_AUX_SMPH_SMPH6_OFFSET 0x0018 /* Semaphore 6 */ +# define TIVA_AUX_SMPH_SMPH7_OFFSET 0x001c /* Semaphore 7 */ +#define TIVA_AUX_SMPH_AUTOTAKE_OFFSET 0x0020 /* Auto Take */ + +/* AUX SMPH Register Addresses **********************************************/ + +#define TIVA_AUX_SMPH_SMPH(n) (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH_OFFSET(n)) +# define TIVA_AUX_SMPH_SMPH0 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH0_OFFSET) +# define TIVA_AUX_SMPH_SMPH1 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH1_OFFSET) +# define TIVA_AUX_SMPH_SMPH2 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH2_OFFSET) +# define TIVA_AUX_SMPH_SMPH3 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH3_OFFSET) +# define TIVA_AUX_SMPH_SMPH4 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH4_OFFSET) +# define TIVA_AUX_SMPH_SMPH5 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH5_OFFSET) +# define TIVA_AUX_SMPH_SMPH6 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH6_OFFSET) +# define TIVA_AUX_SMPH_SMPH7 (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_SMPH7_OFFSET) +#define TIVA_AUX_SMPH_AUTOTAKE (TIVA_AUX_SMPH_BASE + TIVA_AUX_SMPH_AUTOTAKE_OFFSET) + +/* AUX SMPH Register Bitfield Definitions **(********************************/ + +/* TIVA_AUX_SMPH_SMPH0-TIVA_AUX_SMPH_SMPH7 */ + +#define AUX_SMPH_SMPH_STAT (1 << 0) /* Bit 0: Semaphore granted */ +# define AUX_SMPH_SMPH0_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH1_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH2_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH3_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH4_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH5_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH6_STAT AUX_SMPH_SMPH_STAT +# define AUX_SMPH_SMPH7_STAT AUX_SMPH_SMPH_STAT + +/* TIVA_AUX_SMPH_AUTOTAKE */ + +#define AUX_SMPH_AUTOTAKE_SMPH_ID_SHIFT (0) /* Bits 0-7: Write the semaphore + * ID 0-7 to SMPH_ID to request + * semaphore until AUX_EVCTL:EVSTAT3. + * AUX_SMPH_AUTOTAKE_DONE */ +#define AUX_SMPH_AUTOTAKE_SMPH_ID_MASK (7 << AUX_SMPH_AUTOTAKE_SMPH_ID_SHIFT) +# define AUX_SMPH_AUTOTAKE_SMPH_ID(n) ((uint32_t)(n) << AUX_SMPH_AUTOTAKE_SMPH_ID_SHIFT) + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h new file mode 100644 index 0000000000..0226c53896 --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h @@ -0,0 +1,269 @@ +/**************************************************************************** + * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_SMPH_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_SMPH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SMPH Register Offsets ****************************************************/ + +#define TIVA_SMPH_SMPH_OFFSET(n) (0x0000 + ((n) << 2)) +# define TIVA_SMPH_SMPH0_OFFSET 0x0000 /* MCU SEMAPHORE 0 */ +# define TIVA_SMPH_SMPH1_OFFSET 0x0004 /* MCU SEMAPHORE 1 */ +# define TIVA_SMPH_SMPH2_OFFSET 0x0008 /* MCU SEMAPHORE 2 */ +# define TIVA_SMPH_SMPH3_OFFSET 0x000c /* MCU SEMAPHORE 3 */ +# define TIVA_SMPH_SMPH4_OFFSET 0x0010 /* MCU SEMAPHORE 4 */ +# define TIVA_SMPH_SMPH5_OFFSET 0x0014 /* MCU SEMAPHORE 5 */ +# define TIVA_SMPH_SMPH6_OFFSET 0x0018 /* MCU SEMAPHORE 6 */ +# define TIVA_SMPH_SMPH7_OFFSET 0x001c /* MCU SEMAPHORE 7 */ +# define TIVA_SMPH_SMPH8_OFFSET 0x0020 /* MCU SEMAPHORE 8 */ +# define TIVA_SMPH_SMPH9_OFFSET 0x0024 /* MCU SEMAPHORE 9 */ +# define TIVA_SMPH_SMPH10_OFFSET 0x0028 /* MCU SEMAPHORE 10 */ +# define TIVA_SMPH_SMPH11_OFFSET 0x002c /* MCU SEMAPHORE 11 */ +# define TIVA_SMPH_SMPH12_OFFSET 0x0030 /* MCU SEMAPHORE 12 */ +# define TIVA_SMPH_SMPH13_OFFSET 0x0034 /* MCU SEMAPHORE 13 */ +# define TIVA_SMPH_SMPH14_OFFSET 0x0038 /* MCU SEMAPHORE 14 */ +# define TIVA_SMPH_SMPH15_OFFSET 0x003c /* MCU SEMAPHORE 15 */ +# define TIVA_SMPH_SMPH16_OFFSET 0x0040 /* MCU SEMAPHORE 16 */ +# define TIVA_SMPH_SMPH17_OFFSET 0x0044 /* MCU SEMAPHORE 17 */ +# define TIVA_SMPH_SMPH18_OFFSET 0x0048 /* MCU SEMAPHORE 18 */ +# define TIVA_SMPH_SMPH19_OFFSET 0x004c /* MCU SEMAPHORE 19 */ +# define TIVA_SMPH_SMPH20_OFFSET 0x0050 /* MCU SEMAPHORE 20 */ +# define TIVA_SMPH_SMPH21_OFFSET 0x0054 /* MCU SEMAPHORE 21 */ +# define TIVA_SMPH_SMPH22_OFFSET 0x0058 /* MCU SEMAPHORE 22 */ +# define TIVA_SMPH_SMPH23_OFFSET 0x005c /* MCU SEMAPHORE 23 */ +# define TIVA_SMPH_SMPH24_OFFSET 0x0060 /* MCU SEMAPHORE 24 */ +# define TIVA_SMPH_SMPH25_OFFSET 0x0064 /* MCU SEMAPHORE 25 */ +# define TIVA_SMPH_SMPH26_OFFSET 0x0068 /* MCU SEMAPHORE 26 */ +# define TIVA_SMPH_SMPH27_OFFSET 0x006c /* MCU SEMAPHORE 27 */ +# define TIVA_SMPH_SMPH28_OFFSET 0x0070 /* MCU SEMAPHORE 28 */ +# define TIVA_SMPH_SMPH29_OFFSET 0x0074 /* MCU SEMAPHORE 29 */ +# define TIVA_SMPH_SMPH30_OFFSET 0x0078 /* MCU SEMAPHORE 30 */ +# define TIVA_SMPH_SMPH31_OFFSET 0x007c /* MCU SEMAPHORE 31 */ + +#define TIVA_SMPH_PEEK_OFFSET(n) (0x0800 + ((n) << 2)) +# define TIVA_SMPH_PEEK0_OFFSET 0x0800 /* MCU SEMAPHORE 0 ALIAS */ +# define TIVA_SMPH_PEEK1_OFFSET 0x0804 /* MCU SEMAPHORE 1 ALIAS */ +# define TIVA_SMPH_PEEK2_OFFSET 0x0808 /* MCU SEMAPHORE 2 ALIAS */ +# define TIVA_SMPH_PEEK3_OFFSET 0x080c /* MCU SEMAPHORE 3 ALIAS */ +# define TIVA_SMPH_PEEK4_OFFSET 0x0810 /* MCU SEMAPHORE 4 ALIAS */ +# define TIVA_SMPH_PEEK5_OFFSET 0x0814 /* MCU SEMAPHORE 5 ALIAS */ +# define TIVA_SMPH_PEEK6_OFFSET 0x0818 /* MCU SEMAPHORE 6 ALIAS */ +# define TIVA_SMPH_PEEK7_OFFSET 0x081c /* MCU SEMAPHORE 7 ALIAS */ +# define TIVA_SMPH_PEEK8_OFFSET 0x0820 /* MCU SEMAPHORE 8 ALIAS */ +# define TIVA_SMPH_PEEK9_OFFSET 0x0824 /* MCU SEMAPHORE 9 ALIAS */ +# define TIVA_SMPH_PEEK10_OFFSET 0x0828 /* MCU SEMAPHORE 10 ALIAS */ +# define TIVA_SMPH_PEEK11_OFFSET 0x082c /* MCU SEMAPHORE 11 ALIAS */ +# define TIVA_SMPH_PEEK12_OFFSET 0x0830 /* MCU SEMAPHORE 12 ALIAS */ +# define TIVA_SMPH_PEEK13_OFFSET 0x0834 /* MCU SEMAPHORE 13 ALIAS */ +# define TIVA_SMPH_PEEK14_OFFSET 0x0838 /* MCU SEMAPHORE 14 ALIAS */ +# define TIVA_SMPH_PEEK15_OFFSET 0x083c /* MCU SEMAPHORE 15 ALIAS */ +# define TIVA_SMPH_PEEK16_OFFSET 0x0840 /* MCU SEMAPHORE 16 ALIAS */ +# define TIVA_SMPH_PEEK17_OFFSET 0x0844 /* MCU SEMAPHORE 17 ALIAS */ +# define TIVA_SMPH_PEEK18_OFFSET 0x0848 /* MCU SEMAPHORE 18 ALIAS */ +# define TIVA_SMPH_PEEK19_OFFSET 0x084c /* MCU SEMAPHORE 19 ALIAS */ +# define TIVA_SMPH_PEEK20_OFFSET 0x0850 /* MCU SEMAPHORE 20 ALIAS */ +# define TIVA_SMPH_PEEK21_OFFSET 0x0854 /* MCU SEMAPHORE 21 ALIAS */ +# define TIVA_SMPH_PEEK22_OFFSET 0x0858 /* MCU SEMAPHORE 22 ALIAS */ +# define TIVA_SMPH_PEEK23_OFFSET 0x085c /* MCU SEMAPHORE 23 ALIAS */ +# define TIVA_SMPH_PEEK24_OFFSET 0x0860 /* MCU SEMAPHORE 24 ALIAS */ +# define TIVA_SMPH_PEEK25_OFFSET 0x0864 /* MCU SEMAPHORE 25 ALIAS */ +# define TIVA_SMPH_PEEK26_OFFSET 0x0868 /* MCU SEMAPHORE 26 ALIAS */ +# define TIVA_SMPH_PEEK27_OFFSET 0x086c /* MCU SEMAPHORE 27 ALIAS */ +# define TIVA_SMPH_PEEK28_OFFSET 0x0870 /* MCU SEMAPHORE 28 ALIAS */ +# define TIVA_SMPH_PEEK29_OFFSET 0x0874 /* MCU SEMAPHORE 29 ALIAS */ +# define TIVA_SMPH_PEEK30_OFFSET 0x0878 /* MCU SEMAPHORE 30 ALIAS */ +# define TIVA_SMPH_PEEK31_OFFSET 0x087c /* MCU SEMAPHORE 31 ALIAS */ + +/* SMPH Register Addresses **************************************************/ + +#define TIVA_SMPH_SMPH(n) (TIVA_SMPH_BASE + TIVA_SMPH_SMPH_OFFSET(n)) +# define TIVA_SMPH_SMPH0 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH0_OFFSET) +# define TIVA_SMPH_SMPH1 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH1_OFFSET) +# define TIVA_SMPH_SMPH2 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH2_OFFSET) +# define TIVA_SMPH_SMPH3 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH3_OFFSET) +# define TIVA_SMPH_SMPH4 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH4_OFFSET) +# define TIVA_SMPH_SMPH5 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH5_OFFSET) +# define TIVA_SMPH_SMPH6 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH6_OFFSET) +# define TIVA_SMPH_SMPH7 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH7_OFFSET) +# define TIVA_SMPH_SMPH8 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH8_OFFSET) +# define TIVA_SMPH_SMPH9 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH9_OFFSET) +# define TIVA_SMPH_SMPH10 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH10_OFFSET) +# define TIVA_SMPH_SMPH11 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH11_OFFSET) +# define TIVA_SMPH_SMPH12 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH12_OFFSET) +# define TIVA_SMPH_SMPH13 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH13_OFFSET) +# define TIVA_SMPH_SMPH14 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH14_OFFSET) +# define TIVA_SMPH_SMPH15 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH15_OFFSET) +# define TIVA_SMPH_SMPH16 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH16_OFFSET) +# define TIVA_SMPH_SMPH17 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH17_OFFSET) +# define TIVA_SMPH_SMPH18 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH18_OFFSET) +# define TIVA_SMPH_SMPH19 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH19_OFFSET) +# define TIVA_SMPH_SMPH20 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH20_OFFSET) +# define TIVA_SMPH_SMPH21 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH21_OFFSET) +# define TIVA_SMPH_SMPH22 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH22_OFFSET) +# define TIVA_SMPH_SMPH23 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH23_OFFSET) +# define TIVA_SMPH_SMPH24 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH24_OFFSET) +# define TIVA_SMPH_SMPH25 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH25_OFFSET) +# define TIVA_SMPH_SMPH26 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH26_OFFSET) +# define TIVA_SMPH_SMPH27 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH27_OFFSET) +# define TIVA_SMPH_SMPH28 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH28_OFFSET) +# define TIVA_SMPH_SMPH29 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH29_OFFSET) +# define TIVA_SMPH_SMPH30 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH30_OFFSET) +# define TIVA_SMPH_SMPH31 (TIVA_SMPH_BASE + TIVA_SMPH_SMPH31_OFFSET) + +#define TIVA_SMPH_PEEK(n) (TIVA_SMPH_BASE + TIVA_SMPH_PEEK_OFFSET(n)) +# define TIVA_SMPH_PEEK0 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK0_OFFSET) +# define TIVA_SMPH_PEEK1 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK1_OFFSET) +# define TIVA_SMPH_PEEK2 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK2_OFFSET) +# define TIVA_SMPH_PEEK3 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK3_OFFSET) +# define TIVA_SMPH_PEEK4 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK4_OFFSET) +# define TIVA_SMPH_PEEK5 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK5_OFFSET) +# define TIVA_SMPH_PEEK6 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK6_OFFSET) +# define TIVA_SMPH_PEEK7 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK7_OFFSET) +# define TIVA_SMPH_PEEK8 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK8_OFFSET) +# define TIVA_SMPH_PEEK9 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK9_OFFSET) +# define TIVA_SMPH_PEEK10 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK10_OFFSET) +# define TIVA_SMPH_PEEK11 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK11_OFFSET) +# define TIVA_SMPH_PEEK12 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK12_OFFSET) +# define TIVA_SMPH_PEEK13 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK13_OFFSET) +# define TIVA_SMPH_PEEK14 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK14_OFFSET) +# define TIVA_SMPH_PEEK15 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK15_OFFSET) +# define TIVA_SMPH_PEEK16 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK16_OFFSET) +# define TIVA_SMPH_PEEK17 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK17_OFFSET) +# define TIVA_SMPH_PEEK18 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK18_OFFSET) +# define TIVA_SMPH_PEEK19 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK19_OFFSET) +# define TIVA_SMPH_PEEK20 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK20_OFFSET) +# define TIVA_SMPH_PEEK21 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK21_OFFSET) +# define TIVA_SMPH_PEEK22 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK22_OFFSET) +# define TIVA_SMPH_PEEK23 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK23_OFFSET) +# define TIVA_SMPH_PEEK24 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK24_OFFSET) +# define TIVA_SMPH_PEEK25 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK25_OFFSET) +# define TIVA_SMPH_PEEK26 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK26_OFFSET) +# define TIVA_SMPH_PEEK27 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK27_OFFSET) +# define TIVA_SMPH_PEEK28 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK28_OFFSET) +# define TIVA_SMPH_PEEK29 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK29_OFFSET) +# define TIVA_SMPH_PEEK30 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK30_OFFSET) +# define TIVA_SMPH_PEEK31 (TIVA_SMPH_BASE + TIVA_SMPH_PEEK31_OFFSET) + +/* SMPH Register Bitfield Definitions ***************************************/ + +/* TIVA_SMPH_SMPH0-TIVA_SMPH_SMPH31 */ + +#define SMPH_SMPH_STAT (1 << 0) /* Bit 0: Semaphore is available */ +# define SMPH_SMPH0_STAT SMPH_SMPH_STAT +# define SMPH_SMPH1_STAT SMPH_SMPH_STAT +# define SMPH_SMPH2_STAT SMPH_SMPH_STAT +# define SMPH_SMPH3_STAT SMPH_SMPH_STAT +# define SMPH_SMPH4_STAT SMPH_SMPH_STAT +# define SMPH_SMPH5_STAT SMPH_SMPH_STAT +# define SMPH_SMPH6_STAT SMPH_SMPH_STAT +# define SMPH_SMPH7_STAT SMPH_SMPH_STAT +# define SMPH_SMPH8_STAT SMPH_SMPH_STAT +# define SMPH_SMPH9_STAT SMPH_SMPH_STAT +# define SMPH_SMPH10_STAT SMPH_SMPH_STAT +# define SMPH_SMPH11_STAT SMPH_SMPH_STAT +# define SMPH_SMPH12_STAT SMPH_SMPH_STAT +# define SMPH_SMPH13_STAT SMPH_SMPH_STAT +# define SMPH_SMPH14_STAT SMPH_SMPH_STAT +# define SMPH_SMPH15_STAT SMPH_SMPH_STAT +# define SMPH_SMPH16_STAT SMPH_SMPH_STAT +# define SMPH_SMPH17_STAT SMPH_SMPH_STAT +# define SMPH_SMPH18_STAT SMPH_SMPH_STAT +# define SMPH_SMPH19_STAT SMPH_SMPH_STAT +# define SMPH_SMPH20_STAT SMPH_SMPH_STAT +# define SMPH_SMPH21_STAT SMPH_SMPH_STAT +# define SMPH_SMPH22_STAT SMPH_SMPH_STAT +# define SMPH_SMPH23_STAT SMPH_SMPH_STAT +# define SMPH_SMPH24_STAT SMPH_SMPH_STAT +# define SMPH_SMPH25_STAT SMPH_SMPH_STAT +# define SMPH_SMPH26_STAT SMPH_SMPH_STAT +# define SMPH_SMPH27_STAT SMPH_SMPH_STAT +# define SMPH_SMPH28_STAT SMPH_SMPH_STAT +# define SMPH_SMPH29_STAT SMPH_SMPH_STAT +# define SMPH_SMPH30_STAT SMPH_SMPH_STAT +# define SMPH_SMPH31_STAT SMPH_SMPH_STAT + +/* TIVA_SMPH_PEEK0-TIVA_SMPH_PEEK31 */ + +#define SMPH_PEEK_STAT (1 << 0) /* Bit 0: Semaphore is available */ +# define SMPH_PEEK0_STAT SMPH_PEEK_STAT +# define SMPH_PEEK1_STAT SMPH_PEEK_STAT +# define SMPH_PEEK2_STAT SMPH_PEEK_STAT +# define SMPH_PEEK3_STAT SMPH_PEEK_STAT +# define SMPH_PEEK4_STAT SMPH_PEEK_STAT +# define SMPH_PEEK5_STAT SMPH_PEEK_STAT +# define SMPH_PEEK6_STAT SMPH_PEEK_STAT +# define SMPH_PEEK7_STAT SMPH_PEEK_STAT +# define SMPH_PEEK8_STAT SMPH_PEEK_STAT +# define SMPH_PEEK9_STAT SMPH_PEEK_STAT +# define SMPH_PEEK10_STAT SMPH_PEEK_STAT +# define SMPH_PEEK11_STAT SMPH_PEEK_STAT +# define SMPH_PEEK12_STAT SMPH_PEEK_STAT +# define SMPH_PEEK13_STAT SMPH_PEEK_STAT +# define SMPH_PEEK14_STAT SMPH_PEEK_STAT +# define SMPH_PEEK15_STAT SMPH_PEEK_STAT +# define SMPH_PEEK16_STAT SMPH_PEEK_STAT +# define SMPH_PEEK17_STAT SMPH_PEEK_STAT +# define SMPH_PEEK18_STAT SMPH_PEEK_STAT +# define SMPH_PEEK19_STAT SMPH_PEEK_STAT +# define SMPH_PEEK20_STAT SMPH_PEEK_STAT +# define SMPH_PEEK21_STAT SMPH_PEEK_STAT +# define SMPH_PEEK22_STAT SMPH_PEEK_STAT +# define SMPH_PEEK23_STAT SMPH_PEEK_STAT +# define SMPH_PEEK24_STAT SMPH_PEEK_STAT +# define SMPH_PEEK25_STAT SMPH_PEEK_STAT +# define SMPH_PEEK26_STAT SMPH_PEEK_STAT +# define SMPH_PEEK27_STAT SMPH_PEEK_STAT +# define SMPH_PEEK28_STAT SMPH_PEEK_STAT +# define SMPH_PEEK29_STAT SMPH_PEEK_STAT +# define SMPH_PEEK30_STAT SMPH_PEEK_STAT +# define SMPH_PEEK31_STAT SMPH_PEEK_STAT + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aux_smph.h b/arch/arm/src/tiva/hardware/tiva_aux_smph.h new file mode 100644 index 0000000000..fe8fc7cc63 --- /dev/null +++ b/arch/arm/src/tiva/hardware/tiva_aux_smph.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * arch/arm/src/tiva/hardware/tiva_aux_smph.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SMPH_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SMPH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ + +#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the AUX SMPH block */ +#elif defined(CONFIG_ARCH_CHIP_CC13X0) +# include "hardware/cc13x0/cc13x0_aux_smph.h" +#elif defined(CONFIG_ARCH_CHIP_CC13X2) +# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h" +#else +# error "Unsupported Tiva/Stellaris/SimpleLink AUX SMPH" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_smph.h b/arch/arm/src/tiva/hardware/tiva_smph.h new file mode 100644 index 0000000000..4502190bc8 --- /dev/null +++ b/arch/arm/src/tiva/hardware/tiva_smph.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * arch/arm/src/tiva/hardware/tiva_smph.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SMPH_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SMPH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ + +#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the SMPH block */ +#elif defined(CONFIG_ARCH_CHIP_CC13X0) +# include "hardware/cc13x0/cc13x0_smph.h" +#elif defined(CONFIG_ARCH_CHIP_CC13X2) +# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h" +#else +# error "Unsupported Tiva/Stellaris/SimpleLink SMPH" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SMPH_H */ diff --git a/configs/launchxl-cc1310/README.txt b/configs/launchxl-cc1310/README.txt index 38c3c7df08..2f06a3c116 100644 --- a/configs/launchxl-cc1310/README.txt +++ b/configs/launchxl-cc1310/README.txt @@ -17,7 +17,8 @@ Status 2019-01-21: Fragmentary board support in place. The initial intent of this board support is simply to assist in the CC13x0 architecture development. Serious board development will occur later. At present, - the CC13x0 does not even compile error-free. + the CC13x0 does not even compile error-free: Compilation of cc14x0_rom.c + fails because the DDI0 OSC header file has not yet been ported. Serial Console ============== diff --git a/configs/launchxl-cc1310/nsh/defconfig b/configs/launchxl-cc1310/nsh/defconfig index cc567043df..bff9db4fa6 100644 --- a/configs/launchxl-cc1310/nsh/defconfig +++ b/configs/launchxl-cc1310/nsh/defconfig @@ -1,10 +1,11 @@ # CONFIG_NSH_DISABLE_DATE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="launchxl-cc1310" -CONFIG_ARCH_BOARD_LAUNCH_CC1310=y +CONFIG_ARCH_BOARD_LAUNCHXL_CC1310=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP_CC1310=y CONFIG_ARCH_CHIP_CC13X0=y +CONFIG_ARCH_CHIP_CC13XX_V2=y CONFIG_ARCH_CHIP_SIMPLELINK=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/configs/launchxl-cc1312r1/nsh/defconfig b/configs/launchxl-cc1312r1/nsh/defconfig index 40c5453f35..37c6934d1f 100644 --- a/configs/launchxl-cc1312r1/nsh/defconfig +++ b/configs/launchxl-cc1312r1/nsh/defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_BOARD_LAUNCHXL_CC1312R1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP_CC1312R1=y CONFIG_ARCH_CHIP_CC13X2=y -CONFIG_ARCH_CHIP_CC13X2_V1=y +CONFIG_ARCH_CHIP_CC13XX_V1=y CONFIG_ARCH_CHIP_SIMPLELINK=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y