esp32_spiflash.c: Keep the index of the other CPU between SPI Flash
operations. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
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@ -161,6 +161,9 @@ struct spiflash_map_req
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struct spiflash_cachestate_s
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{
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int cpu;
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#ifdef CONFIG_SMP
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int other;
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#endif
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irqstate_t flags;
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uint32_t val[2];
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};
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@ -405,26 +408,23 @@ static inline void spi_reset_regbits(struct esp32_spiflash_s *priv,
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static inline void IRAM_ATTR
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esp32_spiflash_opstart(struct spiflash_cachestate_s *state)
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{
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#ifdef CONFIG_SMP
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int other;
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#endif
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state->flags = enter_critical_section();
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state->cpu = up_cpu_index();
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#ifdef CONFIG_SMP
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other = state->cpu ? 0 : 1;
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state->other = state->cpu ? 0 : 1;
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#endif
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DEBUGASSERT(state->cpu == 0 || state->cpu == 1);
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#ifdef CONFIG_SMP
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DEBUGASSERT(other == 0 || other == 1);
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up_cpu_pause(other);
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DEBUGASSERT(state->other == 0 || state->other == 1);
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DEBUGASSERT(state->other != state->cpu);
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up_cpu_pause(state->other);
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#endif
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spi_disable_cache(state->cpu, &state->val[state->cpu]);
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#ifdef CONFIG_SMP
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spi_disable_cache(other, &state->val[other]);
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spi_disable_cache(state->other, &state->val[state->other]);
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#endif
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}
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@ -439,23 +439,16 @@ static inline void IRAM_ATTR
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static inline void IRAM_ATTR
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esp32_spiflash_opdone(const struct spiflash_cachestate_s *state)
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{
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#ifdef CONFIG_SMP
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int other;
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#endif
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#ifdef CONFIG_SMP
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other = state->cpu ? 0 : 1;
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#endif
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DEBUGASSERT(state->cpu == 0 || state->cpu == 1);
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#ifdef CONFIG_SMP
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DEBUGASSERT(other == 0 || other == 1);
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DEBUGASSERT(state->other == 0 || state->other == 1);
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DEBUGASSERT(state->other != state->cpu);
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#endif
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spi_enable_cache(state->cpu, state->val[state->cpu]);
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#ifdef CONFIG_SMP
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spi_enable_cache(other, state->val[other]);
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up_cpu_resume(other);
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spi_enable_cache(state->other, state->val[state->other]);
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up_cpu_resume(state->other);
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#endif
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leave_critical_section(state->flags);
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