nrf52 GPIO/GPIOTE: better expose pin interrupt capability
This change improves upon current support for pin interrupts. Before, a pin interrupt was handled (with nrf52_gpiote_setevent) using one of the eight available GPIOTE channels. Moreover, it didn't event let the user specify which channel to use (simply tried to get a free one). Also, it was buggy since it did not consider unsetting the callback. Besides GPIOTE channels, there is another way to deal with pin interrupts. The GPIO peripheral is capable of generating a PORT event (for the whole GPIO port) depending on the pin SENSE configuration (HIGH or LOW, or NONE) and GPIO DETECTMODE register (latching or non-latching). This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event, maintaining functionality of original function, but now allows specifying channel (and correctly handles unsetting the callback). Then, a new nrf52_gpiote_set_pin_event is added, which allows to set a callback for a given pin. During initialization, interrupt for the PORT event is enabled and handled in such way that for each pin whose corresponding bit in LATCH register (indicates the result of pin SENSEing) the callback for this pin will be invoked. This mechanism means that every pin can get an ISR. It also avoids using GPIOTE channels for this purpose which carry higher current consumption. This new per-pin callback mechanism has some added memory requirement so it can be disabled and its default is dependant on DEFAULT_SMALL. When disabled, a callback for the PORT event can be set directly with nrf52_gpiote_set_port_event There was only one use of nrf52_gpio_setevent() which was migrated into nrf52_gpio_set_ch_event() passing channel zero.
This commit is contained in:
Matias N
Mateusz Szafoni
parent
723698c787
commit
f55a2879ca
@ -386,6 +386,24 @@ config NRF52_PROGMEM
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menu "GPIO Interrupt Configuration"
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config NRF52_PER_PIN_INTERRUPTS
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bool "Per-pin interrupt callbacks"
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default n if DEFAULT_SMALL
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default y if !DEFAULT_SMALL
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depends on NRF52_GPIOTE
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---help---
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The GPIOTE peripheral supports a limited number of channels which can
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be set to EVENT mode and thus generate interrupts on pin state changes.
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Another mechanism offered by the GPIO/GPIOTE peripherals is the PORT
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event. This event is generated from a signal shared by all pins in
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the GPIO port.
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This option enables the ability to set per-pin callbacks that will
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be invoked from the main GPIOTE ISR when a PORT event is generated.
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As this involves extra storage to store each callback, this option can
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be disabled to save space. In such case, it is possible to set a callback
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for the whole PORT event directly.
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endmenu # GPIO Interrupt Configuration
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menu "PWM configuration"
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@ -57,6 +57,8 @@
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# define NRF52_GPIO_NPORTS 1
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#endif
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#define NRF52_GPIO_NPINS 32
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/* Register offsets *****************************************************************/
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#define NRF52_GPIO_OUT_OFFSET 0x0504 /* Write GPIO port */
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@ -95,6 +97,9 @@
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/* Register bit definitions *********************************************************/
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#define GPIO_DETECTMODE_DEFAULT (0)
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#define GPIO_DETECTMODE_LDETECT (1)
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#define GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */
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#define GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */
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#define GPIO_CNF_PULL_SHIFT (2)
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@ -102,5 +107,20 @@
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# define GPIO_CNF_PULL_DISABLED (0 << GPIO_CNF_PULL_SHIFT)
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# define GPIO_CNF_PULL_DOWN (1 << GPIO_CNF_PULL_SHIFT)
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# define GPIO_CNF_PULL_UP (3 << GPIO_CNF_PULL_SHIFT)
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#define GPIO_CNF_DRIVE_SHIFT (8)
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#define GPIO_CNF_DRIVE_MASK (0x7 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_S0S1 (0 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_H0S1 (1 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_S0H1 (2 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_H0H1 (3 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_D0S1 (4 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_D0H1 (5 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_S0D1 (6 << GPIO_CNF_DRIVE_SHIFT)
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# define GPIO_CNF_DRIVE_H0D1 (7 << GPIO_CNF_DRIVE_SHIFT)
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#define GPIO_CNF_SENSE_SHIFT (16)
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#define GPIO_CNF_SENSE_MASK (0x3 << GPIO_CNF_SENSE_SHIFT)
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# define GPIO_CNF_SENSE_DISABLED (0 << GPIO_CNF_SENSE_SHIFT)
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# define GPIO_CNF_SENSE_HIGH (2 << GPIO_CNF_SENSE_SHIFT)
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# define GPIO_CNF_SENSE_LOW (3 << GPIO_CNF_SENSE_SHIFT)
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H */
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@ -67,7 +67,8 @@
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#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT)
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# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK)
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#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */
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#define GPIOTE_INT_PORT_SHIFT 31 /* Bit 31: Enable interrupt for event PORT */
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#define GPIOTE_INT_PORT (1 << GPIOTE_INT_PORT_SHIFT)
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/* CONFIG Register */
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@ -144,22 +144,54 @@ static inline void nrf52_gpio_mode(nrf52_pinset_t cfgset,
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mode = cfgset & GPIO_MODE_MASK;
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regval = getreg32(offset);
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regval &= GPIO_CNF_PULL_MASK;
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regval &= ~GPIO_CNF_PULL_MASK;
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if (mode == GPIO_PULLUP)
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{
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regval &= GPIO_CNF_PULL_MASK;
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regval |= GPIO_CNF_PULL_UP;
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}
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else if (mode == GPIO_PULLDOWN)
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{
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regval &= GPIO_CNF_PULL_MASK;
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regval |= GPIO_CNF_PULL_DOWN;
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}
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putreg32(regval, offset);
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}
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/****************************************************************************
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* Name: nrf52_gpio_sense
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*
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* Description:
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* Set SENSE configuration for an input pin
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*
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****************************************************************************/
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static inline void nrf52_gpio_sense(nrf52_pinset_t cfgset,
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unsigned int port, unsigned int pin)
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{
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uint32_t mode;
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uint32_t regval;
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uint32_t offset;
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mode = cfgset & GPIO_SENSE_MASK;
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offset = nrf52_gpio_regget(port, NRF52_GPIO_PIN_CNF_OFFSET(pin));
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regval = getreg32(offset);
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regval &= ~GPIO_CNF_SENSE_MASK;
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if (mode == GPIO_SENSE_HIGH)
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{
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regval |= GPIO_CNF_SENSE_HIGH;
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}
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else
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{
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regval |= GPIO_CNF_SENSE_LOW;
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}
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putreg32(regval, offset);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -204,7 +236,8 @@ int nrf52_gpio_config(nrf52_pinset_t cfgset)
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switch (cfgset & GPIO_FUNC_MASK)
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{
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case GPIO_INPUT: /* GPIO input pin */
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break; /* Already configured */
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nrf52_gpio_sense(cfgset, port, pin);
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break;
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case GPIO_OUTPUT: /* GPIO outpout pin */
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nrf52_gpio_output(cfgset, port, pin);
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@ -313,3 +346,20 @@ bool nrf52_gpio_read(nrf52_pinset_t pinset)
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return (regval >> pin) & 1UL;
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}
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/****************************************************************************
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* Name: nrf52_gpio_detectmode
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*
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* Description:
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* Set DETECTMODE to either default or latched
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*
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****************************************************************************/
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void nrf52_gpio_detectmode(int port, enum nrf52_gpio_detectmode_e mode)
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{
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uint32_t offset = nrf52_gpio_regget(port, NRF52_GPIO_DETECTMODE_OFFSET);
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putreg32(mode == NRF52_GPIO_DETECTMODE_DETECT ?
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GPIO_DETECTMODE_DEFAULT :
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GPIO_DETECTMODE_LDETECT, offset);
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}
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@ -187,6 +187,12 @@
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typedef uint32_t nrf52_pinset_t;
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enum nrf52_gpio_detectmode_e
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{
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NRF52_GPIO_DETECTMODE_DETECT,
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NRF52_GPIO_DETECTMODE_LDETECT,
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};
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/************************************************************************************
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* Public Data
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************************************************************************************/
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@ -61,9 +61,21 @@ struct nrf52_gpiote_callback_s
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* Private Data
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****************************************************************************/
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/* Interrupt handlers attached to each GPIOTE */
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/* Callbacks attached to each GPIOTE channel */
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static struct nrf52_gpiote_callback_s g_gpiote_callbacks[GPIOTE_CHANNELS];
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static struct nrf52_gpiote_callback_s g_gpiote_ch_callbacks[GPIOTE_CHANNELS];
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#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS
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/* Callbacks attached to each GPIO pin */
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static struct nrf52_gpiote_callback_s
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g_gpiote_pin_callbacks[NRF52_GPIO_NPORTS][NRF52_GPIO_NPINS];
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#else
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/* Callback for the PORT event */
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static struct nrf52_gpiote_callback_s
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g_gpiote_port_callback[NRF52_GPIO_NPORTS];
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#endif
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/****************************************************************************
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* Private Functions
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@ -108,6 +120,9 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg)
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uint32_t regval = 0;
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int ret = OK;
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int i = 0;
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#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS
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int j = 0;
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#endif
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/* Scan all GPIOTE channels */
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@ -115,7 +130,7 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg)
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{
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/* Only if callback is registered */
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if (g_gpiote_callbacks[i].callback != NULL)
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if (g_gpiote_ch_callbacks[i].callback != NULL)
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{
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/* Get input event register */
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@ -124,8 +139,8 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg)
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{
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/* Execute callback */
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xcpt_t callback = g_gpiote_callbacks[i].callback;
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FAR void *cbarg = g_gpiote_callbacks[i].arg;
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xcpt_t callback = g_gpiote_ch_callbacks[i].callback;
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FAR void *cbarg = g_gpiote_ch_callbacks[i].arg;
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ret = callback(irq, context, cbarg);
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/* Clear event */
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@ -135,6 +150,76 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg)
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}
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}
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/* Check for PORT event */
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regval = nrf52_gpiote_getreg(NRF52_GPIOTE_EVENTS_PORT_OFFSET);
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if (regval)
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{
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uint32_t addr = 0;
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/* Ack PORT event */
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nrf52_gpiote_putreg(NRF52_GPIOTE_EVENTS_PORT_OFFSET, 0);
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/* For each GPIO port, get LATCH register */
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for (i = 0; i < NRF52_GPIO_NPORTS; i++)
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{
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switch (i)
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{
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case 0:
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addr = NRF52_GPIO_P0_BASE + NRF52_GPIO_LATCH_OFFSET;
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break;
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#ifdef CONFIG_NRF52_HAVE_PORT1
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case 1:
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addr = NRF52_GPIO_P1_BASE + NRF52_GPIO_LATCH_OFFSET;
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break;
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#endif
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}
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/* Retrieve LATCH register */
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regval = getreg32(addr);
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/* Clear LATCH register (this may set PORT again) */
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putreg32(0xffffffff, addr);
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#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS
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/* Check for pins with DETECT bit high in LATCH register
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* and dispatch callback if set
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*/
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for (j = 0; j < NRF52_GPIO_NPINS && regval; j++)
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{
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if (regval & (1 << j) && g_gpiote_pin_callbacks[i][j].callback)
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{
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/* Run callback */
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xcpt_t callback = g_gpiote_pin_callbacks[i][j].callback;
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FAR void *cbarg = g_gpiote_pin_callbacks[i][j].arg;
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ret = callback(irq, context, cbarg);
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/* Mark bit is as "visited", we can stop looping sooner
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* this way
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*/
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regval &= ~(1 << j);
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}
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}
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#else
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if (g_gpiote_port_callback[i].callback)
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{
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xcpt_t callback = g_gpiote_port_callback[i].callback;
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FAR void *cbarg = g_gpiote_port_callback[i].arg;
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ret = callback(irq, context, cbarg);
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}
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#endif
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}
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}
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return ret;
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}
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@ -142,11 +227,126 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg)
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* Public Functions
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****************************************************************************/
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#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS
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/****************************************************************************
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* Name: nrf52_gpiosetevent
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* Name: nrf52_gpiote_set_pin_event
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*
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* Description:
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* Sets/clears GPIO based event and interrupt triggers.
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* Sets/clears a handler for a given pin for the GPIO PORT event. This
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* will mean edge-sensitive or level-sensitive according to GPIO detect
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* mode configuration for the port (see nrf52_gpio_detectmode()). Pin
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* will be sensitive to high/low according to GPIO_SENSE_LOW/HIGH
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* (set via nrf52_gpio_config()).
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*
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* The passed handler will be invoked from the main ISR for the PORT
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* event and will take care of clearing the LATCH register.
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*
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* Input Parameters:
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* - pinset: GPIO pin configuration
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* - func: When non-NULL, generate interrupt
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* - arg: Argument passed to the interrupt callback
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno value on failure indicating the
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* nature of the failure.
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*
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****************************************************************************/
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void nrf52_gpiote_set_pin_event(uint32_t pinset, xcpt_t func, FAR void *arg)
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{
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int pin = 0;
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int port = 0;
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irqstate_t flags;
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pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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#ifdef CONFIG_NRF52_HAVE_PORT1
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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#endif
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flags = enter_critical_section();
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g_gpiote_pin_callbacks[port][pin].callback = func;
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g_gpiote_pin_callbacks[port][pin].arg = arg;
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leave_critical_section(flags);
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}
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#else
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/****************************************************************************
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* Name: nrf52_gpiote_set_port_event
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*
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* Description:
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* Sets/clears the handler for the GPIO PORT event.
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*
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* The passed handler will be invoked from the main ISR for the PORT
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* event and will take care of clearing the LATCH register.
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*
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* Input Parameters:
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* - pinset: GPIO port will be extracted from this parameter
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* - func: When non-NULL, generate interrupt
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* - arg: Argument passed to the interrupt callback
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno value on failure indicating the
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* nature of the failure.
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*
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****************************************************************************/
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void nrf52_gpiote_set_port_event(uint32_t pinset, xcpt_t func, FAR void *arg)
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{
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int port = 0;
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irqstate_t flags;
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#ifdef CONFIG_NRF52_HAVE_PORT1
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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#endif
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flags = enter_critical_section();
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g_gpiote_port_callback[port].callback = func;
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g_gpiote_port_callback[port].arg = arg;
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if (func)
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{
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/* Enable the ISR */
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nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_PORT);
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}
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else
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{
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#if NRF52_GPIO_NPORTS > 1
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/* Check if we can disable the ISR */
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int i;
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for (i = 0; i < NRF52_GPIO_NPORTS; i++)
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{
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if (g_gpiote_port_callback[port].callback)
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{
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break;
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}
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}
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if (i == NRF52_GPIO_NPORTS)
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{
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nrf52_gpiote_putreg(NRF52_GPIOTE_INTENCLR_OFFSET, GPIOTE_INT_PORT);
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}
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#else
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/* Disable the ISR */
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nrf52_gpiote_putreg(NRF52_GPIOTE_INTENCLR_OFFSET, GPIOTE_INT_PORT);
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#endif
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}
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leave_critical_section(flags);
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}
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#endif
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/****************************************************************************
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* Name: nrf52_gpiote_set_ch_event
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*
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* Description:
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* Configures a GPIOTE channel in EVENT mode, assigns it to a given pin
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* and sets a handler for the corresponding channel events.
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*
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* Input Parameters:
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* - pinset: GPIO pin configuration
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@ -162,122 +362,90 @@ static int nrf52_gpiote_isr(int irq, FAR void *context, FAR void *arg)
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*
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****************************************************************************/
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int nrf52_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
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bool event, xcpt_t func, FAR void *arg)
|
||||
void nrf52_gpiote_set_ch_event(uint32_t pinset, int channel,
|
||||
bool risingedge, bool fallingedge,
|
||||
xcpt_t func, FAR void *arg)
|
||||
{
|
||||
int ret = OK;
|
||||
int i = 0;
|
||||
int pin = 0;
|
||||
#ifdef CONFIG_NRF52_HAVE_PORT1
|
||||
int port = 0;
|
||||
#endif
|
||||
uint32_t regval = 0;
|
||||
bool found = false;
|
||||
irqstate_t flags;
|
||||
|
||||
/* Find available GPIOTE channel */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
for (i = 0; i < GPIOTE_CHANNELS; i += 1)
|
||||
{
|
||||
if (g_gpiote_callbacks[i].callback == NULL)
|
||||
{
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Return error if there is no free channel */
|
||||
|
||||
if (found == false)
|
||||
{
|
||||
ret = -ENODEV;
|
||||
goto errout;
|
||||
}
|
||||
DEBUGASSERT(channel < GPIOTE_CHANNELS);
|
||||
|
||||
/* NOTE: GPIOTE module has priority over GPIO module
|
||||
* so GPIO configuration will be ignored
|
||||
*/
|
||||
|
||||
/* Select GPIOTE pin */
|
||||
flags = enter_critical_section();
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
regval = (pin << GPIOTE_CONFIG_PSEL_SHIFT);
|
||||
if (func)
|
||||
{
|
||||
/* Select EVENT mode */
|
||||
|
||||
regval |= GPIOTE_CONFIG_MODE_EV;
|
||||
|
||||
/* Select GPIOTE pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
regval |= (pin << GPIOTE_CONFIG_PSEL_SHIFT);
|
||||
|
||||
#ifdef CONFIG_NRF52_HAVE_PORT1
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
regval |= (port << GPIOTE_CONFIG_PORT_SHIFT);
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
regval |= (port << GPIOTE_CONFIG_PORT_SHIFT);
|
||||
#endif
|
||||
|
||||
/* Select EVENT mode */
|
||||
/* Select polarity */
|
||||
|
||||
if (event || func)
|
||||
{
|
||||
regval &= ~GPIOTE_CONFIG_MODE_MASK;
|
||||
regval |= GPIOTE_CONFIG_MODE_EV;
|
||||
}
|
||||
if (risingedge == true && fallingedge == true)
|
||||
{
|
||||
regval |= GPIOTE_CONFIG_POL_TG;
|
||||
}
|
||||
else if (risingedge == true)
|
||||
{
|
||||
regval |= GPIOTE_CONFIG_POL_LTH;
|
||||
}
|
||||
else if (fallingedge == true)
|
||||
{
|
||||
regval |= GPIOTE_CONFIG_POL_HTL;
|
||||
}
|
||||
|
||||
/* Select polarity */
|
||||
/* Enable callback for channel */
|
||||
|
||||
if (risingedge == true && fallingedge == true)
|
||||
{
|
||||
regval |= GPIOTE_CONFIG_POL_TG;
|
||||
g_gpiote_ch_callbacks[channel].callback = func;
|
||||
g_gpiote_ch_callbacks[channel].arg = arg;
|
||||
|
||||
/* Enable interrupt for given event */
|
||||
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET,
|
||||
GPIOTE_INT_IN(channel));
|
||||
}
|
||||
else if (risingedge == true)
|
||||
else
|
||||
{
|
||||
regval |= GPIOTE_CONFIG_POL_LTH;
|
||||
}
|
||||
else if (fallingedge == true)
|
||||
{
|
||||
regval |= GPIOTE_CONFIG_POL_HTL;
|
||||
/* Leave register as zero (disabled mode) */
|
||||
|
||||
/* Disable interrupt for given event */
|
||||
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_INTENCLR_OFFSET,
|
||||
GPIOTE_INT_IN(channel));
|
||||
|
||||
/* Remove callback configuration */
|
||||
|
||||
g_gpiote_ch_callbacks[channel].callback = NULL;
|
||||
g_gpiote_ch_callbacks[channel].arg = NULL;
|
||||
}
|
||||
|
||||
/* Write CONFIG register */
|
||||
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_CONFIG_OFFSET(i), regval);
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_CONFIG_OFFSET(channel), regval);
|
||||
|
||||
/* Enable interrupt for given event */
|
||||
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_IN(i));
|
||||
|
||||
/* Connect callback */
|
||||
|
||||
g_gpiote_callbacks[i].callback = func;
|
||||
g_gpiote_callbacks[i].arg = arg;
|
||||
|
||||
errout:
|
||||
return ret;
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiote_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize GPIOTE
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_gpiote_init(void)
|
||||
{
|
||||
/* Reset GPIOTE data */
|
||||
|
||||
memset(&g_gpiote_callbacks,
|
||||
0,
|
||||
sizeof(struct nrf52_gpiote_callback_s)*GPIOTE_CHANNELS);
|
||||
|
||||
/* Attach GPIOTE interrupt handler */
|
||||
|
||||
irq_attach(NRF52_IRQ_GPIOTE, nrf52_gpiote_isr, NULL);
|
||||
up_enable_irq(NRF52_IRQ_GPIOTE);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiotaskset
|
||||
* Name: nrf52_gpio_set_task
|
||||
*
|
||||
* Description:
|
||||
* Configure GPIO in TASK mode (to be controlled via tasks).
|
||||
@ -299,8 +467,9 @@ int nrf52_gpiote_init(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_gpiotaskset(uint32_t pinset, int channel,
|
||||
bool output_high, enum nrf52_gpiote_outcfg_e outcfg)
|
||||
void nrf52_gpiote_set_task(uint32_t pinset, int channel,
|
||||
bool output_high,
|
||||
enum nrf52_gpiote_outcfg_e outcfg)
|
||||
{
|
||||
uint32_t regval;
|
||||
int pin;
|
||||
@ -351,6 +520,36 @@ int nrf52_gpiotaskset(uint32_t pinset, int channel,
|
||||
/* Write register */
|
||||
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_CONFIG_OFFSET(channel), regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiote_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize GPIOTE
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_gpiote_init(void)
|
||||
{
|
||||
/* Reset GPIOTE data */
|
||||
|
||||
memset(&g_gpiote_ch_callbacks, 0, sizeof(g_gpiote_ch_callbacks));
|
||||
|
||||
#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS
|
||||
memset(&g_gpiote_pin_callbacks, 0, sizeof(g_gpiote_pin_callbacks));
|
||||
|
||||
/* Enable PORT event interrupt */
|
||||
|
||||
nrf52_gpiote_putreg(NRF52_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_PORT);
|
||||
#else
|
||||
memset(&g_gpiote_port_callback, 0, sizeof(g_gpiote_port_callback));
|
||||
#endif
|
||||
|
||||
/* Attach GPIOTE interrupt handler */
|
||||
|
||||
irq_attach(NRF52_IRQ_GPIOTE, nrf52_gpiote_isr, NULL);
|
||||
up_enable_irq(NRF52_IRQ_GPIOTE);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -49,17 +49,19 @@ enum nrf52_gpiote_outcfg_e
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiosetevent
|
||||
* Name: nrf52_gpiote_set_ch_event
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
* Configures a GPIOTE channel in EVENT mode, assigns it to a given pin
|
||||
* and sets a handler for the corresponding channel events.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - pinset: gpio pin configuration
|
||||
* - rising/falling edge: enables
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
* - pinset: GPIO pin configuration
|
||||
* - risingedge: Enables interrupt on rising edges
|
||||
* - fallingedge: Enables interrupt on falling edges
|
||||
* - event: Generate event when set
|
||||
* - func: When non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure indicating the
|
||||
@ -67,11 +69,65 @@ enum nrf52_gpiote_outcfg_e
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
bool event, xcpt_t func, FAR void *arg);
|
||||
void nrf52_gpiote_set_ch_event(uint32_t pinset, int channel,
|
||||
bool risingedge, bool fallingedge,
|
||||
xcpt_t func, FAR void *arg);
|
||||
|
||||
#ifdef CONFIG_NRF52_PER_PIN_INTERRUPTS
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiote_set_pin_event
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears a handler for a given pin for the GPIO PORT event. This
|
||||
* will mean edge-sensitive or level-sensitive according to GPIO detect
|
||||
* mode configuration for the port (see nrf52_gpio_detectmode()). Pin
|
||||
* will be sensitive to high/low according to GPIO_SENSE_LOW/HIGH
|
||||
* (set via nrf52_gpio_config()).
|
||||
*
|
||||
* The passed handler will be invoked from the main ISR for the PORT
|
||||
* event and will take care of clearing the LATCH register.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - pinset: GPIO pin configuration
|
||||
* - func: When non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure indicating the
|
||||
* nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void nrf52_gpiote_set_pin_event(uint32_t pinset, xcpt_t func, FAR void *arg);
|
||||
#else
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiotaskset
|
||||
* Name: nrf52_gpiote_set_port_event
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears the handler for the GPIO PORT event.
|
||||
*
|
||||
* The passed handler will be invoked from the main ISR for the PORT
|
||||
* event and will take care of clearing the LATCH register.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - pinset: GPIO port will be extracted from this parameter
|
||||
* - func: When non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure indicating the
|
||||
* nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void nrf52_gpiote_set_port_event(uint32_t pinset, xcpt_t func,
|
||||
FAR void *arg);
|
||||
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpio_set_task
|
||||
*
|
||||
* Description:
|
||||
* Configure GPIO in TASK mode (to be controlled via tasks).
|
||||
@ -93,8 +149,8 @@ int nrf52_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_gpiotaskset(uint32_t pinset, int channel, bool output_high,
|
||||
enum nrf52_gpiote_outcfg_e outcfg);
|
||||
void nrf52_gpio_set_task(uint32_t pinset, int channel,
|
||||
bool output_high, enum nrf52_gpiote_outcfg_e outcfg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpiote_init
|
||||
|
||||
@ -88,7 +88,7 @@ static int sx127x_irq0_attach(xcpt_t isr, FAR void *arg)
|
||||
|
||||
/* IRQ on rising edge */
|
||||
|
||||
nrf52_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg);
|
||||
nrf52_gpiote_set_ch_event(GPIO_SX127X_DIO0, 0, true, false, isr, arg);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user