TMS570: Add PBIST header file
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Gregory Nutt
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arch/arm/src/tms570/chip/tms570_pbist.h
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arch/arm/src/tms570/chip/tms570_pbist.h
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/****************************************************************************************************
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* arch/arm/src/tms570/chip/tms570_pbist.h
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* Secondary System Control Register Definitions
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas
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* Instruments, Literature Number: SPNU517A, September 2013
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H
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#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/tms570_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */
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#define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */
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#define TMS570_PBIST_PCR_OFFSET 0x016c /* Program Control Register */
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#define TMS570_PBIST_PACT_OFFSET 0x0180 /* PBIST Activate/ROM Clock Enable Register */
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#define TMS570_PBIST_PBISTID_OFFSET 0x0184 /* PBIST ID Register */
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#define TMS570_PBIST_OVER_OFFSET 0x0188 /* Override Register */
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#define TMS570_PBIST_FSRF0_OFFSET 0x0190 /* Fail Status Fail Register 0 */
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#define TMS570_PBIST_FSRC0_OFFSET 0x0198 /* Fail Status Count Register 0 */
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#define TMS570_PBIST_FSRC1_OFFSET 0x019c /* Fail Status Count Register 1 */
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#define TMS570_PBIST_FSRA0_OFFSET 0x01a0 /* Fail Status Address 0 Register */
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#define TMS570_PBIST_FSRA1_OFFSET 0x01a4 /* Fail Status Address 1 Register */
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#define TMS570_PBIST_FSRDL0_OFFSET 0x01a8 /* Fail Status Data Register 0 */
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#define TMS570_PBIST_FSRDL1_OFFSET 0x01b0 /* Fail Status Data Register 1 */
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#define TMS570_PBIST_ROM_OFFSET 0x01c0 /* ROM Mask Register */
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#define TMS570_PBIST_ALGO_OFFSET 0x01c4 /* ROM Algorithm Mask Register */
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#define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */
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#define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */
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/* Register Addresses *******************************************************************************/
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#define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET)
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#define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET)
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#define TMS570_PBIST_PCR (TMS570_PBIST_BASE+TMS570_PBIST_PCR_OFFSET)
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#define TMS570_PBIST_PACT (TMS570_PBIST_BASE+TMS570_PBIST_PACT_OFFSET)
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#define TMS570_PBIST_PBISTID (TMS570_PBIST_BASE+TMS570_PBIST_PBISTID_OFFSET)
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#define TMS570_PBIST_OVER (TMS570_PBIST_BASE+TMS570_PBIST_OVER_OFFSET)
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#define TMS570_PBIST_FSRF0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF0_OFFSET)
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#define TMS570_PBIST_FSRC0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC0_OFFSET)
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#define TMS570_PBIST_FSRC1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC1_OFFSET)
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#define TMS570_PBIST_FSRA0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA0_OFFSET)
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#define TMS570_PBIST_FSRA1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA1_OFFSET)
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#define TMS570_PBIST_FSRDL0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL0_OFFSET)
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#define TMS570_PBIST_FSRDL1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL1_OFFSET)
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#define TMS570_PBIST_ROM (TMS570_PBIST_BASE+TMS570_PBIST_ROM_OFFSET)
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#define TMS570_PBIST_ALGO (TMS570_PBIST_BASE+TMS570_PBIST_ALGO_OFFSET)
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#define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET)
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#define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET)
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/* Register Bit-Field Definitions *******************************************************************/
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/* RAM Configuration Register */
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#define PBIST_RAMT_
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/* Datalogger Register */
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#define PBIST_DLR_
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/* Program Control Register */
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#define PBIST_PCR_
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/* PBIST Activate/ROM Clock Enable Register */
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#define PBIST_PACT_
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/* PBIST ID Register */
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#define PBIST_PBISTID_
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/* Override Register */
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#define PBIST_OVER_
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/* Fail Status Fail Register 0 */
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#define PBIST_FSRF0_
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/* Fail Status Count Register 0 */
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#define PBIST_FSRC0_
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/* Fail Status Count Register 1 */
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#define PBIST_FSRC1_
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/* Fail Status Address 0 Register */
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#define PBIST_FSRA0_
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/* Fail Status Address 1 Register */
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#define PBIST_FSRA1_
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/* Fail Status Data Register 0 */
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#define PBIST_FSRDL0_
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/* Fail Status Data Register 1 */
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#define PBIST_FSRDL1_
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/* ROM Mask Register */
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#define PBIST_ROM_
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/* ROM Algorithm Mask Register */
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#define PBIST_ALGO_
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/* RAM Info Mask Lower Register */
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#define PBIST_RINFOL_
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/* RAM Info Mask Upper Register */
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#define PBIST_RINFOU_
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#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H */
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