From f5a0fb060d0eacd0902a4a57a77dc77c0727ab76 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 24 Feb 2015 11:16:32 -0600 Subject: [PATCH] PIC32MZ: Add Oscillator header file; Add logic to set up peripheral clocks on reset --- arch/mips/src/pic32mz/chip/pic32mz-features.h | 4 +- arch/mips/src/pic32mz/chip/pic32mz-osc.h | 233 ++++++++++++++++++ arch/mips/src/pic32mz/chip/pic32mz-prefetch.h | 36 +-- .../src/pic32mz/chip/pic32mzec-features.h | 3 + arch/mips/src/pic32mz/pic32mz-lowinit.c | 220 ++++++++++++++++- 5 files changed, 465 insertions(+), 31 deletions(-) create mode 100644 arch/mips/src/pic32mz/chip/pic32mz-osc.h diff --git a/arch/mips/src/pic32mz/chip/pic32mz-features.h b/arch/mips/src/pic32mz/chip/pic32mz-features.h index 8e395a72ea..4bc21f2583 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-features.h @@ -42,10 +42,10 @@ #include -#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2) +#if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include #else -# error "Unknown PIC32MZ family +# error Unknown PIC32MZ family #endif #endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mz-osc.h b/arch/mips/src/pic32mz/chip/pic32mz-osc.h new file mode 100644 index 0000000000..1b46fbd6a8 --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mz-osc.h @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-osc.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "pic32mz-memorymap.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Register Offsets *********************************************************/ + +#define PIC32MZ_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */ +#define PIC32MZ_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */ +#define PIC32MZ_SPLLCON_OFFSET 0x0020 /* System PLL control register */ +#define PIC32MZ_REFO1CON_OFFSET 0x0080 /* Reference oscillator control register 1 */ +#define PIC32MZ_REFO1TRIM_OFFSET 0x00a0 /* Reference oscillator trim register 1 */ +#define PIC32MZ_REFO2CON_OFFSET 0x00b0 /* Reference oscillator control register 2 */ +#define PIC32MZ_REFO2TRIM_OFFSET 0x00c0 /* Reference oscillator trim register 2 */ +#define PIC32MZ_REFO3CON_OFFSET 0x00d0 /* Reference oscillator control register 3 */ +#define PIC32MZ_REFO3TRIM_OFFSET 0x00e0 /* Reference oscillator trim register 3 */ +#define PIC32MZ_REFO4CON_OFFSET 0x00f0 /* Reference oscillator control register 4 */ +#define PIC32MZ_REFO4TRIM_OFFSET 0x0100 /* Reference oscillator trim register 4 */ +#define PIC32MZ_PB1DIV_OFFSET 0x0100 /* Peripheral bus 1 clock divisor control register */ +#define PIC32MZ_PB2DIV_OFFSET 0x0110 /* Peripheral bus 2 clock divisor control register */ +#define PIC32MZ_PB3DIV_OFFSET 0x0120 /* Peripheral bus 3 clock divisor control register */ +#define PIC32MZ_PB4DIV_OFFSET 0x0130 /* Peripheral bus 4 clock divisor control register */ +#define PIC32MZ_PB5DIV_OFFSET 0x0140 /* Peripheral bus 5 clock divisor control register */ +#define PIC32MZ_PB6DIV_OFFSET 0x0150 /* Peripheral bus 6 clock divisor control register */ +#define PIC32MZ_PB7DIV_OFFSET 0x0160 /* Peripheral bus 7 clock divisor control register */ +#define PIC32MZ_PB8DIV_OFFSET 0x0170 /* Peripheral bus 8 clock divisor control register */ + +/* Register Addresses *******************************************************/ + +#define PIC32MZ_OSCCON (PIC32MZ_OSC_K1BASE+PIC32MZ_OSCCON_OFFSET) +#define PIC32MZ_OSCTUN (PIC32MZ_OSC_K1BASE+PIC32MZ_OSCTUN_OFFSET) + +#define PIC32MZ_SPLLCON (PIC32MZ_OSC_K1BASE+PIC32MZ_SPLLCON_OFFSET) +#define PIC32MZ_REFO1CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO1CON_OFFSET) +#define PIC32MZ_REFO1TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO1TRIM_OFFSET) +#define PIC32MZ_REFO2CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO2CON_OFFSET) +#define PIC32MZ_REFO2TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO2TRIM_OFFSET) +#define PIC32MZ_REFO3CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO3CON_OFFSET) +#define PIC32MZ_REFO3TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO3TRIM_OFFSET) +#define PIC32MZ_REFO4CON (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO4CON_OFFSET) +#define PIC32MZ_REFO4TRIM (PIC32MZ_OSC_K1BASE+PIC32MZ_REFO4TRIM_OFFSET) +#define PIC32MZ_PB1DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB1DIV_OFFSET) +#define PIC32MZ_PB2DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB2DIV_OFFSET) +#define PIC32MZ_PB3DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB3DIV_OFFSET) +#define PIC32MZ_PB4DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB4DIV_OFFSET) +#define PIC32MZ_PB5DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB5DIV_OFFSET) +#define PIC32MZ_PB6DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB6DIV_OFFSET) +#define PIC32MZ_PB7DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB7DIV_OFFSET) +#define PIC32MZ_PB8DIV (PIC32MZ_OSC_K1BASE+PIC32MZ_PB8DIV_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Oscillator control register offset */ + +#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */ +#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */ +#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */ +#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */ +#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */ +#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */ +#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */ +#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */ +#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT) +# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* Internal fast RC oscillator / FRCDIV */ +# define OSCCON_NOSC_SPLL (1 << OSCCON_NOSC_SHIFT) /* System PLL */ +# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator (HS or EC) */ +# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */ +# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Internal low power RC oscillator */ +# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* Internal fast RC / FRCDIV */ +#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */ +#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT) +# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* Internal fast RC oscillator / FRCDIV */ +# define OSCCON_COSC_SPLL (1 << OSCCON_COSC_SHIFT) /* System PLL */ +# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator (HS or EC) */ +# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */ +# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Internal low power RC oscillator */ +# define OSCCON_COSC_BFRC (5 << OSCCON_COSC_SHIFT) /* Back-up Fast RC Oscillator */ +# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* Internal fast RC / FRCDIV */ +#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */ +#define OSCCON_DRMEN (1 << 23) /* Bit 23: Dream mode enable */ +#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */ +#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV(n) ((uint32_t)((n)-1) << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT) + +/* FRC tuning register offset (6-bit, signed twos complement) */ + +#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */ +#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT) +# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT) +# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT) +# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT) + +/* System PLL control register */ + +#define SPLLCON_PLLRANGE_SHIFT (0) /* Bits 0-2: System PLL Frequency Range Selection bits */ +#define SPLLCON_PLLRANGE_MASK (7 << SPLLCON_PLLRANGE_SHIFT) +# define SPLLCON_PLLRANGE_BYPASS (0 << SPLLCON_PLLRANGE_SHIFT) /* Bypass */ +# define SPLLCON_PLLRANGE_5_10MHZ (1 << SPLLCON_PLLRANGE_SHIFT) /* 5-10 MHz */ +# define SPLLCON_PLLRANGE_8_16MHZ (2 << SPLLCON_PLLRANGE_SHIFT) /* 8-16 MHz */ +# define SPLLCON_PLLRANGE_13_26MHZ (3 << SPLLCON_PLLRANGE_SHIFT) /* 13-26 MHz */ +# define SPLLCON_PLLRANGE_21_42MHZ (4 << SPLLCON_PLLRANGE_SHIFT) /* 21-42 MHz */ +# define SPLLCON_PLLRANGE_34_64MHZ (5 << SPLLCON_PLLRANGE_SHIFT) /* 34-64 MHz */ +#define SPLLCON_PLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Source bit */ +#define SPLLCON_PLLIDIV_SHIFT (8) /* Bits 8-10: System PLL Input Clock Divider bits */ +#define SPLLCON_PLLIDIV_MASK (7 << SPLLCON_PLLIDIV_SHIFT) +# define SPLLCON_PLLIDIV(n) ((uint32_t)((n)-1) << SPLLCON_PLLIDIV_SHIFT) /* Divide by n, n=1..8 */ +#define SPLLCON_PLLMULT_SHIFT (16) /* Bits 16-22 <6:0>: System PLL Multiplier bits */ +#define SPLLCON_PLLMULT_MASK (0x7f << SPLLCON_PLLMULT_SHIFT) +# define SPLLCON_PLLMULT(n) ((uint32_t)((n)-1) << SPLLCON_PLLMULT_SHIFT) /* Muliply by n, n=1..128 */ +#define SPLLCON_PLLODIV_SHIFT (24) /* Bits 24-26: System PLL Output Clock Divider bits */ +#define SPLLCON_PLLODIV_MASK (7 << SPLLCON_PLLODIV_SHIFT) +# define SPLLCON_PLLODIV_2 (1 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 2 */ +# define SPLLCON_PLLODIV_4 (2 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 4 */ +# define SPLLCON_PLLODIV_8 (3 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 8 */ +# define SPLLCON_PLLODIV_16 (4 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 16 */ +# define SPLLCON_PLLODIV_32 (5 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 32 */ + +/* Reference oscillator control register n, n=1..4 */ + +#define REFOCON_ROSEL_SHIFT (0) /* Bits 0-3: Reference Clock Source Select bits */ +#define REFOCON_ROSEL_MASK (15 << REFOCON_ROSEL_SHIFT) +# define REFOCON_ROSEL_SYSCLK (0 << REFOCON_ROSEL_SHIFT) /* SYSCLK */ +# define REFOCON_ROSEL_PBCLK1 (1 << REFOCON_ROSEL_SHIFT) /* PBCLK1 */ +# define REFOCON_ROSEL_POSC (2 << REFOCON_ROSEL_SHIFT) /* POSC */ +# define REFOCON_ROSEL_FRC (3 << REFOCON_ROSEL_SHIFT) /* FRC */ +# define REFOCON_ROSEL_LPRC (4 << REFOCON_ROSEL_SHIFT) /* LPRC */ +# define REFOCON_ROSEL_SOSC (5 << REFOCON_ROSEL_SHIFT) /* SOSC */ +# define REFOCON_ROSEL_SPLL (7 << REFOCON_ROSEL_SHIFT) /* System PLL output */ +# define REFOCON_ROSEL_REFCLKI (8 << REFOCON_ROSEL_SHIFT) /* REFCLKIx */ +# define REFOCON_ROSEL_BFRC (9 << REFOCON_ROSEL_SHIFT) /* BFRC */ +#define REFOCON_ACTIVE (1 << 8) /* Bit 8: Reference Clock Request Status bit */ +#define REFOCON_DIVSWEN (1 << 9) /* Bit 9: Divider Switch Enable bit */ +#define REFOCON_RSLP (1 << 11) /* Bit 11: Reference Oscillator Module Run in Sleep bit */ +#define REFOCON_OE (1 << 12) /* Bit 12: Reference Clock Output Enable bit */ +#define REFOCON_SIDL (1 << 13) /* Bit 13: Peripheral Stop in Idle Mode bit */ +#define REFOCON_ON (1 << 15) /* Bit 15: Output Enable bit */ +#define REFOCON_RODIV_SHIFT (16) /* Bits 16-30: Reference Clock Divider bits */ +#define REFOCON_RODIV_MASK (0x7fff << REFOCON_RODIV_SHIFT) +# define REFOCON_RODIV(n) ((uint32_t)(n) << REFOCON_RODIV_SHIFT) + +/* Reference oscillator trim register n, n=1..4 */ + +#define REFOTRIM_SHIFT (23) /* Bits 23-31: Reference Oscillator Trim bits */ +#define REFOTRIM_MASK (0x1ff << REFOTRIM_SHIFT) + +/* Peripheral bus n clock divisor control register n=1..8 */ + +#define PBDIV_SHIFT (0) /* Bits 0-6: Peripheral Bus Clock Divisor Control bits */ +#define PBDIV_MASK (0x7f << PBDIV_SHIFT) +# define PBDIV(n) ((uint32_t)((n)-1) << PBDIV_SHIFT) /* PBCLK = SYSLCK/n, n=1..128 */ +#define PBDIV_PBDIVRDY (1 << 11) /* Bit 11: Peripheral Bus Clock Divisor Ready bit */ +#define PBDIV_ON (1 << 15) /* Bit 15: Peripheral Bus Output Clock Enable bit */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mz-prefetch.h b/arch/mips/src/pic32mz/chip/pic32mz-prefetch.h index 636b788c93..1279451c7a 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-prefetch.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-prefetch.h @@ -49,34 +49,34 @@ ********************************************************************************************/ /* Prefetch register offsets ****************************************************************/ -#define PIC32MZ_PREFETCH_PRECON_OFFSET 0x0000 /* Prefetch module control register */ -#define PIC32MZ_PREFETCH_PRESTAT_OFFSET 0x0000 /* Prefetch module status register */ +#define PIC32MZ_PRECON_OFFSET 0x0000 /* Prefetch module control register */ +#define PIC32MZ_PRESTAT_OFFSET 0x0000 /* Prefetch module status register */ /* Prefetch register addresses **************************************************************/ -#define PIC32MZ_PREFETCH_PRECON (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PREFETCH_PRECON_OFFSET) -#define PIC32MZ_PREFETCH_PRESTAT (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PREFETCH_PRESTAT_OFFSET) +#define PIC32MZ_PRECON (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PRECON_OFFSET) +#define PIC32MZ_PRESTAT (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PRESTAT_OFFSET) /* Prefetch register bit field definitions **************************************************/ /* Prefetch module control register */ -#define PREFETCH_PRECON_PFMWS_SHIFT (0) /* Bits 0-2: PFM Access Time */ -#define PREFETCH_PRECON_PFMWS_MASK (7 << PREFETCH_PRECON_PFMWS_SHIFT) -# define PREFETCH_PRECON_PFMWS(n) ((uint32_t)(n) << PREFETCH_PRECON_PFMWS_SHIFT) /* n wait states, n=0..7 */ -#define PREFETCH_PRECON_PREFEN_SHIFT (4) /* Bit 4-5: Predictive Prefetch Enable */ -#define PREFETCH_PRECON_PREFEN_MASK (3 << PREFETCH_PRECON_PREFEN_SHIFT) -# define PREFETCH_PRECON_PREFEN_DISABLE (0 << PREFETCH_PRECON_PREFEN_SHIFT) /* Disable predictive prefetch */ -# define PREFETCH_PRECON_PREFEN_CPUI (1 << PREFETCH_PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions */ -# define PREFETCH_PRECON_PREFEN_CPUID (2 << PREFETCH_PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions and data */ -# define PREFETCH_PRECON_PREFEN_ANY (3 << PREFETCH_PRECON_PREFEN_SHIFT) /* Predictive prefetch any address */ -#define PREFETCH_PRECON_PFMSECEN (1 << 26) /* Bit 26: Flash SEC Interrupt Enable */ +#define PRECON_PFMWS_SHIFT (0) /* Bits 0-2: PFM Access Time */ +#define PRECON_PFMWS_MASK (7 << PRECON_PFMWS_SHIFT) +# define PRECON_PFMWS(n) ((uint32_t)(n) << PRECON_PFMWS_SHIFT) /* n wait states, n=0..7 */ +#define PRECON_PREFEN_SHIFT (4) /* Bit 4-5: Predictive Prefetch Enable */ +#define PRECON_PREFEN_MASK (3 << PRECON_PREFEN_SHIFT) +# define PRECON_PREFEN_DISABLE (0 << PRECON_PREFEN_SHIFT) /* Disable predictive prefetch */ +# define PRECON_PREFEN_CPUI (1 << PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions */ +# define PRECON_PREFEN_CPUID (2 << PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions and data */ +# define PRECON_PREFEN_ANY (3 << PRECON_PREFEN_SHIFT) /* Predictive prefetch any address */ +#define PRECON_PFMSECEN (1 << 26) /* Bit 26: Flash SEC Interrupt Enable */ /* Prefetch module status register */ -#define PREFETCH_PRESTAT_PFMSECCNT_SHIFT (0) /* Bits 0-7: Flash SEC Count bits */ -#define PREFETCH_PRESTAT_PFMSECCNT_MASK (0xff << PREFETCH_PRESTAT_PFMSECCNT_SHIFT) -#define PREFETCH_PRESTAT_PFMSEC (1 << 26) /* Bit 26: Flash Single-bit Error Corrected Status */ -#define PREFETCH_PRESTAT_PFMDED (1 << 27) /* Bit 27: Flash Double-bit Error Detected Status */ +#define PRESTAT_PFMSECCNT_SHIFT (0) /* Bits 0-7: Flash SEC Count bits */ +#define PRESTAT_PFMSECCNT_MASK (0xff << PRESTAT_PFMSECCNT_SHIFT) +#define PRESTAT_PFMSEC (1 << 26) /* Bit 26: Flash Single-bit Error Corrected Status */ +#define PRESTAT_PFMDED (1 << 27) /* Bit 27: Flash Double-bit Error Detected Status */ #endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PREFETCH_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/arch/mips/src/pic32mz/chip/pic32mzec-features.h index 83aa92cd2d..0ec30b3d66 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-features.h @@ -189,6 +189,9 @@ /* System key register: 32-bit key value */ +#define UNLOCK_SYSKEY_0 (0xaa996655ul) +#define UNLOCK_SYSKEY_1 (0x556699aaul) + /* External bus interface address pin configuration register */ #define CFGEBIA_EBIA0N_SHIFT (0) /* Bits 0-23: EBI address pin 0 enable */ diff --git a/arch/mips/src/pic32mz/pic32mz-lowinit.c b/arch/mips/src/pic32mz/pic32mz-lowinit.c index 455cac21c8..15534c37ca 100644 --- a/arch/mips/src/pic32mz/pic32mz-lowinit.c +++ b/arch/mips/src/pic32mz/pic32mz-lowinit.c @@ -47,7 +47,9 @@ #include "up_internal.h" #include "up_arch.h" +#include "chip/pic32mz-features.h" #include "chip/pic32mz-prefetch.h" +#include "chip/pic32mz-osc.h" #include "pic32mz-lowconsole.h" #include "pic32mz-lowinit.h" @@ -57,9 +59,10 @@ ****************************************************************************/ /* Maximum Frequencies ******************************************************/ -#define MAX_FLASH_ECC_HZ 66000000 /* Maximum FLASH speed (Hz) with ECC */ -#define MAX_FLASH_NOECC_HZ 83000000 /* Maximum FLASH speed (Hz) without ECC */ -#define MAX_PBCLOCK 80000000 /* Max peripheral bus speed (Hz) */ +#define MAX_FLASH_ECC_HZ 66000000 /* Maximum FLASH speed (Hz) with ECC */ +#define MAX_FLASH_NOECC_HZ 83000000 /* Maximum FLASH speed (Hz) without ECC */ +#define MAX_PBCLK 100000000 /* Max peripheral bus speed (Hz) */ +#define MAX_PBCLK7 200000000 /* Max peripheral bus speed (Hz) for PBCLK7 */ /* Sanity checks ************************************************************/ @@ -70,13 +73,90 @@ # error "Bad BOARD_CPU_CLOCK calculcation in board.h" #endif -#define CALC_PBCLOCK (CALC_SYSCLOCK / BOARD_PBDIV) -#if CALC_PBCLOCK != BOARD_PBCLOCK -# error "Bad BOARD_PBCLOCK calculcation in board.h" +#define CALC_PBCLK1 (CALC_SYSCLOCK / BOARD_PB1DIV) +#if CALC_PBCLK1 != BOARD_PBCLK1 +# error "Bad BOARD_PBCLK1 calculcation in board.h" #endif -#if CALC_PBCLOCK > MAX_PBCLOCK -# error "PBCLOCK exceeds maximum value" +#if CALC_PBCLK1 > MAX_PBCLK +# error "PBCLK1 exceeds maximum value" +#endif + +#ifdef BOARD_PBCLK2_ENABLE +# define CALC_PBCLK2 (CALC_SYSCLOCK / BOARD_PB2DIV) +# if CALC_PBCLK2 != BOARD_PBCLK2 +# error "Bad BOARD_PBCLK2 calculcation in board.h" +# endif + +# if CALC_PBCLK2 > MAX_PBCLK +# error "PBCLK2 exceeds maximum value" +# endif +#endif + +#ifdef BOARD_PBCLK3_ENABLE +# define CALC_PBCLK3 (CALC_SYSCLOCK / BOARD_PB3DIV) +# if CALC_PBCLK3 != BOARD_PBCLK3 +# error "Bad BOARD_PBCLK3 calculcation in board.h" +# endif + +# if CALC_PBCLK3 > MAX_PBCLK +# error "PBCLK3 exceeds maximum value" +# endif +#endif + +#ifdef BOARD_PBCLK4_ENABLE +# define CALC_PBCLK4 (CALC_SYSCLOCK / BOARD_PB4DIV) +# if CALC_PBCLK4 != BOARD_PBCLK4 +# error "Bad BOARD_PBCLK4 calculcation in board.h" +# endif + +# if CALC_PBCLK4 > MAX_PBCLK +# error "PBCLK4 exceeds maximum value" +# endif +#endif + +#ifdef BOARD_PBCLK5_ENABLE +# define CALC_PBCLK5 (CALC_SYSCLOCK / BOARD_PB5DIV) +# if CALC_PBCLK5 != BOARD_PBCLK5 +# error "Bad BOARD_PBCLK5 calculcation in board.h" +# endif + +# if CALC_PBCLK5 > MAX_PBCLK +# error "PBCLK5 exceeds maximum value" +# endif +#endif + +#ifdef BOARD_PBCLK6_ENABLE +# define CALC_PBCLK6 (CALC_SYSCLOCK / BOARD_PB6DIV) +# if CALC_PBCLK6 != BOARD_PBCLK6 +# error "Bad BOARD_PBCLK6 calculcation in board.h" +# endif + +# if CALC_PBCLK6 > MAX_PBCLK +# error "PBCLK6 exceeds maximum value" +# endif +#endif + +#ifdef BOARD_PBCLK7_ENABLE +# define CALC_PBCLK7 (CALC_SYSCLOCK / BOARD_PB7DIV) +# if CALC_PBCLK7 != BOARD_PBCLK7 +# error "Bad BOARD_PBCLK7 calculcation in board.h" +# endif + +# if CALC_PBCLK7 > MAX_PBCLK7 +# error "PBCLK7 exceeds maximum value" +# endif +#endif + +#ifdef BOARD_PBCLK8_ENABLE +# define CALC_PBCLK8 (CALC_SYSCLOCK / BOARD_PB8DIV) +# if CALC_PBCLK8 != BOARD_PBCLK8 +# error "Bad BOARD_PBCLK8 calculcation in board.h" +# endif + +# if CALC_PBCLK8 > MAX_PBCLK +# error "PBCLK8 exceeds maximum value" +# endif #endif /**************************************************************************** @@ -118,7 +198,6 @@ static inline void pic32mz_prefetch(void) unsigned int nwaits; unsigned int residual; uint32_t regval; - /* Configure pre-fetch cache FLASH wait states (assuming ECC is enabled) */ @@ -137,8 +216,8 @@ static inline void pic32mz_prefetch(void) * data. */ - regval = (PREFETCH_PRECON_PREFEN_CPUID | PREFETCH_PRECON_PFMWS(nwaits)); - putreg32(regval, PIC32MZ_PREFETCH_PRECON); + regval = (PRECON_PREFEN_CPUID | PRECON_PFMWS(nwaits)); + putreg32(regval, PIC32MZ_PRECON); } /**************************************************************************** @@ -166,6 +245,123 @@ static inline void pic32mz_k0cache(void) UNUSED(regval); } +/**************************************************************************** + * Name: pic32mz_pbclk + * + * Description: + * Configure peripheral bus clocking + * + * Assumptions: + * Interrupts are disabled. + * + ****************************************************************************/ + +static inline void pic32mz_pbclk(void) +{ + uint32_t regval; + + /* Perform the unlock sequence */ + + putreg32(UNLOCK_SYSKEY_0, PIC32MZ_SYSKEY); + putreg32(UNLOCK_SYSKEY_1, PIC32MZ_SYSKEY); + + /* PBCLK1 + * Peripherals: OSC2 pin + * + * NOTES: + * - PBCLK1 is used by system modules and cannot be turned off + * - PBCLK1 divided by 2 is available on the OSC2 pin in certain clock + * modes. + */ + + regval = (PBDIV_ON | PBDIV(BOARD_PB1DIV)); + putreg32(regval, PIC32MZ_PB1DIV); + + /* PBCLK2 + * Peripherals: PMP, I2C, UART, SPI + */ + +#ifdef BOARD_PBCLK2_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB2DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB2DIV); + + /* PBCLK3 + * Peripherals: ADC, Comparator, Timers, Output Compare, Input Compare + * + * NOTES: + * - Timer 1 uses SOSC + */ + +#ifdef BOARD_PBCLK3_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB3DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB3DIV); + +/* PBCLK4 + * Peripherals: Ports + */ + +#ifdef BOARD_PBCLK4_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB4DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB4DIV); + +/* PBCLK5 + * Peripherals: Flash, Crypto, RND, USB, CAN, Ethernet, SQI + * + * NOTES: + * - PBCLK5 is used to fetch data from/to the Flash Controller, while the + * FRC clock is used for programming + */ + +#ifdef BOARD_PBCLK5_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB5DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB5DIV); + +/* PBCLK6 + * Peripherals: + */ + +#ifdef BOARD_PBCLK6_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB6DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB6DIV); + +/* PBCLK7 + * Peripherals: CPU, Deadman timer + */ + +#ifdef BOARD_PBCLK7_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB7DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB7DIV); + +/* PBCLK8 + * Peripherals: EBI + */ + +#ifdef BOARD_PBCLK8_ENABLE + regval = (PBDIV_ON | PBDIV(BOARD_PB8DIV)); +#else + regval = 0; +#endif + putreg32(regval, PIC32MZ_PB8DIV); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -191,6 +387,8 @@ void pic32mz_lowinit(void) pic32mz_k0cache();; + /* Configure peripheral clocking */ + /* Initialize a console (probably a serial console) */ pic32mz_consoleinit();