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arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2021-08-15 04:15:28 +08:00 committed by Abdelatif Guettouche
parent fad0c3b38b
commit f63d1cfbbb
24 changed files with 89 additions and 44 deletions
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20
arch/arm/src/armv7-m/nvic.h
View File

@ -417,6 +417,11 @@
#define NVIC_DEMCR (ARMV7M_NVIC_BASE + NVIC_DEMCR_OFFSET)
#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
#define NVIC_FPCCR (ARMV7M_NVIC_BASE + NVIC_FPCCR_OFFSET)
#define NVIC_FPCAR (ARMV8M_NVIC_BASE + NVIC_FPCAR_OFFSET)
#define NVIC_FPDSCR (ARMV8M_NVIC_BASE + NVIC_FPDSCR_OFFSET)
#define NVIC_MVFR0 (ARMV8M_NVIC_BASE + NVIC_MVFR0_OFFSET)
#define NVIC_MVFR1 (ARMV8M_NVIC_BASE + NVIC_MVFR1_OFFSET)
#define NVIC_MVFR2 (ARMV8M_NVIC_BASE + NVIC_MVFR2_OFFSET)
#define NVIC_ICIALLU (ARMV7M_NVIC_BASE + NVIC_ICIALLU_OFFSET)
#define NVIC_ICIMVAU (ARMV7M_NVIC_BASE + NVIC_ICIMVAU_OFFSET)
#define NVIC_DCIMVAU (ARMV7M_NVIC_BASE + NVIC_DCIMVAU_OFFSET)
@ -656,6 +661,21 @@
#define NVIC_DEMCR_MONREQ (1 << 19) /* Bit 19: Monitor wake-up mode */
#define NVIC_DEMCR_TRCENA (1 << 24) /* Bit 24: Enable trace and debug blocks */
/* Floating-Point Context Control Register (FPCCR) */
#define NVIC_FPCCR_LSPACT (1 << 0) /* Bit 0: Lazy state preservation active */
#define NVIC_FPCCR_USER (1 << 1) /* Bit 1: User privilege */
#define NVIC_FPCCR_THREAD (1 << 3) /* Bit 3: Thread mode */
#define NVIC_FPCCR_HFRDY (1 << 4) /* Bit 4: HardFault ready */
#define NVIC_FPCCR_MMRDY (1 << 5) /* Bit 5: MemManage ready */
#define NVIC_FPCCR_BFRDY (1 << 6) /* Bit 6: BusFault ready */
#define NVIC_FPCCR_MONRDY (1 << 8) /* Bit 8: DebugMonitor ready */
#define NVIC_FPCCR_SPLIMVIOL (1 << 9) /* Bit 9: Stack pointer limit violation */
#define NVIC_FPCCR_UFRDY (1 << 10) /* Bit 10: UsageFault ready */
#define NVIC_FPCCR_CLRONRET (1 << 28) /* Bit 28: Clear on return */
#define NVIC_FPCCR_LSPEN (1 << 30) /* Bit 30: Lazy state preservation enable */
#define NVIC_FPCCR_ASPEN (1 << 31) /* Bit 31: Automatic state preservation enable */
/* Instruction Tightly-Coupled Memory Control Register (ITCMCR) */
/* Data Tightly-Coupled Memory Control Registers (DTCMCR */

25
arch/arm/src/armv8-m/nvic.h
View File

@ -437,6 +437,11 @@
#define NVIC_DEMCR (ARMV8M_NVIC_BASE + NVIC_DEMCR_OFFSET)
#define NVIC_STIR (ARMV8M_NVIC_BASE + NVIC_STIR_OFFSET)
#define NVIC_FPCCR (ARMV8M_NVIC_BASE + NVIC_FPCCR_OFFSET)
#define NVIC_FPCAR (ARMV8M_NVIC_BASE + NVIC_FPCAR_OFFSET)
#define NVIC_FPDSCR (ARMV8M_NVIC_BASE + NVIC_FPDSCR_OFFSET)
#define NVIC_MVFR0 (ARMV8M_NVIC_BASE + NVIC_MVFR0_OFFSET)
#define NVIC_MVFR1 (ARMV8M_NVIC_BASE + NVIC_MVFR1_OFFSET)
#define NVIC_MVFR2 (ARMV8M_NVIC_BASE + NVIC_MVFR2_OFFSET)
#define NVIC_ICIALLU (ARMV8M_NVIC_BASE + NVIC_ICIALLU_OFFSET)
#define NVIC_ICIMVAU (ARMV8M_NVIC_BASE + NVIC_ICIMVAU_OFFSET)
#define NVIC_DCIMVAC (ARMV8M_NVIC_BASE + NVIC_DCIMVAC_OFFSET)
@ -675,6 +680,26 @@
#define NVIC_DEMCR_MONREQ (1 << 19) /* Bit 19: Monitor wake-up mode */
#define NVIC_DEMCR_TRCENA (1 << 24) /* Bit 24: Enable trace and debug blocks */
/* Floating-Point Context Control Register (FPCCR) */
#define NVIC_FPCCR_LSPACT (1 << 0) /* Bit 0: Lazy state preservation active */
#define NVIC_FPCCR_USER (1 << 1) /* Bit 1: User privilege */
#define NVIC_FPCCR_SECURE (1 << 2) /* Bit 2: Security status */
#define NVIC_FPCCR_THREAD (1 << 3) /* Bit 3: Thread mode */
#define NVIC_FPCCR_HFRDY (1 << 4) /* Bit 4: HardFault ready */
#define NVIC_FPCCR_MMRDY (1 << 5) /* Bit 5: MemManage ready */
#define NVIC_FPCCR_BFRDY (1 << 6) /* Bit 6: BusFault ready */
#define NVIC_FPCCR_SFRDY (1 << 7) /* Bit 7: SecureFault ready */
#define NVIC_FPCCR_MONRDY (1 << 8) /* Bit 8: DebugMonitor ready */
#define NVIC_FPCCR_SPLIMVIOL (1 << 9) /* Bit 9: Stack pointer limit violation */
#define NVIC_FPCCR_UFRDY (1 << 10) /* Bit 10: UsageFault ready */
#define NVIC_FPCCR_TS (1 << 26) /* Bit 26: Treat as Secure */
#define NVIC_FPCCR_CLRONRETS (1 << 27) /* Bit 27: Clear on return, Secure only */
#define NVIC_FPCCR_CLRONRET (1 << 28) /* Bit 28: Clear on return */
#define NVIC_FPCCR_LSPENS (1 << 29) /* Bit 29: Lazy state preservation enable Secure */
#define NVIC_FPCCR_LSPEN (1 << 30) /* Bit 30: Lazy state preservation enable */
#define NVIC_FPCCR_ASPEN (1 << 31) /* Bit 31: Automatic state preservation enable */
/* Instruction Tightly-Coupled Memory Control Register (ITCMCR) */
/* Data Tightly-Coupled Memory Control Registers (DTCMCR */

4
arch/arm/src/cxd56xx/cxd56_start.c
View File

@ -156,7 +156,7 @@ void fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -186,7 +186,7 @@ void fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/efm32/efm32_start.c
View File

@ -148,7 +148,7 @@ static inline void efm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -178,7 +178,7 @@ static inline void efm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/eoss3/eoss3_start.c
View File

@ -146,7 +146,7 @@ static inline void eoss3_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -176,7 +176,7 @@ static inline void eoss3_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/imxrt/imxrt_start.c
View File

@ -130,7 +130,7 @@ static inline void imxrt_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -160,7 +160,7 @@ static inline void imxrt_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/kinetis/kinetis_start.c
View File

@ -142,7 +142,7 @@ static inline void kinetis_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -172,7 +172,7 @@ static inline void kinetis_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
View File

@ -131,7 +131,7 @@ static inline void lpc17_40_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -161,7 +161,7 @@ static inline void lpc17_40_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/lpc43xx/lpc43_start.c
View File

@ -199,7 +199,7 @@ static inline void lpc43_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -229,7 +229,7 @@ static inline void lpc43_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/lpc54xx/lpc54_start.c
View File

@ -129,7 +129,7 @@ static inline void lpc54_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -157,7 +157,7 @@ static inline void lpc54_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/max326xx/common/max326_start.c
View File

@ -129,7 +129,7 @@ static inline void max326_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -157,7 +157,7 @@ static inline void max326_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/nrf52/nrf52_start.c
View File

@ -116,7 +116,7 @@ static inline void nrf52_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -144,7 +144,7 @@ static inline void nrf52_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/s32k1xx/s32k1xx_start.c
View File

@ -169,7 +169,7 @@ static inline void s32k1xx_fpu_config(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -197,7 +197,7 @@ static inline void s32k1xx_fpu_config(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/sam34/sam_start.c
View File

@ -144,7 +144,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -174,7 +174,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/samd5e5/sam_start.c
View File

@ -146,7 +146,7 @@ static inline void sam_fpu_configure(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -176,7 +176,7 @@ static inline void sam_fpu_configure(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/samv7/sam_start.c
View File

@ -141,7 +141,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -171,7 +171,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/stm32/stm32_start.c
View File

@ -147,7 +147,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -177,7 +177,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/stm32f7/stm32_start.c
View File

@ -141,7 +141,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -171,7 +171,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/stm32h7/stm32_start.c
View File

@ -156,7 +156,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -186,7 +186,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/stm32l4/stm32l4_start.c
View File

@ -156,7 +156,7 @@ static inline void stm32l4_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -186,7 +186,7 @@ static inline void stm32l4_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/stm32l5/stm32l5_start.c
View File

@ -159,7 +159,7 @@ static inline void stm32l5_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -189,7 +189,7 @@ static inline void stm32l5_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/tiva/cc13xx/cc13xx_start.c
View File

@ -143,7 +143,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -173,7 +173,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/tiva/common/lmxx_tm4c_start.c
View File

@ -134,7 +134,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -164,7 +164,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */

4
arch/arm/src/xmc4/xmc4_start.c
View File

@ -165,7 +165,7 @@ static inline void xmc4_fpu_config(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
@ -195,7 +195,7 @@ static inline void xmc4_fpu_config(void)
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */