diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h
index 2615599b36..1aa87f63bd 100644
--- a/arch/arm/src/armv7-m/nvic.h
+++ b/arch/arm/src/armv7-m/nvic.h
@@ -417,6 +417,11 @@
 #define NVIC_DEMCR                      (ARMV7M_NVIC_BASE + NVIC_DEMCR_OFFSET)
 #define NVIC_STIR                       (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
 #define NVIC_FPCCR                      (ARMV7M_NVIC_BASE + NVIC_FPCCR_OFFSET)
+#define NVIC_FPCAR                      (ARMV8M_NVIC_BASE + NVIC_FPCAR_OFFSET)
+#define NVIC_FPDSCR                     (ARMV8M_NVIC_BASE + NVIC_FPDSCR_OFFSET)
+#define NVIC_MVFR0                      (ARMV8M_NVIC_BASE + NVIC_MVFR0_OFFSET)
+#define NVIC_MVFR1                      (ARMV8M_NVIC_BASE + NVIC_MVFR1_OFFSET)
+#define NVIC_MVFR2                      (ARMV8M_NVIC_BASE + NVIC_MVFR2_OFFSET)
 #define NVIC_ICIALLU                    (ARMV7M_NVIC_BASE + NVIC_ICIALLU_OFFSET)
 #define NVIC_ICIMVAU                    (ARMV7M_NVIC_BASE + NVIC_ICIMVAU_OFFSET)
 #define NVIC_DCIMVAU                    (ARMV7M_NVIC_BASE + NVIC_DCIMVAU_OFFSET)
@@ -656,6 +661,21 @@
 #define NVIC_DEMCR_MONREQ               (1 << 19) /* Bit 19: Monitor wake-up mode */
 #define NVIC_DEMCR_TRCENA               (1 << 24) /* Bit 24: Enable trace and debug blocks */
 
+/*  Floating-Point Context Control Register (FPCCR) */
+
+#define NVIC_FPCCR_LSPACT               (1 << 0)  /* Bit 0:  Lazy state preservation active */
+#define NVIC_FPCCR_USER                 (1 << 1)  /* Bit 1:  User privilege */
+#define NVIC_FPCCR_THREAD               (1 << 3)  /* Bit 3:  Thread mode */
+#define NVIC_FPCCR_HFRDY                (1 << 4)  /* Bit 4:  HardFault ready */
+#define NVIC_FPCCR_MMRDY                (1 << 5)  /* Bit 5:  MemManage ready */
+#define NVIC_FPCCR_BFRDY                (1 << 6)  /* Bit 6:  BusFault ready */
+#define NVIC_FPCCR_MONRDY               (1 << 8)  /* Bit 8:  DebugMonitor ready */
+#define NVIC_FPCCR_SPLIMVIOL            (1 << 9)  /* Bit 9:  Stack pointer limit violation */
+#define NVIC_FPCCR_UFRDY                (1 << 10) /* Bit 10: UsageFault ready */
+#define NVIC_FPCCR_CLRONRET             (1 << 28) /* Bit 28: Clear on return */
+#define NVIC_FPCCR_LSPEN                (1 << 30) /* Bit 30: Lazy state preservation enable */
+#define NVIC_FPCCR_ASPEN                (1 << 31) /* Bit 31: Automatic state preservation enable */
+
 /* Instruction Tightly-Coupled Memory Control Register (ITCMCR) */
 
 /* Data Tightly-Coupled Memory Control Registers (DTCMCR */
diff --git a/arch/arm/src/armv8-m/nvic.h b/arch/arm/src/armv8-m/nvic.h
index 1c20d68fd0..bd8109a91b 100644
--- a/arch/arm/src/armv8-m/nvic.h
+++ b/arch/arm/src/armv8-m/nvic.h
@@ -437,6 +437,11 @@
 #define NVIC_DEMCR                      (ARMV8M_NVIC_BASE + NVIC_DEMCR_OFFSET)
 #define NVIC_STIR                       (ARMV8M_NVIC_BASE + NVIC_STIR_OFFSET)
 #define NVIC_FPCCR                      (ARMV8M_NVIC_BASE + NVIC_FPCCR_OFFSET)
+#define NVIC_FPCAR                      (ARMV8M_NVIC_BASE + NVIC_FPCAR_OFFSET)
+#define NVIC_FPDSCR                     (ARMV8M_NVIC_BASE + NVIC_FPDSCR_OFFSET)
+#define NVIC_MVFR0                      (ARMV8M_NVIC_BASE + NVIC_MVFR0_OFFSET)
+#define NVIC_MVFR1                      (ARMV8M_NVIC_BASE + NVIC_MVFR1_OFFSET)
+#define NVIC_MVFR2                      (ARMV8M_NVIC_BASE + NVIC_MVFR2_OFFSET)
 #define NVIC_ICIALLU                    (ARMV8M_NVIC_BASE + NVIC_ICIALLU_OFFSET)
 #define NVIC_ICIMVAU                    (ARMV8M_NVIC_BASE + NVIC_ICIMVAU_OFFSET)
 #define NVIC_DCIMVAC                    (ARMV8M_NVIC_BASE + NVIC_DCIMVAC_OFFSET)
@@ -675,6 +680,26 @@
 #define NVIC_DEMCR_MONREQ               (1 << 19) /* Bit 19: Monitor wake-up mode */
 #define NVIC_DEMCR_TRCENA               (1 << 24) /* Bit 24: Enable trace and debug blocks */
 
+/*  Floating-Point Context Control Register (FPCCR) */
+
+#define NVIC_FPCCR_LSPACT               (1 << 0)  /* Bit 0:  Lazy state preservation active */
+#define NVIC_FPCCR_USER                 (1 << 1)  /* Bit 1:  User privilege */
+#define NVIC_FPCCR_SECURE               (1 << 2)  /* Bit 2:  Security status */
+#define NVIC_FPCCR_THREAD               (1 << 3)  /* Bit 3:  Thread mode */
+#define NVIC_FPCCR_HFRDY                (1 << 4)  /* Bit 4:  HardFault ready */
+#define NVIC_FPCCR_MMRDY                (1 << 5)  /* Bit 5:  MemManage ready */
+#define NVIC_FPCCR_BFRDY                (1 << 6)  /* Bit 6:  BusFault ready */
+#define NVIC_FPCCR_SFRDY                (1 << 7)  /* Bit 7:  SecureFault ready */
+#define NVIC_FPCCR_MONRDY               (1 << 8)  /* Bit 8:  DebugMonitor ready */
+#define NVIC_FPCCR_SPLIMVIOL            (1 << 9)  /* Bit 9:  Stack pointer limit violation */
+#define NVIC_FPCCR_UFRDY                (1 << 10) /* Bit 10: UsageFault ready */
+#define NVIC_FPCCR_TS                   (1 << 26) /* Bit 26: Treat as Secure */
+#define NVIC_FPCCR_CLRONRETS            (1 << 27) /* Bit 27: Clear on return, Secure only */
+#define NVIC_FPCCR_CLRONRET             (1 << 28) /* Bit 28: Clear on return */
+#define NVIC_FPCCR_LSPENS               (1 << 29) /* Bit 29: Lazy state preservation enable Secure */
+#define NVIC_FPCCR_LSPEN                (1 << 30) /* Bit 30: Lazy state preservation enable */
+#define NVIC_FPCCR_ASPEN                (1 << 31) /* Bit 31: Automatic state preservation enable */
+
 /* Instruction Tightly-Coupled Memory Control Register (ITCMCR) */
 
 /* Data Tightly-Coupled Memory Control Registers (DTCMCR */
diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c
index 8376f71f6d..af58453550 100644
--- a/arch/arm/src/cxd56xx/cxd56_start.c
+++ b/arch/arm/src/cxd56xx/cxd56_start.c
@@ -156,7 +156,7 @@ void fpuconfig(void)
    */
 
   regval  = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -186,7 +186,7 @@ void fpuconfig(void)
    */
 
   regval  = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index 3740ddbe13..eb9453d94b 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -148,7 +148,7 @@ static inline void efm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -178,7 +178,7 @@ static inline void efm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/eoss3/eoss3_start.c b/arch/arm/src/eoss3/eoss3_start.c
index b0ce3d2597..a288c6ace2 100644
--- a/arch/arm/src/eoss3/eoss3_start.c
+++ b/arch/arm/src/eoss3/eoss3_start.c
@@ -146,7 +146,7 @@ static inline void eoss3_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -176,7 +176,7 @@ static inline void eoss3_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c
index 7c256266c9..f6f6a59c10 100644
--- a/arch/arm/src/imxrt/imxrt_start.c
+++ b/arch/arm/src/imxrt/imxrt_start.c
@@ -130,7 +130,7 @@ static inline void imxrt_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -160,7 +160,7 @@ static inline void imxrt_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index 37cabf6b50..8fa57d415b 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -142,7 +142,7 @@ static inline void kinetis_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -172,7 +172,7 @@ static inline void kinetis_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
index 9ba9694f04..1928eb37fb 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
@@ -131,7 +131,7 @@ static inline void lpc17_40_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -161,7 +161,7 @@ static inline void lpc17_40_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c
index 26c351547c..f7bbed8a61 100644
--- a/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/arch/arm/src/lpc43xx/lpc43_start.c
@@ -199,7 +199,7 @@ static inline void lpc43_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -229,7 +229,7 @@ static inline void lpc43_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/lpc54xx/lpc54_start.c b/arch/arm/src/lpc54xx/lpc54_start.c
index 768b9e1d11..67c9c9bf77 100644
--- a/arch/arm/src/lpc54xx/lpc54_start.c
+++ b/arch/arm/src/lpc54xx/lpc54_start.c
@@ -129,7 +129,7 @@ static inline void lpc54_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -157,7 +157,7 @@ static inline void lpc54_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/max326xx/common/max326_start.c b/arch/arm/src/max326xx/common/max326_start.c
index 24766c7ee2..63575b2ce8 100644
--- a/arch/arm/src/max326xx/common/max326_start.c
+++ b/arch/arm/src/max326xx/common/max326_start.c
@@ -129,7 +129,7 @@ static inline void max326_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -157,7 +157,7 @@ static inline void max326_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c
index fb167f4dbd..ea5a739630 100644
--- a/arch/arm/src/nrf52/nrf52_start.c
+++ b/arch/arm/src/nrf52/nrf52_start.c
@@ -116,7 +116,7 @@ static inline void nrf52_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -144,7 +144,7 @@ static inline void nrf52_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c
index 08f3d31d4f..c364b4c9d2 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_start.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_start.c
@@ -169,7 +169,7 @@ static inline void s32k1xx_fpu_config(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -197,7 +197,7 @@ static inline void s32k1xx_fpu_config(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c
index e4cc45b452..9486b0cb1d 100644
--- a/arch/arm/src/sam34/sam_start.c
+++ b/arch/arm/src/sam34/sam_start.c
@@ -144,7 +144,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -174,7 +174,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/samd5e5/sam_start.c b/arch/arm/src/samd5e5/sam_start.c
index a09d621e8b..e81a11dc4c 100644
--- a/arch/arm/src/samd5e5/sam_start.c
+++ b/arch/arm/src/samd5e5/sam_start.c
@@ -146,7 +146,7 @@ static inline void sam_fpu_configure(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -176,7 +176,7 @@ static inline void sam_fpu_configure(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c
index d3be8b0c35..fae64399b5 100644
--- a/arch/arm/src/samv7/sam_start.c
+++ b/arch/arm/src/samv7/sam_start.c
@@ -141,7 +141,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -171,7 +171,7 @@ static inline void sam_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index c7a5f1d4f5..5182f0f7c2 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -147,7 +147,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -177,7 +177,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c
index 82f2ea4361..162fc98f62 100644
--- a/arch/arm/src/stm32f7/stm32_start.c
+++ b/arch/arm/src/stm32f7/stm32_start.c
@@ -141,7 +141,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -171,7 +171,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c
index 726df7e191..5b33d03fb7 100644
--- a/arch/arm/src/stm32h7/stm32_start.c
+++ b/arch/arm/src/stm32h7/stm32_start.c
@@ -156,7 +156,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -186,7 +186,7 @@ static inline void stm32_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c
index 8c371be8ae..2002cf0b60 100644
--- a/arch/arm/src/stm32l4/stm32l4_start.c
+++ b/arch/arm/src/stm32l4/stm32l4_start.c
@@ -156,7 +156,7 @@ static inline void stm32l4_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -186,7 +186,7 @@ static inline void stm32l4_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c
index f82f671f13..8041bbd69f 100644
--- a/arch/arm/src/stm32l5/stm32l5_start.c
+++ b/arch/arm/src/stm32l5/stm32l5_start.c
@@ -159,7 +159,7 @@ static inline void stm32l5_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -189,7 +189,7 @@ static inline void stm32l5_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_start.c b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
index 4585538422..f96824aa59 100644
--- a/arch/arm/src/tiva/cc13xx/cc13xx_start.c
+++ b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
@@ -143,7 +143,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -173,7 +173,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_start.c b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
index 014e08e891..1911260a71 100644
--- a/arch/arm/src/tiva/common/lmxx_tm4c_start.c
+++ b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
@@ -134,7 +134,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -164,7 +164,7 @@ static inline void tiva_fpuconfig(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c
index f2b2f96083..21682115e1 100644
--- a/arch/arm/src/xmc4/xmc4_start.c
+++ b/arch/arm/src/xmc4/xmc4_start.c
@@ -165,7 +165,7 @@ static inline void xmc4_fpu_config(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */
@@ -195,7 +195,7 @@ static inline void xmc4_fpu_config(void)
    */
 
   regval = getreg32(NVIC_FPCCR);
-  regval &= ~((1 << 31) | (1 << 30));
+  regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
 
   /* Enable full access to CP10 and CP11 */