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Merge remote-tracking branch 'origin/master' into netiob

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This commit is contained in:
Gregory Nutt 2014-06-29 13:22:23 -06:00
commit f684e7a805
11 changed files with 119 additions and 92 deletions

8
ChangeLog

@ -7569,3 +7569,11 @@
devif/devif.h (2014-6-28).
* net/devif: Rename many functions in net/devif from uip_* to devif_*
(2014-6-28).
* configs/sama5d4-ek/src/nsh: The SAMA5D4-EK NSH configuration now
supports the RTC by default (2014-6-29).
* arch/arm/src/sama5/Kconfig and sam_hsmci.c: Add configuration to
assign an XDMAC channel to an HSMCI (2014-6029).
* Various fixes for networking and tiny webserver from Max (2014-6-29).
* SAMA5: Various fixes related to DMA in order to get the HSMCI
driver to build for the SAMA5D4 (2014-6-29).
* SAMA5D4-EK: Fix HSMCI card-detect pin selection (2014-6-29).

6
arch/arm/src/sama5/sam_adc.c

@ -319,12 +319,12 @@
#ifdef CONFIG_SAMA5_ADC_DMA
# define DMA_FLAGS \
DMACH_FLAG_FIFOCFG_LARGEST | \
((SAM_IRQ_ADC << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF2 | \
DMACH_FLAG_PERIPHPID(SAM_IRQ_ADC) | DMACH_FLAG_PERIPHAHB_AHB_IF2 | \
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
DMACH_FLAG_PERIPHWIDTH_16BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_16BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_1)
DMACH_FLAG_MEMCHUNKSIZE_1 | DMACH_FLAG_MEMBURST_4)
#endif
/* Pick an unused channel number */

8
arch/arm/src/sama5/sam_dmac.h

@ -100,7 +100,8 @@
# define DMACH_FLAG_PERIPHPID_SHIFT (2) /* Bits 1-7: Peripheral PID */
# define DMACH_FLAG_PERIPHPID_MASK (0x3f << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID(n) ((uint32_t) << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID(n) ((uint32_t)(n) << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID_MAX DMACH_FLAG_PERIPHPID_MASK
# define DMACH_FLAG_PERIPHH2SEL (1 << 8) /* Bits 8: HW handshaking */
# define DMACH_FLAG_PERIPHISPERIPH (1 << 9) /* Bits 9: 0=memory; 1=peripheral */
# define DMACH_FLAG_PERIPHAHB_SHIFT (10) /* Bits 10-11: Peripheral ABH layer number */
@ -138,6 +139,7 @@
# define DMACH_FLAG_MEMPID_SHIFT (17) /* Bits 17-22: Memory PID */
# define DMACH_FLAG_MEMPID_MASK (0x3f << DMACH_FLAG_MEMPID_SHIFT)
# define DMACH_FLAG_MEMPID(n) ((uint32_t)(n) << DMACH_FLAG_MEMPID_SHIFT)
# define DMACH_FLAG_MEMPID_MAX DMACH_FLAG_MEMPID_MASK
# define DMACH_FLAG_MEMH2SEL (1 << 23) /* Bits 23: HW handshaking */
# define DMACH_FLAG_MEMISPERIPH (1 << 24) /* Bits 24: 0=memory; 1=peripheral */
# define DMACH_FLAG_MEMAHB_SHIFT (25) /* Bits 25-26: Peripheral ABH layer number */
@ -199,7 +201,8 @@
# define DMACH_FLAG_PERIPHPID_SHIFT (0) /* Bits 0-7: Peripheral PID */
# define DMACH_FLAG_PERIPHPID_MASK (0x7f << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID(n) ((uint32_t) << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID(n) ((uint32_t)(n) << DMACH_FLAG_PERIPHPID_SHIFT)
# define DMACH_FLAG_PERIPHPID_MAX DMACH_FLAG_PERIPHPID_MASK
# define DMACH_FLAG_PERIPHH2SEL (0) /* No HW handshaking */
# define DMACH_FLAG_PERIPHISPERIPH (1 << 7) /* Bit 7: 0=memory; 1=peripheral */
# define DMACH_FLAG_PERIPHAHB_MASK (1 << 8) /* Bit 8: Peripheral ABH layer 1 */
@ -234,6 +237,7 @@
*/
# define DMACH_FLAG_MEMPID(n) (0) /* No memory peripheral identifier */
# define DMACH_FLAG_MEMPID_MAX (0)
# define DMACH_FLAG_MEMH2SEL (0) /* No HW handshaking */
# define DMACH_FLAG_MEMISPERIPH (0) /* No peripheral-to-peripheral */
# define DMACH_FLAG_MEMAHB_MASK (1 << 16) /* Bit 16: Memory ABH layer 1 */

31
arch/arm/src/sama5/sam_hsmci.c

@ -100,6 +100,11 @@
# error "HSMCI2 support requires CONFIG_SAMA5_DMAC1"
# endif
/* System Bus Interfaces */
# define HSMCI_SYSBUS_IF DMACH_FLAG_PERIPHAHB_AHB_IF2
# define MEMORY_SYSBUS_IF DMACH_FLAG_MEMAHB_AHB_IF0
#elif defined(ATSAMA5D4)
/* The SAMA5D3 has two HSMCI blocks: HSMCI0-1. They can be driven
* either by XDMAC0 (secure) or XDMAC1 (unsecure).
@ -125,6 +130,18 @@
# error No valid DMA configuration for HSMCI1
# endif
/* System Bus Interfaces
*
* HSMCI0 is on H32MX, APB1; HSMCI1 is on H32MX, APB0. Both are
* accessible on MATRIX IF1.
*
* Memory is available on either port 5 (IF0 for both XDMAC0 and 1) or
* port 6 (IF1 for both XDMAC0 and 1).
*/
# define HSMCI_SYSBUS_IF DMACH_FLAG_PERIPHAHB_AHB_IF1
# define MEMORY_SYSBUS_IF DMACH_FLAG_MEMAHB_AHB_IF0
#else
# error Unrecognized SAMA5 architecture
#endif
@ -193,22 +210,22 @@
#ifdef HSCMI_FIFODMA
# define DMA_FLAGS(pid) \
(((pid) << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF2 | \
(DMACH_FLAG_PERIPHPID(pid) | HSMCI_SYSBUS_IF | \
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHINCREMENT | \
DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMPID_MAX | MEMORY_SYSBUS_IF | \
DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_4)
DMACH_FLAG_MEMCHUNKSIZE_4 | DMACH_FLAG_MEMBURST_4)
#else
# define DMA_FLAGS(pid) \
(((pid) << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF2 | \
(DMACH_FLAG_PERIPHPID(pid) | HSMCI_SYSBUS_IF | \
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMPID_MAX | MEMORY_SYSBUS_IF | \
DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_4)
DMACH_FLAG_MEMCHUNKSIZE_4 | DMACH_FLAG_MEMBURST_4)
#endif
@ -1172,7 +1189,7 @@ static void sam_cmddump(struct sam_dev_s *priv)
{
sam_hsmcidump(priv, &priv->cmdsamples[SAMPLENDX_AFTER_CMDR],
"After command setup");
sam_hsmcidump(priv, &g_cmdsamples[SAMPLENDX_AT_WAKEUP],
sam_hsmcidump(priv, &priv->cmdsamples[SAMPLENDX_AT_WAKEUP],
"After wakeup");
#ifdef CONFIG_SAMA5_HSMCI_XFRDEBUG
priv->cmdinitialized = false;

18
arch/arm/src/sama5/sam_nand.c

@ -109,28 +109,28 @@
#define NFCSRAM_DMA_FLAGS \
DMACH_FLAG_FIFOCFG_LARGEST | \
(((0x3f) << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF0 | \
(DMACH_FLAG_PERIPHPID_MAX | DMACH_FLAG_PERIPHAHB_AHB_IF0 | \
DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHINCREMENT | \
DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_1)
DMACH_FLAG_MEMCHUNKSIZE_1 | DMACH_FLAG_MEMBURST_4)
#define NAND_DMA_FLAGS8 \
DMACH_FLAG_FIFOCFG_LARGEST | \
(((0x3f) << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF0 | \
(DMACH_FLAG_PERIPHPID_MAX | DMACH_FLAG_PERIPHAHB_AHB_IF0 | \
DMACH_FLAG_PERIPHWIDTH_8BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_8BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_1)
DMACH_FLAG_MEMCHUNKSIZE_1 | DMACH_FLAG_MEMBURST_4)
#define NAND_DMA_FLAGS16 \
DMACH_FLAG_FIFOCFG_LARGEST | \
(((0x3f) << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF0 | \
(DMACH_FLAG_PERIPHPID_MAX | DMACH_FLAG_PERIPHAHB_AHB_IF0 | \
DMACH_FLAG_PERIPHWIDTH_16BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_16BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_1)
DMACH_FLAG_MEMCHUNKSIZE_1 | DMACH_FLAG_MEMBURST_4)
/****************************************************************************
* Private Types

16
arch/arm/src/sama5/sam_spi.c

@ -1436,14 +1436,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
* provided on the SPI bus.
*/
rxflags = DMACH_FLAG_FIFOCFG_LARGEST |
((uint32_t)spi->pid << DMACH_FLAG_PERIPHPID_SHIFT) |
rxflags = DMACH_FLAG_FIFOCFG_LARGEST | DMACH_FLAG_PERIPHPID(spi->pid) |
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |
DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHWIDTH_8BITS |
DMACH_FLAG_PERIPHCHUNKSIZE_1 |
((uint32_t)(0x3f) << DMACH_FLAG_MEMPID_SHIFT) |
DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX |
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_8BITS |
DMACH_FLAG_MEMCHUNKSIZE_1;
DMACH_FLAG_MEMCHUNKSIZE_1 | DMACH_FLAG_MEMBURST_4;
if (!rxbuffer)
{
@ -1460,14 +1458,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
rxflags |= DMACH_FLAG_MEMINCREMENT;
}
txflags = DMACH_FLAG_FIFOCFG_LARGEST |
((uint32_t)spi->pid << DMACH_FLAG_PERIPHPID_SHIFT) |
txflags = DMACH_FLAG_FIFOCFG_LARGEST | DMACH_FLAG_PERIPHPID(spi->pid) |
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |
DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHWIDTH_8BITS |
DMACH_FLAG_PERIPHCHUNKSIZE_1 |
((uint32_t)(0x3f) << DMACH_FLAG_MEMPID_SHIFT) |
DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX |
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_8BITS |
DMACH_FLAG_MEMCHUNKSIZE_1;
DMACH_FLAG_MEMCHUNKSIZE_1 | DMACH_FLAG_MEMBURST_4;
if (!txbuffer)
{

36
arch/arm/src/sama5/sam_ssc.c

@ -186,31 +186,29 @@
/* DMA configuration */
#define DMA_PID(pid) ((pid) << DMACH_FLAG_PERIPHPID_SHIFT)
#define DMA8_FLAGS \
(DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHH2SEL | \
DMACH_FLAG_PERIPHISPERIPH | DMACH_FLAG_PERIPHWIDTH_8BITS | \
DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_16BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_4)
DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX | \
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_16BITS | \
DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_4| \
DMACH_FLAG_MEMBURST_4)
#define DMA16_FLAGS \
(DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHH2SEL | \
DMACH_FLAG_PERIPHISPERIPH | DMACH_FLAG_PERIPHWIDTH_16BITS | \
DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_16BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_4)
DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX | \
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_16BITS | \
DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_4 | \
DMACH_FLAG_MEMBURST_4)
#define DMA32_FLAGS \
(DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHH2SEL | \
DMACH_FLAG_PERIPHISPERIPH | DMACH_FLAG_PERIPHWIDTH_32BITS | \
DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
DMACH_FLAG_MEMCHUNKSIZE_4)
DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX | \
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_32BITS | \
DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_4 | \
DMACH_FLAG_MEMBURST_4)
/* DMA timeout. The value is not critical; we just don't want the system to
* hang in the event that a DMA does not finish. This is set to
@ -2658,20 +2656,20 @@ static void ssc_clocking(struct sam_ssc_s *priv)
static int ssc_dma_flags(struct sam_ssc_s *priv, uint32_t *dmaflags)
{
uint32_t regval;
uint32_t flags;
switch (priv->datalen)
{
case 8:
regval = DMA8_FLAGS;
flags = DMA8_FLAGS;
break;
case 16:
regval = DMA16_FLAGS;
flags = DMA16_FLAGS;
break;
case 32:
regval = DMA32_FLAGS;
flags = DMA32_FLAGS;
break;
default:
@ -2679,7 +2677,7 @@ static int ssc_dma_flags(struct sam_ssc_s *priv, uint32_t *dmaflags)
return -ENOSYS;
}
*dmaflags = (regval | DMA_PID(priv->pid));
*dmaflags = (flags | DMACH_FLAG_PERIPHPID(priv->pid));
return OK;
}

20
arch/arm/src/sama5/sam_xdmac.c

@ -1707,7 +1707,7 @@ static inline int sam_multiple(struct sam_xdmach_s *xdmach)
*/
if ((xdmach->cc & XDMACH_CC_TYPE) == 0 ||
(xdmach->cc & XDMACH_CC_TYPE) != 0)
(xdmach->cc & XDMACH_CC_DSYNC) != 0)
{
regval |= XDMACH_CNDC_NDSUP;
}
@ -1989,7 +1989,7 @@ void weak_function up_dmainitialize(void)
}
/****************************************************************************
* Name: sam_xdmachannel
* Name: sam_dmachannel
*
* Allocate a DMA channel. This function sets aside a DMA channel then
* gives the caller exclusive access to the DMA channel.
@ -2005,7 +2005,7 @@ void weak_function up_dmainitialize(void)
*
****************************************************************************/
DMA_HANDLE sam_xdmachannel(uint8_t dmacno, uint32_t chflags)
DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
{
struct sam_xdmac_s *xdmac;
struct sam_xdmach_s *xdmach;
@ -2086,14 +2086,14 @@ DMA_HANDLE sam_xdmachannel(uint8_t dmacno, uint32_t chflags)
}
/************************************************************************************
* Name: sam_xdmaconfig
* Name: sam_dmaconfig
*
* Description:
* There are two channel usage models: (1) The channel is allocated and configured
* in one step. This is the typical case where a DMA channel performs a constant
* role. The alternative is (2) where the DMA channel is reconfigured on the fly.
* In this case, the chflags provided to sam_xdmachannel are not used and
* sam_xdmaconfig() is called before each DMA to configure the DMA channel
* In this case, the chflags provided to sam_dmachannel are not used and
* sam_dmaconfig() is called before each DMA to configure the DMA channel
* appropriately.
*
* Returned Value:
@ -2101,7 +2101,7 @@ DMA_HANDLE sam_xdmachannel(uint8_t dmacno, uint32_t chflags)
*
************************************************************************************/
void sam_xdmaconfig(DMA_HANDLE handle, uint32_t chflags)
void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
{
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
@ -2126,7 +2126,7 @@ void sam_xdmaconfig(DMA_HANDLE handle, uint32_t chflags)
*
* Description:
* Release a DMA channel. NOTE: The 'handle' used in this argument must
* NEVER be used again until sam_xdmachannel() is called again to re-gain
* NEVER be used again until sam_dmachannel() is called again to re-gain
* a valid handle.
*
* Returned Value:
@ -2390,7 +2390,7 @@ void sam_dmastop(DMA_HANDLE handle)
* Sample DMA register contents
*
* Assumptions:
* - DMA handle allocated by sam_xdmachannel()
* - DMA handle allocated by sam_dmachannel()
*
****************************************************************************/
@ -2444,7 +2444,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
* Dump previously sampled DMA register contents
*
* Assumptions:
* - DMA handle allocated by sam_xdmachannel()
* - DMA handle allocated by sam_dmachannel()
*
****************************************************************************/

50
configs/sama5d4-ek/README.txt

@ -997,7 +997,7 @@ PIO Usage
PE11/A11/TCLK2 USBB_EN5V_PE11 EN5V_USBB
PE12/A12/TIOA1/PWMH2 USBC_EN5V_PE12 EN5V_USBC
PE13/A13/TIOB1/PWML2 PB_USER1_PE13 PB_USER1
PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD
PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD ???
PE15/A15/SCK3/TIOA0 MCI1_PWR_PE15 MCI1_PWR
PE16/A16/RXD3/TIOB0 DBGU_RXD3_PE16 DBGU_RXD3 (See JP19)
PE17/A17/TXD3/TCLK0 DBGU_TXD3_PE17 DBGU_TXD3 (See JP20)
@ -1456,13 +1456,13 @@ HSMCI Card Slots
HSMCI1
------
The microSD connects vi HSMCI1. The card detect discrete is available on
PE14 (pulled high). NOTE that PE15 must be controlled to provide power
PE6 (pulled high). NOTE that PE15 must be controlled to provide power
to the HSMCI1 slot (the HSMCI0 slot is always powered).
------------------------------ ------------------- -------------------------
SAMA5D4 PIO SIGNAL USAGE
------------------------------ ------------------- -------------------------
PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD
PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD ???
PE15/A15/SCK3/TIOA0 MCI1_PWR_PE15 MCI1_PWR
PE18/A18/TIOA5/MCI1_CK PE18 MCI1_CK, EXP
PE19/A19/TIOB5/MCI1_CDA PE19 MCI1_CDA, EXP
@ -1485,12 +1485,11 @@ HSMCI Card Slots
System Type->ATSAMA5 Peripheral Support
CONFIG_SAMA5_HSMCI0=y : Enable HSMCI0 support
CONFIG_SAMA5_HSMCI1=y : Enable HSMCI1 support
CONFIG_SAMA5_XDMAC0=y : XDMAC0 is needed by HSMCI0 <- REVISIT
CONFIG_SAMA5_XDMAC1=y : XDMAC1 is needed by HSMCI1 <- REVISIT
CONFIG_SAMA5_XDMAC1=y : XDMAC1 is needed by HSMCI0/1
System Type
CONFIG_SAMA5_PIO_IRQ=y : PIO interrupts needed
CONFIG_SAMA5_PIOD_IRQ=y : Card detect pins are on PIOD
CONFIG_SAMA5_PIOE_IRQ=y : Card detect pins are on PE5 and PE6
Device Drivers -> MMC/SD Driver Support
CONFIG_MMCSD=y : Enable MMC/SD support
@ -2858,19 +2857,18 @@ SAMA4D4-EK Configuration Options
CONFIG_SAMA5_TWI2 - Two-Wire Interface 2
CONFIG_SAMA5_HSMCI0 - High Speed Multimedia Card Interface 0
CONFIG_SAMA5_HSMCI1 - High Speed Multimedia Card Interface 1
CONFIG_SAMA5_HSMCI2 - High Speed Multimedia Card Interface 2
CONFIG_SAMA5_SPI0 - Serial Peripheral Interface 0
CONFIG_SAMA5_SPI1 - Serial Peripheral Interface 1
CONFIG_SAMA5_TC0 - Timer Counter 0 (ch. 0, 1, 2)
CONFIG_SAMA5_TC1 - Timer Counter 1 (ch. 3, 4, 5)
CONFIG_SAMA5_PWM - Pulse Width Modulation Controller
CONFIG_SAMA5_ADC - Touch Screen ADC Controller
CONFIG_SAMA5_DMAC0 - DMA Controller 0
CONFIG_SAMA5_DMAC1 - DMA Controller 1
CONFIG_SAMA5_XDMAC0 - XDMA Controller 0
CONFIG_SAMA5_XDMAC1 - XDMA Controller 1
CONFIG_SAMA5_UHPHS - USB Host High Speed
CONFIG_SAMA5_UDPHS - USB Device High Speed
CONFIG_SAMA5_GMAC - Gigabit Ethernet MAC
CONFIG_SAMA5_EMAC0 - Ethernet MAC 0
CONFIG_SAMA5_EMAC0 - Ethernet MAC 0 (GMAC0)
CONFIG_SAMA5_EMAC1 - Ethernet MAC 1 (GMAC1)
CONFIG_SAMA5_LCDC - LCD Controller
CONFIG_SAMA5_ISI - Image Sensor Interface
CONFIG_SAMA5_SSC0 - Synchronous Serial Controller 0
@ -3094,9 +3092,11 @@ Configurations
This is a little program to help debug of code in DRAM. It does the
following:
- It configures DRAM,
- It loads and Intel HEX file into DRAM over the terminal port,
- Waits for you to break in with GDB.
- Sets the clocking so that the SAMA5 is running at 528MHz.
- Configures DRAM,
- Loads and Intel HEX file into DRAM over the terminal port,
- Waits for you to break in with GDB (or optionally starts the
newly loaded program).
At that point, you can set the PC and begin executing from SDRAM under
debug control. See the section entitled "Creating and Using
@ -3330,16 +3330,20 @@ Configurations
will need to install a battery in the battery holder (J12) and close
the jumper, JP13.
8. The SAMA5D4-EK includes for an AT25 serial DataFlash. Support for that
serial FLASH can be enabled by modifying the NuttX configuration as
described above in the paragraph entitled "AT25 Serial FLASH".
8. Support for HSMCI0 and HSMCI1 is built-in by default. The SAMA4D4-EK
provides a two SD memory card slots: (1) a full size SD card slot
(J10), and (2) a microSD memory card slot (J11). The full size SD
card slot connects via HSMCI0; the microSD connects vi HSMCI1.
Support for both SD slots can be enabled with the settings provided
in the paragraph entitled "HSMCI Card Slots" above.
9. Enabling HSMCI support. The SAMA4D4-EK provides a two SD memory
card slots: (1) a full size SD card slot (J10), and (2) a microSD
memory card slot (J11). The full size SD card slot connects via HSMCI0;
the microSD connects vi HSMCI1. Support for both SD slots can be enabled
with the settings provided in the paragraph entitled "HSMCI Card Slots"
above.
NOTE: For now I am boot off the microSD slot so, unless are booting
in a different manner, this HSMCI1 slot may not be useful to you.
9. The SAMA5D4-EK includes for an AT25 serial DataFlash. That support is
NOT enabled in this configuration. Support for that serial FLASH can
be enabled by modifying the NuttX configuration as described above in
the paragraph entitled "AT25 Serial FLASH".
10. Support the USB low-, high- and full-speed OHCI host driver can be enabled
by changing the NuttX configuration file as described in the section

4
configs/sama5d4-ek/src/sam_hsmci.c

@ -59,12 +59,12 @@
* ------------------------------ ------------------- -------------------------
*
* The microSD connects vi HSMCI1. The card detect discrete is available on
* PE14 (pulled high):
* PE6 (pulled high):
*
* ------------------------------ ------------------- -------------------------
* SAMA5D4 PIO SIGNAL USAGE
* ------------------------------ ------------------- -------------------------
* PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD
* PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD ???
* PE15/A15/SCK3/TIOA0 MCI1_PWR_PE15 MCI1_PWR
* PE18/A18/TIOA5/MCI1_CK PE18 MCI1_CK, EXP
* PE19/A19/TIOB5/MCI1_CDA PE19 MCI1_CDA, EXP

14
configs/sama5d4-ek/src/sama5d4-ek.h

@ -77,10 +77,10 @@
# undef HAVE_HSMCI
#endif
/* We need PIO interrupts on PIOD to support card detect interrupts */
/* We need PIO interrupts on PIOE to support card detect interrupts */
#if defined(HAVE_HSMCI) && !defined(CONFIG_SAMA5_PIOD_IRQ)
# warning PIOD interrupts not enabled. No MMC/SD support.
#if defined(HAVE_HSMCI) && !defined(CONFIG_SAMA5_PIOE_IRQ)
# warning PIOE interrupts not enabled. No MMC/SD support.
# undef HAVE_HSMCI
#endif
@ -346,13 +346,13 @@
#define IRQ_MCI0_CD SAM_IRQ_PE5
/* The microSD connects vi HSMCI1. The card detect discrete is available on
* PE14 (pulled high) NOTE that PE15 must be controlled to provide power
* PE6 (pulled high) NOTE that PE15 must be controlled to provide power
* to the HSMCI1 slot (the HSMCI0 slot is always powered).
*
* ------------------------------ ------------------- -------------------------
* SAMA5D4 PIO SIGNAL USAGE
* ------------------------------ ------------------- -------------------------
* PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD
* PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD ???
* PE15/A15/SCK3/TIOA0 MCI1_PWR_PE15 MCI1_PWR
* PE18/A18/TIOA5/MCI1_CK PE18 MCI1_CK, EXP
* PE19/A19/TIOB5/MCI1_CDA PE19 MCI1_CDA, EXP
@ -365,8 +365,8 @@
*/
#define PIO_MCI1_CD (PIO_INPUT | PIO_CFG_DEFAULT | PIO_CFG_DEGLITCH | \
PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN14)
#define IRQ_MCI1_CD SAM_IRQ_PE14
PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN6)
#define IRQ_MCI1_CD SAM_IRQ_PE6
#define IRQ_MCI1_PWR (PIO_OUTPUT | PIO_CFG_DEFAULT | PIO_OUTPUT_SET | \
PIO_PORT_PIOE | PIO_PIN15)