SAMV7: Add GPIO interrupt support
This commit is contained in:
Gregory Nutt
parent
dbb972b2f7
commit
f696530485
@ -247,7 +247,24 @@
|
||||
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
|
||||
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
|
||||
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
|
||||
# define SAM_NGPIOBIRQS 15
|
||||
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
|
||||
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
|
||||
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
|
||||
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
|
||||
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
|
||||
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
|
||||
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
|
||||
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
|
||||
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
|
||||
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
|
||||
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
|
||||
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
|
||||
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
|
||||
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
|
||||
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
|
||||
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
|
||||
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
|
||||
# define SAM_NGPIOBIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOBIRQS 0
|
||||
#endif
|
||||
@ -338,7 +355,33 @@
|
||||
# define SAM_IRQ_PE3 (SAM_IRQ_GPIOE_PINS+3) /* GPIOE, PIN 3 */
|
||||
# define SAM_IRQ_PE4 (SAM_IRQ_GPIOE_PINS+4) /* GPIOE, PIN 4 */
|
||||
# define SAM_IRQ_PE5 (SAM_IRQ_GPIOE_PINS+5) /* GPIOE, PIN 5 */
|
||||
# define SAM_NGPIOEIRQS 6
|
||||
# define SAM_IRQ_PE6 (SAM_IRQ_GPIOE_PINS+6) /* GPIOE, PIN 6 */
|
||||
# define SAM_IRQ_PE7 (SAM_IRQ_GPIOE_PINS+7) /* GPIOE, PIN 7 */
|
||||
# define SAM_IRQ_PE8 (SAM_IRQ_GPIOE_PINS+8) /* GPIOE, PIN 8 */
|
||||
# define SAM_IRQ_PE9 (SAM_IRQ_GPIOE_PINS+9) /* GPIOE, PIN 9 */
|
||||
# define SAM_IRQ_PE10 (SAM_IRQ_GPIOE_PINS+10) /* GPIOE, PIN 10 */
|
||||
# define SAM_IRQ_PE11 (SAM_IRQ_GPIOE_PINS+11) /* GPIOE, PIN 11 */
|
||||
# define SAM_IRQ_PE12 (SAM_IRQ_GPIOE_PINS+12) /* GPIOE, PIN 12 */
|
||||
# define SAM_IRQ_PE13 (SAM_IRQ_GPIOE_PINS+13) /* GPIOE, PIN 13 */
|
||||
# define SAM_IRQ_PE14 (SAM_IRQ_GPIOE_PINS+14) /* GPIOE, PIN 14 */
|
||||
# define SAM_IRQ_PE15 (SAM_IRQ_GPIOE_PINS+15) /* GPIOE, PIN 15 */
|
||||
# define SAM_IRQ_PE16 (SAM_IRQ_GPIOE_PINS+16) /* GPIOE, PIN 16 */
|
||||
# define SAM_IRQ_PE17 (SAM_IRQ_GPIOE_PINS+17) /* GPIOE, PIN 17 */
|
||||
# define SAM_IRQ_PE18 (SAM_IRQ_GPIOE_PINS+18) /* GPIOE, PIN 18 */
|
||||
# define SAM_IRQ_PE19 (SAM_IRQ_GPIOE_PINS+19) /* GPIOE, PIN 19 */
|
||||
# define SAM_IRQ_PE20 (SAM_IRQ_GPIOE_PINS+20) /* GPIOE, PIN 20 */
|
||||
# define SAM_IRQ_PE21 (SAM_IRQ_GPIOE_PINS+21) /* GPIOE, PIN 21 */
|
||||
# define SAM_IRQ_PE22 (SAM_IRQ_GPIOE_PINS+22) /* GPIOE, PIN 22 */
|
||||
# define SAM_IRQ_PE23 (SAM_IRQ_GPIOE_PINS+23) /* GPIOE, PIN 23 */
|
||||
# define SAM_IRQ_PE24 (SAM_IRQ_GPIOE_PINS+24) /* GPIOE, PIN 24 */
|
||||
# define SAM_IRQ_PE25 (SAM_IRQ_GPIOE_PINS+25) /* GPIOE, PIN 25 */
|
||||
# define SAM_IRQ_PE26 (SAM_IRQ_GPIOE_PINS+26) /* GPIOE, PIN 26 */
|
||||
# define SAM_IRQ_PE27 (SAM_IRQ_GPIOE_PINS+27) /* GPIOE, PIN 27 */
|
||||
# define SAM_IRQ_PE28 (SAM_IRQ_GPIOE_PINS+28) /* GPIOE, PIN 28 */
|
||||
# define SAM_IRQ_PE29 (SAM_IRQ_GPIOE_PINS+29) /* GPIOE, PIN 29 */
|
||||
# define SAM_IRQ_PE30 (SAM_IRQ_GPIOE_PINS+30) /* GPIOE, PIN 30 */
|
||||
# define SAM_IRQ_PE31 (SAM_IRQ_GPIOE_PINS+31) /* GPIOE, PIN 31 */
|
||||
# define SAM_NGPIOEIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOEIRQS 0
|
||||
#endif
|
||||
|
||||
@ -99,3 +99,7 @@ CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_gpio.c
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += sam_timerisr.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMV7_GPIO_IRQ),y)
|
||||
CHIP_CSRCS += sam_gpioirq.c
|
||||
endif
|
||||
|
||||
@ -309,7 +309,7 @@ static inline void sam_disabledefaultmaster(void)
|
||||
* Name: sam_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the SAM3/4. This does whatever setup is needed
|
||||
* Called to initialize the SAMV7. This does whatever setup is needed
|
||||
* to put the SoC in a usable state. This includes the initialization of
|
||||
* clocking using the settings in board.h. (After power-on reset, the
|
||||
* SAMV7 is initially running on a 4MHz internal RC clock). This function
|
||||
|
||||
@ -77,7 +77,7 @@ extern "C"
|
||||
* Name: sam_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
|
||||
* Called to initialize the SAMV7. This does whatever setup is needed to put the
|
||||
* SoC in a usable state. This includes the initialization of clocking using the
|
||||
* settings in board.h.
|
||||
*
|
||||
|
||||
@ -539,15 +539,9 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
|
||||
lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
|
||||
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
|
||||
#endif
|
||||
lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
|
||||
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
|
||||
@ -557,18 +551,20 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
|
||||
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4E
|
||||
lldbg("SCHMITT: %08x DELAYR:%08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET));
|
||||
#else
|
||||
lldbg("SCHMITT: %08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
|
||||
#endif
|
||||
#endif
|
||||
lldbg("SCHMITT: %08x DRIVER:%08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET));
|
||||
lldbg(" KER: %08x KRCR: %08x KDR: %08x KIMR: %08x\n",
|
||||
getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET),
|
||||
getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET));
|
||||
lldbg(" KSR: %08x KKPR: %08x KKRR: %08x\n",
|
||||
getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET),
|
||||
getreg32(base + SAM_PIO_KKRR_OFFSET));
|
||||
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_SAM_GPIO_H
|
||||
#define __ARCH_ARM_SRC_SAM34_SAM_GPIO_H
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_GPIO_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAM_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@ -270,7 +270,7 @@ static inline int sam_gpio_pinmask(gpio_pinset_t cfgset)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_GPIO_IRQ
|
||||
#ifdef CONFIG_SAMV7_GPIO_IRQ
|
||||
void sam_gpioirqinitialize(void);
|
||||
#else
|
||||
# define sam_gpioirqinitialize()
|
||||
@ -314,7 +314,7 @@ bool sam_gpioread(gpio_pinset_t pinset);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_GPIO_IRQ
|
||||
#ifdef CONFIG_SAMV7_GPIO_IRQ
|
||||
void sam_gpioirq(gpio_pinset_t pinset);
|
||||
#else
|
||||
# define sam_gpioirq(pinset)
|
||||
@ -328,7 +328,7 @@ void sam_gpioirq(gpio_pinset_t pinset);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_GPIO_IRQ
|
||||
#ifdef CONFIG_SAMV7_GPIO_IRQ
|
||||
void sam_gpioirqenable(int irq);
|
||||
#else
|
||||
# define sam_gpioirqenable(irq)
|
||||
@ -342,7 +342,7 @@ void sam_gpioirqenable(int irq);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_GPIO_IRQ
|
||||
#ifdef CONFIG_SAMV7_GPIO_IRQ
|
||||
void sam_gpioirqdisable(int irq);
|
||||
#else
|
||||
# define sam_gpioirqdisable(irq)
|
||||
@ -368,4 +368,4 @@ int sam_dumpgpio(uint32_t pinset, const char *msg);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM_GPIO_H */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_GPIO_H */
|
||||
|
||||
429
arch/arm/src/samv7/sam_gpioirq.c
Normal file
429
arch/arm/src/samv7/sam_gpioirq.c
Normal file
@ -0,0 +1,429 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samv7/sam_gpioirq.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "sam_gpio.h"
|
||||
#include "sam_periphclks.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam_pio.h"
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIO_IRQ
|
||||
|
||||
/****************************************************************************
|
||||
* Private Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpiobase
|
||||
*
|
||||
* Description:
|
||||
* Return the base address of the GPIO register set
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t sam_gpiobase(gpio_pinset_t pinset)
|
||||
{
|
||||
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
return SAM_PION_BASE(port >> GPIO_PORT_SHIFT);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpiopin
|
||||
*
|
||||
* Description:
|
||||
* Returun the base address of the GPIO register set
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_gpiopin(gpio_pinset_t pinset)
|
||||
{
|
||||
return 1 << ((pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_irqbase
|
||||
*
|
||||
* Description:
|
||||
* Return gpio information associated with this IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int sam_irqbase(int irq, uint32_t *base, int *pin)
|
||||
{
|
||||
if (irq >= SAM_IRQ_NIRQS)
|
||||
{
|
||||
#ifdef CONFIG_SAMV7_GPIOA_IRQ
|
||||
if (irq <= SAM_IRQ_PA31)
|
||||
{
|
||||
*base = SAM_PIOA_BASE;
|
||||
*pin = irq - SAM_IRQ_PA0;
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_GPIOB_IRQ
|
||||
if (irq <= SAM_IRQ_PB31)
|
||||
{
|
||||
*base = SAM_PIOB_BASE;
|
||||
*pin = irq - SAM_IRQ_PB0;
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_GPIOC_IRQ
|
||||
if (irq <= SAM_IRQ_PC31)
|
||||
{
|
||||
*base = SAM_PIOC_BASE;
|
||||
*pin = irq - SAM_IRQ_PC0;
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_GPIOD_IRQ
|
||||
if (irq <= SAM_IRQ_PD31)
|
||||
{
|
||||
*base = SAM_PIOD_BASE;
|
||||
*pin = irq - SAM_IRQ_PD0;
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_GPIOE_IRQ
|
||||
if (irq <= SAM_IRQ_PE31)
|
||||
{
|
||||
*base = SAM_PIOE_BASE;
|
||||
*pin = irq - SAM_IRQ_PE0;
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpioa/b/cinterrupt
|
||||
*
|
||||
* Description:
|
||||
* Receive GPIOA/B/C interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int sam_gpiointerrupt(uint32_t base, int irq0, void *context)
|
||||
{
|
||||
uint32_t pending;
|
||||
uint32_t bit;
|
||||
int irq;
|
||||
|
||||
pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base + SAM_PIO_IMR_OFFSET);
|
||||
for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++)
|
||||
{
|
||||
if ((pending & bit) != 0)
|
||||
{
|
||||
/* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */
|
||||
|
||||
irq_dispatch(irq, context);
|
||||
|
||||
/* Remove this from the set of pending interrupts */
|
||||
|
||||
pending &= ~bit;
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOA_IRQ
|
||||
static int sam_gpioainterrupt(int irq, void *context)
|
||||
{
|
||||
return sam_gpiointerrupt(SAM_PIOA_BASE, SAM_IRQ_PA0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOB_IRQ
|
||||
static int sam_gpiobinterrupt(int irq, void *context)
|
||||
{
|
||||
return sam_gpiointerrupt(SAM_PIOB_BASE, SAM_IRQ_PB0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOC_IRQ
|
||||
static int sam_gpiocinterrupt(int irq, void *context)
|
||||
{
|
||||
return sam_gpiointerrupt(SAM_PIOC_BASE, SAM_IRQ_PC0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOD_IRQ
|
||||
static int sam_gpiodinterrupt(int irq, void *context)
|
||||
{
|
||||
return sam_gpiointerrupt(SAM_PIOD_BASE, SAM_IRQ_PD0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOE_IRQ
|
||||
static int sam_gpioeinterrupt(int irq, void *context)
|
||||
{
|
||||
return sam_gpiointerrupt(SAM_PIOE_BASE, SAM_IRQ_PE0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpioirqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support a second level of interrupt decoding for
|
||||
* GPIO pins.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_gpioirqinitialize(void)
|
||||
{
|
||||
/* Configure GPIOA interrupts */
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOA_IRQ
|
||||
/* Enable GPIOA clocking */
|
||||
|
||||
sam_pioa_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOA interrupts */
|
||||
|
||||
(void)getreg32(SAM_PIOA_ISR);
|
||||
putreg32(0xffffffff, SAM_PIOA_IDR);
|
||||
|
||||
/* Attach and enable the GPIOA IRQ */
|
||||
|
||||
(void)irq_attach(SAM_IRQ_PIOA, sam_gpioainterrupt);
|
||||
up_enable_irq(SAM_IRQ_PIOA);
|
||||
#endif
|
||||
|
||||
/* Configure GPIOB interrupts */
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOB_IRQ
|
||||
/* Enable GPIOB clocking */
|
||||
|
||||
sam_piob_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOB interrupts */
|
||||
|
||||
(void)getreg32(SAM_PIOB_ISR);
|
||||
putreg32(0xffffffff, SAM_PIOB_IDR);
|
||||
|
||||
/* Attach and enable the GPIOB IRQ */
|
||||
|
||||
(void)irq_attach(SAM_IRQ_PIOB, sam_gpiobinterrupt);
|
||||
up_enable_irq(SAM_IRQ_PIOB);
|
||||
#endif
|
||||
|
||||
/* Configure GPIOC interrupts */
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOC_IRQ
|
||||
/* Enable GPIOC clocking */
|
||||
|
||||
sam_pioc_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOC interrupts */
|
||||
|
||||
(void)getreg32(SAM_PIOC_ISR);
|
||||
putreg32(0xffffffff, SAM_PIOC_IDR);
|
||||
|
||||
/* Attach and enable the GPIOC IRQ */
|
||||
|
||||
(void)irq_attach(SAM_IRQ_PIOC, sam_gpiocinterrupt);
|
||||
up_enable_irq(SAM_IRQ_PIOC);
|
||||
#endif
|
||||
|
||||
/* Configure GPIOD interrupts */
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOD_IRQ
|
||||
/* Enable GPIOD clocking */
|
||||
|
||||
sam_piod_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOD interrupts */
|
||||
|
||||
(void)getreg32(SAM_PIOD_ISR);
|
||||
putreg32(0xffffffff, SAM_PIOD_IDR);
|
||||
|
||||
/* Attach and enable the GPIOC IRQ */
|
||||
|
||||
(void)irq_attach(SAM_IRQ_PIOD, sam_gpiodinterrupt);
|
||||
up_enable_irq(SAM_IRQ_PIOD);
|
||||
#endif
|
||||
|
||||
/* Configure GPIOE interrupts */
|
||||
|
||||
#ifdef CONFIG_SAMV7_GPIOE_IRQ
|
||||
/* Enable GPIOE clocking */
|
||||
|
||||
sam_pioe_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOE interrupts */
|
||||
|
||||
(void)getreg32(SAM_PIOE_ISR);
|
||||
putreg32(0xffffffff, SAM_PIOE_IDR);
|
||||
|
||||
/* Attach and enable the GPIOE IRQ */
|
||||
|
||||
(void)irq_attach(SAM_IRQ_PIOE, sam_gpioeinterrupt);
|
||||
up_enable_irq(SAM_IRQ_PIOE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirq
|
||||
*
|
||||
* Description:
|
||||
* Configure an interrupt for the specified GPIO pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_gpioirq(gpio_pinset_t pinset)
|
||||
{
|
||||
uint32_t base = sam_gpiobase(pinset);
|
||||
int pin = sam_gpiopin(pinset);
|
||||
|
||||
/* Are any additional interrupt modes selected? */
|
||||
|
||||
if ((pinset & _GIO_INT_AIM) != 0)
|
||||
{
|
||||
/* Yes.. Enable additional interrupt mode */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_AIMER_OFFSET);
|
||||
|
||||
/* Level or edge detected interrupt? */
|
||||
|
||||
if ((pinset & _GPIO_INT_LEVEL) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */
|
||||
}
|
||||
|
||||
/* High level/rising edge or low level /falling edge? */
|
||||
|
||||
if ((pinset & _GPIO_INT_RH) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No.. Disable additional interrupt mode */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_AIMDR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_gpioirqenable(int irq)
|
||||
{
|
||||
uint32_t base;
|
||||
int pin;
|
||||
|
||||
if (sam_irqbase(irq, &base, &pin) == OK)
|
||||
{
|
||||
/* Clear (all) pending interrupts and enable this pin interrupt */
|
||||
|
||||
//(void)getreg32(base + SAM_PIO_ISR_OFFSET);
|
||||
putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_gpioirqdisable(int irq)
|
||||
{
|
||||
uint32_t base;
|
||||
int pin;
|
||||
|
||||
if (sam_irqbase(irq, &base, &pin) == OK)
|
||||
{
|
||||
/* Disable this pin interrupt */
|
||||
|
||||
putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SAMV7_GPIO_IRQ */
|
||||
@ -1,4 +1,5 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
* arch/arm/src/samv7/sam_mpuinit.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
@ -31,37 +32,42 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_MPUINIT_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAM_MPUINIT_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
@ -72,15 +78,15 @@ extern "C"
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_mpuinitialize
|
||||
*
|
||||
* Description:
|
||||
* Configure the MPU to permit user-space access to only unrestricted SAM3/4
|
||||
* Configure the MPU to permit user-space access to only unrestricted SAMV7
|
||||
* resources.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user