stm32_hrtim: GPIOs configuration + EEV and FAULT strucutres
This commit is contained in:
raiden00pl
parent
d35a060a41
commit
f6ba4642a3
@ -144,6 +144,24 @@
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# define HRTIM_HAVE_CHOPPER 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN)
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# define HRTIM_HAVE_SYNC 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \
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defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \
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defined(CONFIG_STM32_HRTIM_FAULT5)
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# define HRTIM_HAVE_FAULTS 1
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#endif
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#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \
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defined(CONFIG_STM32_HRTIM_EEV3) || defined(CONFIG_STM32_HRTIM_EEV4) || \
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defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \
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defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \
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defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10)
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# define HRTIM_HAVE_EEV 1
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -242,6 +260,92 @@ struct stm32_hrtim_slave_priv_s
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#endif
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};
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#ifdef HRTIM_HAVE_FAULTS
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/* Structure describes single HRTIM Fault configuration */
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struct stm32_hrtim_fault_cfg_s
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{
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uint8_t pol:1; /* Fault poalrity */
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uint8_t src:1; /* Fault source */
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uint8_t filter:4; /* Fault filter */
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uint8_t flts:1; /* Fault Sampling clock division */
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uint8_t lock:1; /* Fault lock */
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};
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/* Structure describes HRTIM Faults configuration */
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struct stm32_hrtim_faults_s
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{
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#ifdef CONFIG_STM32_HRTIM_FAULT1
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struct stm32_hrtim_fault_cfg_s flt1;
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT2
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struct stm32_hrtim_fault_cfg_s flt2;
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT3
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struct stm32_hrtim_fault_cfg_s flt3;
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT4
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struct stm32_hrtim_fault_cfg_s flt4;
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT5
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struct stm32_hrtim_fault_cfg_s flt5;
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#endif
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};
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#endif
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#ifdef HRTIM_HAVE_EEV
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/* Structure describes single HRTIM External Event configuration */
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struct stm32_hrtim_eev_cfg_s
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{
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uint8_t filter:4; /* External Event filter */
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uint8_t src:4; /* External Event source */
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uint8_t pol:1; /* External Event polarity */
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uint8_t sen:1; /* External Event sensivity */
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uint8_t mode:1; /* External Event mode */
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uint8_t _res:5;
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};
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/* Structure describes HRTIM External Events configuration */
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struct stm32_hrtim_eev_s
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{
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#ifdef CONFIG_STM32_HRTIM_EEV1
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struct stm32_hrtim_eev_cfg_s eev1;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV2
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struct stm32_hrtim_eev_cfg_s eev2;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV3
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struct stm32_hrtim_eev_cfg_s eev3;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV4
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struct stm32_hrtim_eev_cfg_s eev4;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV5
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struct stm32_hrtim_eev_cfg_s eev5;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV6
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struct stm32_hrtim_eev_cfg_s eev6;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV7
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struct stm32_hrtim_eev_cfg_s eev7;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV8
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struct stm32_hrtim_eev_cfg_s eev8;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV9
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struct stm32_hrtim_eev_cfg_s eev9;
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV10
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struct stm32_hrtim_eev_cfg_s eev10;
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#endif
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};
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#endif
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/* This structure describes the configuration of HRTIM device */
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struct stm32_hrtim_s
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@ -263,6 +367,12 @@ struct stm32_hrtim_s
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#ifdef CONFIG_STM32_HRTIM_TIME
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struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */
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#endif
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#ifdef HRTIM_HAVE_FAULTS
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struct stm32_hrtim_faults_s *flt;
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#endif
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#ifdef HRTIM_HAVE_EEV
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struct stm32_hrtim_eev_s *eev;
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#endif
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};
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/****************************************************************************
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@ -423,6 +533,23 @@ static struct stm32_hrtim_tim_s g_tima =
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#endif
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/* Faults data */
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#ifdef HRTIM_HAVE_FAULTS
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struct stm32_hrtim_faults_s g_flt =
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{
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#warning "missing faults data"
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};
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#endif
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/* External Events data */
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#ifdef HRTIM_HAVE_EEV
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struct stm32_hrtim_eev_s g_eev =
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{
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#warning "missing eev data"
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};
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#endif
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/* HRTIM1 private data */
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static struct stm32_hrtim_s g_hrtim1priv =
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@ -444,6 +571,12 @@ static struct stm32_hrtim_s g_hrtim1priv =
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#ifdef CONFIG_STM32_HRTIM_TIME
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.time = &g_time,
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#endif
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#ifdef HRTIM_HAVE_FAULTS
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.flt = &g_flt;
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#endif
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#ifdef HRTIM_HAVE_EEV
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.flt = &g_eev;
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#endif
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};
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struct hrtim_dev_s g_hrtim1dev =
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@ -926,7 +1059,6 @@ errout:
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return ret;
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}
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/****************************************************************************
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* Name: stm32_tim_clocks_config
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*
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@ -1024,7 +1156,183 @@ errout:
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#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC)
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static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv)
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{
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#warning "hrtim_gpios_config: missing logic"
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#ifdef HRTIM_HAVE_EEV
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FAR struct stm32_hrtim_eev_s* eev = priv->eev;
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#endif
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#ifdef HRTIM_HAVE_FAULTS
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FAR struct stm32_hrtim_faults_s* flt = priv->flt;
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#endif
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/* Configure Timer A Outputs */
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#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH1
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stm32_configgpio(GPIO_HRTIM1_CHA1);
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH2
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stm32_configgpio(GPIO_HRTIM1_CHA2);
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#endif
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/* Configure Timer B Outputs */
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#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH1
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stm32_configgpio(GPIO_HRTIM1_CHB1);
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH2
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stm32_configgpio(GPIO_HRTIM1_CHB2);
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#endif
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/* Configure Timer C Outputs */
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#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH1
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stm32_configgpio(GPIO_HRTIM1_CHC1);
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH2
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stm32_configgpio(GPIO_HRTIM1_CHC2);
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#endif
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/* Configure Timer D Outputs */
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#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH1
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stm32_configgpio(GPIO_HRTIM1_CHD1);
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH2
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stm32_configgpio(GPIO_HRTIM1_CHD2);
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#endif
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/* Configure Timer E Outputs */
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#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH1
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stm32_configgpio(GPIO_HRTIM1_CHE1);
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2
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stm32_configgpio(GPIO_HRTIM1_CHE2);
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#endif
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/* Configure SCOUT */
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#ifdef CONFIG_STM32_HRTIM_SCOUT
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stm32_configgpio(GPIO_HRTIM1_SCOUT);
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#endif
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/* Configure SCIN */
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#ifdef CONFIG_STM32_HRTIM_SCIN
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stm32_configgpio(GPIO_HRTIM1_SCIN);
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#endif
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/* Configure Faults Inputs */
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#ifdef CONFIG_STM32_HRTIM_FAULT1
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if (flt->flt1.src == HRTIM_FAULT_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_FLT1);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT2
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if (flt->flt2.src == HRTIM_FAULT_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_FLT2);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT3
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if (flt->flt3.src == HRTIM_FAULT_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_FLT3);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT4
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if (flt->flt4.src == HRTIM_FAULT_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_FLT4);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_FAULT5
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if (flt->flt5.src == HRTIM_FAULT_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_FLT5);
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}
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#endif
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/* Configure External Events Inputs */
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#ifdef CONFIG_STM32_HRTIM_EEV1
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if (eev->eev1.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV1);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV2
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if (eev->eev2.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV2);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV3
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if (eev->eev3.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV3);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV4
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if (eev->eev4.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV4);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV5
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if (eev->eev5.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV5);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV6
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if (eev->eev6.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV6);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV7
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if (eev->eev7.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV7);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV8
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if (eev->eev8.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV8);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV9
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if (eev->eev9.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV9);
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}
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#endif
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#ifdef CONFIG_STM32_HRTIM_EEV10
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if (eev->eev10.src == HRTIM_EEV_SRC_PIN)
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{
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stm32_configgpio(GPIO_HRTIM1_EEV10);
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}
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#endif
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return OK;
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}
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#endif
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@ -222,6 +222,26 @@ enum stm32_hrtim_tim_prescaler_e
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HRTIM_PRESCALER_128,
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};
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/* HRTIM Fault Source */
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enum stm32_hrtim_fault_src_e
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{
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HRTIM_FAULT_SRC_PIN,
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HRTIM_FAULT_SRC_INTERNAL
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};
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/* HRTIM External Event Source
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* NOTE: according to Table 82 from STM32F334XX Manual
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*/
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enum stm32_hrtim_eev_src_e
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{
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HRTIM_EEV_SRC_PIN,
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HRTIM_EEV_SRC_ANALOG,
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HRTIM_EEV_SRC_TRGO,
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HRTIM_EEV_SRC_ADC
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};
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struct hrtim_dev_s
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{
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#ifdef CONFIG_HRTIM
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