SAMA5 NAND: Retrofit trim page logic
This commit is contained in:
Gregory Nutt
parent
23d767a19e
commit
f6bef28d96
@ -3039,6 +3039,7 @@ config SAMA5_EBICS0_NAND
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bool "NAND Flash"
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select MTD
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select MTD_NAND
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select SAMA5_HAVE_NAND
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endchoice # CS0 Memory Type
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@ -3061,6 +3062,7 @@ config SAMA5_EBICS0_SWECC
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config SAMA5_EBICS0_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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select SAMA5_HAVE_PMECC
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---help---
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Enable hardware assisted support for ECC calculations
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@ -3120,6 +3122,7 @@ config SAMA5_EBICS1_NAND
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bool "NAND Flash"
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select MTD
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select MTD_NAND
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select SAMA5_HAVE_NAND
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endchoice # CS1 Memory Type
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@ -3142,6 +3145,7 @@ config SAMA5_EBICS1_SWECC
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config SAMA5_EBICS1_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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select SAMA5_HAVE_PMECC
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---help---
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Enable hardware assisted support for ECC calculations
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@ -3201,6 +3205,7 @@ config SAMA5_EBICS2_NAND
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bool "NAND Flash"
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select MTD
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select MTD_NAND
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select SAMA5_HAVE_NAND
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endchoice # CS2 Memory Type
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@ -3223,6 +3228,7 @@ config SAMA5_EBICS2_SWECC
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config SAMA5_EBICS2_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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select SAMA5_HAVE_PMECC
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---help---
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Enable hardware assisted support for ECC calculations
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@ -3282,6 +3288,7 @@ config SAMA5_EBICS3_NAND
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bool "NAND Flash"
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select MTD
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select MTD_NAND
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select SAMA5_HAVE_NAND
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endchoice # CS3 Memory Type
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@ -3304,6 +3311,7 @@ config SAMA5_EBICS3_SWECC
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config SAMA5_EBICS3_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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select SAMA5_HAVE_PMECC
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---help---
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Enable hardware assisted support for ECC calculations
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@ -3316,7 +3324,15 @@ config SAMA5_EBICS3_CHIPECC
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endchoice # NAND ECC type
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endif # SAMA5_EBICS3
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if SAMA5_EBICS0_NAND || SAMA5_EBICS1_NAND || SAMA5_EBICS2_NAND || SAMA5_EBICS3_NAND
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config SAMA5_HAVE_NAND
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bool
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default n
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config SAMA5_HAVE_PMECC
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bool
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default n
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if SAMA5_HAVE_NAND
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config SAMA5_NAND_READYBUSY
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bool "NAND Ready/Busy"
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@ -3336,15 +3352,23 @@ config SAMA5_NAND_CE
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void board_nand_ce(int cs, bool enable);
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if SAMA5_EBICS0_NAND || SAMA5_EBICS1_NAND || SAMA5_EBICS2_NAND || SAMA5_EBICS3_NAND
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if SAMA5_HAVE_PMECC
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config MTD_NAND_MAX_PMECCSIZE
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int "Max H/W ECC size"
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default 200
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depends on MTD_NAND_HWECC
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---help---
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Maximum HW ECC size
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config SAMA5_PMECC_TRIMPAGE
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bool "Trim page support"
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default n
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---help---
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Support page trimming. This behavior was found to fix both UBI and
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JFFS2 images written to cleanly erased NAND partitions. NOTE:
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Nothing in the code base now uses these trim pages. Option support
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is provided in case it becomes necessary in the future.
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config SAMA5_PMECC_EMBEDDEDALGO
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bool "ROM ECC detection/correction"
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default y
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@ -3386,9 +3410,8 @@ config SAMA5_PMECC_GALOIS_TABLE1024_ROMADDR
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address unless you know what you are doing.
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endif # SAMA5_PMECC_GALOIS_ROMTABLES
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endif # SAMA5_EBICS*_PMECC
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endif # SAMA5_EBICS*_NAND
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endif # SAMA5_HAVE_PMECC
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endif # SAMA5_HAVE_NAND
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endmenu # External Memory Configuration
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choice
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@ -179,7 +179,7 @@ static int nand_smc_read16(uintptr_t src, uint8_t *dest,
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static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
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uint8_t *buffer, size_t buflen);
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, void *data);
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#endif
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@ -198,7 +198,7 @@ static int nand_write(struct sam_nandcs_s *priv, bool nfcsram,
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static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, void *data, void *spare);
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, void *data);
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#endif
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@ -206,7 +206,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
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static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, const void *data, const void *spare);
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, const void *data);
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#endif
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@ -1246,7 +1246,7 @@ static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
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*
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****************************************************************************/
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, void *data)
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{
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@ -1619,7 +1619,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
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*
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****************************************************************************/
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, void *data)
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{
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@ -1684,7 +1684,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
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nand_unlock();
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return ret;
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}
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#endif /* NAND_HAVE_PMECC */
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#endif /* CONFIG_SAMA5_HAVE_PMECC */
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/****************************************************************************
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* Name: nand_writepage_noecc
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@ -1845,7 +1845,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
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*
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****************************************************************************/
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
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unsigned int page, const void *data)
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{
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@ -1953,8 +1953,8 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
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eccpersector = (pmecc_get_eccsize()) / sectersperpage;
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sectornumber = 1 << pmecc_get_pagesize();
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#if 0 /* REVISIT. See original Atmel RawNandFlash.c */
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if (isNandTrimffs() && page >= NandGetTrimPage())
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#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
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if (nand_trrimffs(priv) && page >= nand_get_trimpage(priv))
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{
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/* This behaviour was found to fix both UBI and JFFS2 images written to
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* cleanly erased NAND partitions
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@ -2000,7 +2000,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
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nand_unlock();
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return ret;
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}
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#endif /* NAND_HAVE_PMECC */
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#endif /* CONFIG_SAMA5_HAVE_PMECC */
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/****************************************************************************
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* Name: nand_eraseblock
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@ -2202,7 +2202,7 @@ static int nand_readpage(struct nand_raw_s *raw, off_t block,
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case NANDECC_CHIPECC:
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ret = nand_readpage_noecc(priv, block, page, data, spare);
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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case NANDECC_PMECC:
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DEBUGASSERT(!spare);
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ret = nand_readpage_pmecc(priv, block, page, data);
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@ -2266,7 +2266,7 @@ static int nand_writepage(struct nand_raw_s *raw, off_t block,
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case NANDECC_CHIPECC:
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ret = nand_writepage_noecc(priv, block, page, data, spare);
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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case NANDECC_PMECC:
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DEBUGASSERT(!spare);
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ret = nand_writepage_pmecc(priv, block, page, data);
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@ -2505,7 +2505,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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nand_putreg(SAM_HSMC_CTRL, HSMC_CTRL_NFCEN);
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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/* Perform one-time initialization of the PMECC */
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pmecc_initialize();
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@ -188,30 +188,30 @@
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* enabled.
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*/
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#undef HAVE_NAND
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#undef CONFIG_SAMA5_HAVE_NAND
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#ifdef CONFIG_SAMA5_EBICS0_NAND
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# define HAVE_NAND 1
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# define CONFIG_SAMA5_HAVE_NAND 1
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# define NAND_HAVE_EBICS0 1
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#else
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# define NAND_HAVE_EBICS0 0
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#endif
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#ifdef CONFIG_SAMA5_EBICS1_NAND
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# define HAVE_NAND 1
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# define CONFIG_SAMA5_HAVE_NAND 1
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# define NAND_HAVE_EBICS1 1
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#else
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# define NAND_HAVE_EBICS1 0
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#endif
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#ifdef CONFIG_SAMA5_EBICS2_NAND
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# define HAVE_NAND 1
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# define CONFIG_SAMA5_HAVE_NAND 1
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# define NAND_HAVE_EBICS2 1
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#else
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# define NAND_HAVE_EBICS2 0
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#endif
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#ifdef CONFIG_SAMA5_EBICS3_NAND
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# define HAVE_NAND 1
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# define CONFIG_SAMA5_HAVE_NAND 1
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# define NAND_HAVE_EBICS3 1
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#else
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# define NAND_HAVE_EBICS3 0
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@ -222,7 +222,7 @@
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#define NAND_NBANKS \
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(NAND_HAVE_EBICS0 + NAND_HAVE_EBICS1 + NAND_HAVE_EBICS2 + NAND_HAVE_EBICS3)
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#ifdef HAVE_NAND
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#ifdef CONFIG_SAMA5_HAVE_NAND
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/****************************************************************************
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* Public Types
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@ -242,6 +242,10 @@ struct sam_nandcs_s
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uint8_t cs; /* Chip select number (0..3) */
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volatile bool dmadone; /* True: DMA has completed */
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sem_t waitsem; /* Used to wait for DMA done */
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#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
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bool dropjss; /* Enable page trimming */
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uint16_t g_trimpage; /* Trim page number boundary */
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#endif
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DMA_HANDLE dma; /* DMA channel assigned to this CS */
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int result; /* The result of the DMA */
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@ -259,7 +263,7 @@ struct sam_nand_s
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volatile bool rbedge; /* True: Ready/busy edge detected */
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sem_t waitsem; /* Used to wait for one of the above states */
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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uint8_t ecctab[CONFIG_MTD_NAND_MAX_PMECCSIZE];
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#endif
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@ -446,11 +450,101 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval)
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putreg32(regval, regaddr);
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}
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/****************************************************************************
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* Name: nand_trimffs_enable
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*
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* Description:
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* Set current trimffs status.
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*
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* Input Parameters:
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*
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* Returned Value:
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*
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
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static inline void nand_trimffs_enable(struct sam_nandcs_s *priv, bool enable)
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{
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priv->dropjss = enable;
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}
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#else
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# define nand_trimffs_enable(p,e)
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#endif
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/****************************************************************************
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* Name: nand_trrimffs
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*
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* Description:
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* Get current trimffs status.
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*
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* Input Parameters:
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*
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* Returned Value:
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*
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
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static inline bool nand_trrimffs(struct sam_nandcs_s *priv)
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{
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return priv->dropjss;
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}
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#else
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# define nand_trrimffs(p) (false)
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#endif
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/****************************************************************************
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* Name: nand_set_trimpage
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*
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* Description:
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* Set current trimffs page.
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*
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* Input Parameters:
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* page - Start trim page.
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*
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* Returned Value:
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*
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
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static inline void nand_set_trimpage(struct sam_nandcs_s *priv, uint16_t page)
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{
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priv->trimpage = page;
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}
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#else
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# define nand_set_trimpage(p,t)
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#endif
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/****************************************************************************
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* Name: nand_get_trimpage
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*
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* Description:
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* Get current trimffs page.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Start trim page.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
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uint16_t nand_get_trimpage(struct sam_nandcs_s *priv)
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{
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return priv->trimpage;
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}
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#else
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# define nand_get_trimpage(p) (0)
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* HAVE_NAND */
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#endif /* CONFIG_SAMA5_HAVE_NAND */
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#endif /* __ARCH_ARM_SRC_SAMA5_SAM_NAND_H */
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@ -87,34 +87,30 @@
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* enabled.
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*/
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#undef NAND_HAVE_PMECC
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#undef CONFIG_SAMA5_HAVE_PMECC
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#ifdef CONFIG_SAMA5_EBICS0_PMECC
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# undef NAND_HAVE_PMECC
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# define NAND_HAVE_PMECC 1
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# define CONFIG_SAMA5_HAVE_PMECC 1
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# define NAND_HAVE_EBICS0_PMECC 1
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#else
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# define NAND_HAVE_EBICS0_PMECC 0
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#endif
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#ifdef CONFIG_SAMA5_EBICS1_PMECC
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# undef NAND_HAVE_PMECC
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# define NAND_HAVE_PMECC 1
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# define CONFIG_SAMA5_HAVE_PMECC 1
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# define NAND_HAVE_EBICS1_PMECC 1
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#else
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# define NAND_HAVE_EBICS1_PMECC 0
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#endif
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#ifdef CONFIG_SAMA5_EBICS2_PMECC
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# undef NAND_HAVE_PMECC
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# define NAND_HAVE_PMECC 1
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# define CONFIG_SAMA5_HAVE_PMECC 1
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# define NAND_HAVE_EBICS2_PMECC 1
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#else
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# define NAND_HAVE_EBICS2_PMECC 0
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#endif
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#ifdef CONFIG_SAMA5_EBICS3_PMECC
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# undef NAND_HAVE_PMECC
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# define NAND_HAVE_PMECC 1
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# define CONFIG_SAMA5_HAVE_PMECC 1
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# define NAND_HAVE_EBICS3_PMECC 1
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#else
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# define NAND_HAVE_EBICS3_PMECC 0
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@ -130,7 +126,7 @@
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* and with PMECC support enabled.
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*/
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#ifdef NAND_HAVE_PMECC
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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/* Maximum PMECC size */
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@ -381,7 +377,7 @@ uint32_t pmecc_get_pagesize(void);
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}
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#endif
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#else /* NAND_HAVE_PMECC */
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#else /* CONFIG_SAMA5_HAVE_PMECC */
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/****************************************************************************/
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/* Stub definitions to minimize conditional compilation when PMECC is
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* disabled
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@ -396,5 +392,5 @@ uint32_t pmecc_get_pagesize(void);
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# define pmecc_get_eccsize() (0)
|
||||
# define pmecc_get_pagesize() (0)
|
||||
|
||||
#endif /* NAND_HAVE_PMECC */
|
||||
#endif /* CONFIG_SAMA5_HAVE_PMECC */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_PMECC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user