Add SPI header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2485 42af7a65-404d-4744-a932-0658087f49c3
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@ -95,7 +95,7 @@
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# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
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# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
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#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */
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#define CHIPID_CIDR_SRAMSIZ_MASK (15 << bb)
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#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT)
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# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */
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# define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */
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# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */
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@ -165,7 +165,7 @@
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#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
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#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
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#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
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#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-bb17 Master 4 Priority */
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#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */
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#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
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#define MATRIX_MRCR_RCB(x) (1 << (x))
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@ -63,9 +63,9 @@
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/* 0x24000000-0x3fffffff: Undefined */
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#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
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# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
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# define SAM3U_SSC_BASE 0x40000400 /* 0x40000400-0x400007ff: Synchronous Serial Controller */
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# define SAM3U_SPI_BASE 0x40000800 /* 0x40000800-0x40000bff: Serial Peripheral Interface */
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/* 0x40000c00-0x4007ffff: Reserved */
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# define SAM3U_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */
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# define SAM3U_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
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/* 0x4000c000-0x4007ffff: Reserved */
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# define SAM3U_TC_BASE(n) (0x40080000+((n)<<6))
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# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */
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# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */
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188
arch/arm/src/sam3u/sam3u_spi.h
Executable file
188
arch/arm/src/sam3u/sam3u_spi.h
Executable file
@ -0,0 +1,188 @@
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/****************************************************************************************
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* arch/arm/src/sam3u/sam3u_spi.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H
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#define __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "sam3u_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* SPI register offsets *****************************************************************/
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#define SAM3U_SPI_CR_OFFSET 0x00 /* Control Register */
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#define SAM3U_SPI_MR_OFFSET 0x04 /* Mode Register */
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#define SAM3U_SPI_RDR_OFFSET 0x08 /* Receive Data Register */
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#define SAM3U_SPI_TDR_OFFSET 0x0c /* Transmit Data Register */
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#define SAM3U_SPI_SR_OFFSET 0x10 /* Status Register */
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#define SAM3U_SPI_IER_OFFSET 0x14 /* Interrupt Enable Register */
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#define SAM3U_SPI_IDR_OFFSET 0x18 /* Interrupt Disable Register */
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#define SAM3U_SPI_IMR_OFFSET 0x1c /* Interrupt Mask Register */
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/* 0x20-0x2c: Reserved */
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#define SAM3U_SPI_CSR0_OFFSET 0x30 /* Chip Select Register 0 */
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#define SAM3U_SPI_CSR1_OFFSET 0x34 /* Chip Select Register 1 */
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#define SAM3U_SPI_CSR2_OFFSET 0x38 /* Chip Select Register 2 */
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#define SAM3U_SPI_CSR3_OFFSET 0x3c /* Chip Select Register 3 */
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/* 0x40-0xe0: Reserved */
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#define SAM3U_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */
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#define SAM3U_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */
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/* 0xec-0xf8: Reserved*/
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/* SPI register adresses ****************************************************************/
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#define SAM3U_SPI_CR (SAM3U_SPI_BASE+SAM3U_SPI_CR_OFFSET) /* Control Register */
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#define SAM3U_SPI_MR (SAM3U_SPI_BASE+SAM3U_SPI_MR_OFFSET) /* Mode Register */
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#define SAM3U_SPI_RDR (SAM3U_SPI_BASE+SAM3U_SPI_RDR_OFFSET) /* Receive Data Register */
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#define SAM3U_SPI_TDR (SAM3U_SPI_BASE+SAM3U_SPI_TDR_OFFSET) /* Transmit Data Register */
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#define SAM3U_SPI_SR (SAM3U_SPI_BASE+SAM3U_SPI_SR_OFFSET) /* Status Register */
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#define SAM3U_SPI_IER (SAM3U_SPI_BASE+SAM3U_SPI_IER_OFFSET) /* Interrupt Enable Register */
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#define SAM3U_SPI_IDR (SAM3U_SPI_BASE+SAM3U_SPI_IDR_OFFSET) /* Interrupt Disable Register */
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#define SAM3U_SPI_IMR (SAM3U_SPI_BASE+SAM3U_SPI_IMR_OFFSET) /* Interrupt Mask Register */
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#define SAM3U_SPI_CSR0 (SAM3U_SPI_BASE+SAM3U_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
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#define SAM3U_SPI_CSR1 (SAM3U_SPI_BASE+SAM3U_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
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#define SAM3U_SPI_CSR2 (SAM3U_SPI_BASE+SAM3U_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
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#define SAM3U_SPI_CSR3 (SAM3U_SPI_BASE+SAM3U_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
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#define SAM3U_SPI_WPCR (SAM3U_SPI_BASE+SAM3U_SPI_WPCR_OFFSET) /* Write Protection Control Register */
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#define SAM3U_SPI_WPSR (SAM3U_SPI_BASE+SAM3U_SPI_WPSR_OFFSET) /* Write Protection Status Register */
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/* SPI register bit definitions *********************************************************/
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/* SPI Control Register */
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#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
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#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
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#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
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#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Mode Register */
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#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
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#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
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#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
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#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
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#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
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#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
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#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
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#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
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#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
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/* SPI Receive Data Register */
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#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
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#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT)
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#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
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/* SPI Transmit Data Register */
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#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
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#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT)
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#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
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#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
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* and SPI Interrupt Mask Register (common bit fields)
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*/
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#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
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#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
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#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
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#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
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#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
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#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
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#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
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#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
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/* SPI Chip Select Registers 0-3 */
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#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
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#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
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#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
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#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
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#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
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#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
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# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
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# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
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# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
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# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */
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# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */
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# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */
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# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
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# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
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# define SPI_CSR_BITS15 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
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#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
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#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
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#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
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#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT)
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#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
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#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
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/* SPI Write Protection Control Register */
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#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
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#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
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#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT)
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/* SPI Write Protection Status Register */
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#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
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#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT)
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#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
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#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SPI_H */
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@ -133,7 +133,7 @@
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#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */
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#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT)
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#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT)
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#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-bb31 Wake Up Input Transition 0 to 15 */
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#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */
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#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT)
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#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT)
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