Fix message queue/signal handling bugs
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3849 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
c9e3a02996
commit
f72a83961f
@ -37,10 +37,10 @@
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-include chip/Make.defs
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ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
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ifeq ($(CONFIG_ARCH_CORTEXM3),y) /* Cortex-M3 is ARMv7-M */
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ifeq ($(CONFIG_ARCH_CORTEXM3),y) # Cortex-M3 is ARMv7-M
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ARCH_SUBDIR = armv7-m
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else
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ifeq ($(CONFIG_ARCH_CORTEXM4),y) /* Cortex-M4 is ARMv7E-M */
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ifeq ($(CONFIG_ARCH_CORTEXM4),y) # Cortex-M4 is ARMv7E-M
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ARCH_SUBDIR = armv7-m
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else
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ARCH_SUBDIR = arm
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@ -301,7 +301,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N256VLL100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -344,7 +344,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60X256VLL100)
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#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -387,7 +387,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N512VLL100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
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@ -430,7 +430,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N256VML100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -473,7 +473,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60X256VML100)
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#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -516,7 +516,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N512VML100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
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@ -559,7 +559,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N256VLQ100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -602,7 +602,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60X256VLQ100)
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#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -645,7 +645,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N512VLQ100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
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@ -688,7 +688,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N256VMD100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -731,7 +731,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60X256VMD100)
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#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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@ -774,7 +774,7 @@
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(MK60N512VMD100)
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#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
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# undef KIENTIS_K40 /* Not Kinetics K40 family */
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# define KIENTIS_K60 1 /* Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
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@ -49,7 +49,11 @@
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************************************************************************************/
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/* Memory Map ***********************************************************************/
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/* The memory for the following parts is defined in Freescale document K40P144M100SF2RM */
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/* K40 Family
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*
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* The memory map for the following parts is defined in Freescale document
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* K40P144M100SF2RM
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*/
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#if defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) \
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defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) \
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@ -58,7 +62,7 @@
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# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
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* only data (Includes exception
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* vectors in first 1024 bytes) */
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# if !defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) && !defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
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# if !defined(KINETIS_FLEXMEM_SIZE)
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# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
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# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
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# endif
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@ -79,14 +83,14 @@
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# define KINETIS_ALIAS1_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
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* (AIPS-Lite) and general purpose
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* input/output (GPIO) bitband */
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/* 0x40400000 * –0x5fffffff Reserved */
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/* 0x44000000 * –0x5fffffff Reserved */
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# define KINETIS_FLEXBUS_WBBASE 0x60000000 /* –0x7fffffff FlexBus (External Memory -
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* Write-back) */
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# define KINETIS_FLEXBUS_WTBASE 0x80000000 /* –0x9fffffff FlexBus (External Memory -
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* Write-through) */
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# define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* –0xdfffffff FlexBus (External Memory -
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* Non-executable) */
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# define KINETIS_PERIPH_BASE 0xe000000 /* –0xe00fffff Private peripherals */
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# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
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/* 0xe0100000 * –0xffffffff Reserved */
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/* Peripheral Bridge 0 Memory Map ***************************************************/
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@ -107,6 +111,7 @@
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# define KINETIS_CRC_BASE 0x40032000 /* CRC */
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# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
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# define KINETIS_PDB_BASE 0x40036000 /* Programmable delay block */
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# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
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# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
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# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
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# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
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@ -125,7 +130,7 @@
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# define KINETIS_PDMUX_BASE 0x4004c000 /* Port D multiplexing control */
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# define KINETIS_PEMUX_BASE 0x4004d000 /* Port E multiplexing control */
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# define KINETIS_SWWDOG_BASE 0x40052000 /* Software watchdog */
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# define KINETIS_EXTWDOG_BASE 0x40061000 /* Software watchdog */
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# define KINETIS_EXTWDOG_BASE 0x40061000 /* External watchdog */
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# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
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# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
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# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
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@ -172,15 +177,138 @@
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# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
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# define KINETIS_MISC_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
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# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
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# define KINETIS_CRC_BASE 0xe00c0000 /* CRC */
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# define KINETIS_CRC_BASE 0xe00c0000 /* CRC */
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# define KINETIS_CRC_BASE 0xe00c0000 /* CRC */
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# define KINETIS_CRC_BASE 0xe00c0000 /* CRC */
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/* K60 Family
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*
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* The memory map for the following parts is defined in Freescale document
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* K60P144M100SF2RM
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*/
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#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) \
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defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) \
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defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
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# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
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* only data (Includes exception
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* vectors in first 1024 bytes) */
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# if !defined(KINETIS_FLEXMEM_SIZE)
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# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
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# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
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# endif
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# define KINETIS_SRAML_BASE 0x18000000 /* –0x1fffffff SRAM_L: Lower SRAM
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* (ICODE/DCODE) */
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# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
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* region */
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/* 0x20100000 * –0x21ffffff Reserved */
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# define KINETIS_ALIAS1_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
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/* 0x24000000 * –0x3fffffff Reserved */
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# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
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* bridge 0 (AIPS-Lite0) */
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# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
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* bridge 1 (AIPS-Lite1) */
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# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
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* purpose input/output (GPIO) */
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/* 0x40100000 * –0x41ffffff Reserved */
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# define KINETIS_ALIAS1_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
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* (AIPS-Lite) and general purpose
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* input/output (GPIO) bitband */
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/* 0x44000000 * –0x5fffffff Reserved */
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# define KINETIS_FLEXBUS_BASE 0x60000000 /* –0x7fffffff FlexBus */
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# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
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/* 0xe0100000 * –0xffffffff Reserved */
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/* Peripheral Bridge 0 Memory Map ***************************************************/
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# define KINETIS_PBRIDGE0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
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# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
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# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
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# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
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# define KINETIS_FLEXBUS_BASE 0x4000c000 /* FlexBus */
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# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
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# define KINETIS_FLASHC_BASE 0x4001f000 /* Flash memory controller */
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# define KINETIS_FLASH_BASE 0x40020000 /* Flash memory */
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# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
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# define KINETIS_FLEXCAN0_BASE 0x40024000 /* FlexCAN 0 */
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# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
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# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
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# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
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# define KINETIS_CRC_BASE 0x40032000 /* CRC */
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# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
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# define KINETIS_PDB_BASE 0x40036000 /* Programmable delay block */
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# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
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# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
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# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
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# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
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# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
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# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
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# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
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# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
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# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
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# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
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# define KINETIS_TSI_BASE 0x40045000 /* Touch sense interface */
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# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
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# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
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# define KINETIS_PAMUX_BASE 0x40049000 /* Port A multiplexing control */
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# define KINETIS_PBMUX_BASE 0x4004a000 /* Port B multiplexing control */
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# define KINETIS_PCMUX_BASE 0x4004b000 /* Port C multiplexing control */
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# define KINETIS_PDMUX_BASE 0x4004c000 /* Port D multiplexing control */
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# define KINETIS_PEMUX_BASE 0x4004d000 /* Port E multiplexing control */
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# define KINETIS_SWWDOG_BASE 0x40052000 /* Software watchdog */
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# define KINETIS_EXTWDOG_BASE 0x40061000 /* External watchdog */
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# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
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# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
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# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
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# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
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# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
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# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
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# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
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# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
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# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
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# define KINETIS_USBOTG_BASE 0x40072000 /* USB OTG FS/LS */
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# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
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# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
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# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
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# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
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# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
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/* Peripheral Bridge 1 Memory Map ***************************************************/
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# define KINETIS_PBRIDGE1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
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# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
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# define KINETIS_FLEXCAN1_BASE 0x400a4000 /* FlexCAN 1 */
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# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
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# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
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# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
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# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
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# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
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# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
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# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
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# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
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# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
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# define KINETIS_XBAR_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
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* purpose input/output module that shares the
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* crossbar switch slave port with the AIPS-Lite
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* is accessed at this address. */
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/* Private Peripheral Bus (PPB) Memory Map ******************************************/
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# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
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# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
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# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
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# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
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# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
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# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
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# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
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# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
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# define KINETIS_MISC_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
|
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# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
|
||||
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
|
||||
|
||||
#else
|
||||
/* The memory map for other parts is defined in other documents and may or may net
|
||||
* be the same as above. This error means that you have to look at the document and
|
||||
* determine that for yourself.
|
||||
/* The memory map for other parts is defined in other documents and may or may not
|
||||
* be the same as above (the family members are all very similar) This error just
|
||||
* means that you have to look at the document and determine for yourself if the
|
||||
* memory map is the same.
|
||||
*/
|
||||
|
||||
# error "No memory map for this Kinetis part"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user