Kinetis:Fixed CLKSRC Bit Names
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@ -328,7 +328,7 @@
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divided by the PLLFLLCLK fractional divider
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as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
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# define SIM_SOPT2_TPMSRC_OCSERCLK (2 << SIM_SOPT2_TPMSRC_SHIFT) /* OSCERCLK clock */
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# define SIM_SOPT2_TPMSRC_EXTBYP (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */
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# define SIM_SOPT2_TPMSRC_MCGIRCLK (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */
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# endif
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# if defined(KINETIS_SIM_HAS_SOPT2_I2SSRC)
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# define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */
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@ -348,7 +348,7 @@
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divided by the PLLFLLCLK fractional divider
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as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
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# define SIM_SOPT2_LPUARTSRC_OCSERCLK (2 << SIM_SOPT2_LPUARTSRC_SHIFT) /* OSCERCLK clock */
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# define SIM_SOPT2_LPUARTSRC_EXTBYP (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */
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# define SIM_SOPT2_LPUARTSRC_MCGIRCLK (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */
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# endif
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# if defined(KINETIS_SIM_HAS_SOPT2_SDHCSRC)
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# define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select */
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