Add some logic to EFM32 DMA module. Still incomplete
This commit is contained in:
Gregory Nutt
parent
6c044cbf9b
commit
f79e803e89
@ -163,6 +163,18 @@ config EFM32_GPIO_IRQ
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---help---
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Enable support for interrupting GPIO pins
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if EFM32_DMA
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config EFM32_DMA_NDESCR
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int "Pre-allocated Control Structures"
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default 8
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---help---
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DMA transfers require DMA channel control descriptors. These
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descriptors are pre-allocated and this setting provides the number
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of descriptors that will be pre-allocated.
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endif
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choice
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prompt "USART0 Mode"
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default EFM32_USART0_ISUART
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@ -42,12 +42,65 @@
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <queue.h>
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#include <assert.h>
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#include <errno.h>
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#include <nuttx/arch.h>
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#include "efm32_dma.h"
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/*****************************************************************************
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* Public Types
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*****************************************************************************/
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/* This union allows us to keep free DMA descriptors in in a list */
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union dma_descriptor_u
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{
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sq_entry_t link;
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struct dma_desriptor_s desc;
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};
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/* This structure describes one DMA channel */
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struct dma_channel_s
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{
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uint8_t chan; /* DMA channel number (0-EFM_DMA_NCHANNELS) */
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bool inuse; /* TRUE: The DMA channel is in use */
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struct dms_descriptor_s *desc; /* DMA descriptor assigned to the channel */
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dma_callback_t callback; /* Callback invoked when the DMA completes */
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void *arg; /* Argument passed to callback function */
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};
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/* This structure describes the state of the DMA controller */
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struct dma_controller_s
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{
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sem_t exclsem; /* Protects channel table */
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sem_t chansem; /* Count of free channels */
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sem_t freesem; /* Count of free descriptors */
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sq_queue_t freedesc; /* List of free DMA descriptors */
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};
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/*****************************************************************************
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* Private Data
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*****************************************************************************/
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/* This is the overall state of the DMA controller */
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static struct dma_controller_s g_dmac;
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/* This is the array of all DMA channels */
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static struct dma_channel_s g_dmach[EFM_DMA_NCHANNELS];
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/* This array describes the available channel control data structures.
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* Each structure must be aligned to the size of the DMA descriptor.
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*/
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static union dma_descriptor_u g_descriptors[CONFIG_EFM32_DMA_NDESCR]
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__attribute__((aligned(16)));
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/*****************************************************************************
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* Public Data
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@ -57,49 +110,235 @@
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* Private Functions
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*****************************************************************************/
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/****************************************************************************
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* Name: efm32_alloc_descriptor
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*
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* Description:
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* Allocate one DMA descriptor by removing it from the free list.
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*
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* Returned Value:
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* The allocated DMA descriptor. If no DMA descriptors are available, this
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* function will wait until one is returned to the freelist.
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*
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****************************************************************************/
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static struct dma_descriptor_s *efm32_alloc_descriptor(void)
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{
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struct dma_descriptor_s *desc;
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irqstate_t flags;
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/* Take a count from from the descriptor counting semaphore. We may block
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* if there are no free descriptors. When we get the count, then we can
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* be assured that a DMA descriptor is available in the free list and is
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* reserved for us.
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*/
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flags = irqsave();
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while (sem_wait(&g_dmac.freesem) < 0)
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{
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/* sem_wait should fail only if it is awakened by a a signal */
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DEBUGASSERT(errno == EINTR);
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}
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/* Get our descriptor to the free list. Interrupts mus be disabled here
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* because the free list may also be accessed from the DMA interrupt
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* handler.
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*/
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desc = (struct dma_descriptor_s *)sq_remfirst(&g_dmac.freedesc);
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irqrestore(flags);
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/* And return the descriptor */
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DEBUGASSERT(desc && ((uintptr_t)desc & ~15) == 0);
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return desc;
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}
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/****************************************************************************
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* Name: efm32_free_descriptor
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*
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* Description:
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* Free one DMA descriptor by returning it to the free list.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void efm32_free_descriptor(struct dma_descriptor_s *desc)
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{
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union dma_descriptor_u *udesc = (union dma_descriptor_u *)desc;
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irqstate_t flags;
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/* Return the descriptor to the free list. This may be called from the
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* the DMA completion interrupt handler.
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*/
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flags = irqsave();
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sq_addlast(&udesc->link, &g_dmac.freedesc);
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irqrestore(flags);
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/* Notify any waiters that a new DMA descriptor is available in the free
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* list.
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*/
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sem_post(&g_dmac.freesem);
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}
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/****************************************************************************
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* Name: efm32_dmac_interrupt
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*
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* Description:
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* DMA interrupt handler
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*
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****************************************************************************/
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static int efm32_dmac_interrupt(int irq, void *context)
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{
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#warning Missing logic
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return OK;
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}
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/*****************************************************************************
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* Public Functions
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*****************************************************************************/
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/*****************************************************************************
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/****************************************************************************
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* Name: up_dmainitialize
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*
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* Description:
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* Initialize the DMA subsystem
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void weak_function up_dmainitialize(void)
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{
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int i;
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dmallvdbg("Initialize XDMAC0\n");
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/* Add the pre-allocated DMA descriptors to the free list */
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sq_init(&g_dmac.freedesc);
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sem_init(&g_dmac.freesem, 0, CONFIG_EFM32_DMA_NDESCR);
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for (i = 0; i < CONFIG_EFM32_DMA_NDESCR; i++)
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{
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sq_addlast(&g_descriptors[i].link, &g_dmac.freedesc);
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}
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/* Initialize the channel list */
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sem_init(&g_dmac.exclsem, 0, 1);
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sem_init(&g_dmac.chansem, 0, EFM_DMA_NCHANNELS);
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for (i = 0; i < EFM_DMA_NCHANNELS; i++)
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{
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g_dmach[i].chan = i;
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}
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/* Enable clock to the DMA module */
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#warning Missing logic
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/* Attach DMA interrupt vector */
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(void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt);
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/* Initialize the controller */
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#warning Missing logic
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/* Enable the IRQ at the AIC (still disabled at the DMA controller) */
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up_enable_irq(EFM32_IRQ_DMA);
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}
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/****************************************************************************
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* Name: efm32_dmachannel
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*
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* Description:
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* Allocate a DMA channel. This function gives the caller mutually
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* exclusive access to the DMA channel specified by the 'chan' argument.
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* DMA channels are shared on the EFM32: Devices sharing the same DMA
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* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
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* efm32_dma.h.
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* exclusive access to a DMA channel.
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*
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* If the DMA channel is not available, then efm32_dmachannel() will wait
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* until the holder of the channel relinquishes the channel by calling
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* efm32_dmafree(). WARNING: If you have two devices sharing a DMA
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* channel and the code never releases the channel, the efm32_dmachannel
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* call for the other will hang forever in this function! Don't let your
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* design do that!
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* If no DMA channel is available, then efm32_dmachannel() will wait
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* until the holder of a channel relinquishes the channel by calling
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* efm32_dmafree().
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*
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* Hmm.. I suppose this interface could be extended to make a non-blocking
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* version. Feel free to do that if that is what you need.
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*
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* Input parameter:
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* chan - Identifies the channel resource
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* Input parameters:
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* None
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*
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* Returned Value:
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* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'chan' is invalid, the function will
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* assert if debug is enabled or do something ignorant otherwise).
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* This function ALWAYS returns a non-NULL, void* DMA channel handle.
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*
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* Assumptions:
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* - The caller does not hold he DMA channel.
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* - The caller can wait for the DMA channel to be freed if it is no
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* - The caller can wait for a DMA channel to be freed if it is not
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* available.
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*
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*****************************************************************************/
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****************************************************************************/
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DMA_HANDLE efm32_dmachannel(unsigned int chan)
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DMA_HANDLE efm32_dmachannel(void)
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{
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struct dma_channel_s *dmach;
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unsigned int chndx;
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/* Take a count from from the channel counting semaphore. We may block
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* if there are no free channels. When we get the count, then we can
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* be assured that a channel is available in the channel list and is
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* reserved for us.
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*/
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while (sem_wait(&g_dmac.chansem) < 0)
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{
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/* sem_wait should fail only if it is awakened by a a signal */
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DEBUGASSERT(errno == EINTR);
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}
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/* Get exclusive access to the DMA channel list */
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while (sem_wait(&g_dmac.exclsem) < 0)
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{
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/* sem_wait should fail only if it is awakened by a a signal */
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DEBUGASSERT(errno == EINTR);
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}
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/* Search for an available DMA channel */
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for (chndx = 0, dmach = NULL; chndx < EFM_DMA_NCHANNELS; chndx++)
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{
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struct dma_channel_s *candidate = &g_dmach[chndx];
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if (!candidate->inuse)
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{
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dmach = candidate;
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dmach->inuse = true;
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/* Clear any pending channel interrupts */
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#warning Missing logic
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return NULL;
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/* Disable the channel */
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#warning Missing logic
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break;
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}
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}
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sem_post(&g_dmac.exclsem);
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/* Show the result of the allocation */
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if (dmach)
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{
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dmavdbg("Allocated DMA channel %d\n", dmach->chan);
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}
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else
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{
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dmadbg("ERROR: Failed allocate DMA channel\n");
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}
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return (DMA_HANDLE)dmach;
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}
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/****************************************************************************
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@ -123,7 +362,25 @@ DMA_HANDLE efm32_dmachannel(unsigned int chan)
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void efm32_dmafree(DMA_HANDLE handle)
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{
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struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
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DEBUGASSERT(dmach != NULL && dmach->inuse);
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dmavdbg("DMA channel %d\n", dmach->chan);
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/* Disable the channel */
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#warning Missing logic
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/* Mark the channel no longer in use. Clearing the inuse flag is an atomic
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* operation and so should be safe.
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*/
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dmach->inuse = false;
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/* And increment the count of free channels... possibly waking up a
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* thread that may be waiting for a channel.
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*/
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sem_post(&g_dmac.chansem);
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}
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/****************************************************************************
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@ -125,37 +125,25 @@ extern "C"
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*
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* Description:
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* Allocate a DMA channel. This function gives the caller mutually
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* exclusive access to the DMA channel specified by the 'chan' argument.
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* DMA channels are shared on the EFM32: Devices sharing the same DMA
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* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
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* efm32_dma.h.
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* exclusive access to a DMA channel.
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*
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* If the DMA channel is not available, then efm32_dmachannel() will wait
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* until the holder of the channel relinquishes the channel by calling
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* efm32_dmafree(). WARNING: If you have two devices sharing a DMA
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* channel and the code never releases the channel, the efm32_dmachannel
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* call for the other will hang forever in this function! Don't let your
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* design do that!
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* If no DMA channel is available, then efm32_dmachannel() will wait
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* until the holder of a channel relinquishes the channel by calling
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* efm32_dmafree().
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*
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* Hmm.. I suppose this interface could be extended to make a non-blocking
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* version. Feel free to do that if that is what you need.
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*
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* Input parameter:
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* chan - Identifies the channel resource
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* Input parameters:
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* None
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*
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* Returned Value:
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* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'chan' is invalid, the function will
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* assert if debug is enabled or do something ignorant otherwise).
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* This function ALWAYS returns a non-NULL, void* DMA channel handle.
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*
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* Assumptions:
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* - The caller does not hold he DMA channel.
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* - The caller can wait for the DMA channel to be freed if it is no
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* - The caller can wait for a DMA channel to be freed if it is not
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* available.
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*
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****************************************************************************/
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DMA_HANDLE efm32_dmachannel(unsigned int chan);
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DMA_HANDLE efm32_dmachannel(void);
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/****************************************************************************
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* Name: efm32_dmafree
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@ -136,7 +136,7 @@ struct sam_xdmach_s
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struct chnext_view1_s *lltail; /* DMA link list head */
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};
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/* This structure describes the stae of one DMA controller */
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/* This structure describes the state of one DMA controller */
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struct sam_xdmac_s
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{
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