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arch/arm/src/stm32/stm32_adc.h: add prefix STM32 to low-level ops macros

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This commit is contained in:
raiden00pl 2020-04-25 20:51:44 +02:00 committed by patacongo
parent 1b4e0fddb8
commit f837bfecdb
5 changed files with 44 additions and 44 deletions
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26
arch/arm/src/stm32/stm32_adc.h
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@ -1948,31 +1948,31 @@
/* Low-level ops helpers ************************************************************/
#define ADC_INT_ACK(adc, source) \
#define STM32_ADC_INT_ACK(adc, source) \
(adc)->llops->int_ack(adc, source)
#define ADC_INT_GET(adc) \
#define STM32_ADC_INT_GET(adc) \
(adc)->llops->int_get(adc)
#define ADC_INT_ENABLE(adc, source) \
#define STM32_ADC_INT_ENABLE(adc, source) \
(adc)->llops->int_en(adc, source)
#define ADC_INT_DISABLE(adc, source) \
#define STM32_ADC_INT_DISABLE(adc, source) \
(adc)->llops->int_dis(adc, source)
#define ADC_REGDATA_GET(adc) \
#define STM32_ADC_REGDATA_GET(adc) \
(adc)->llops->val_get(adc)
#define ADC_REGBUF_REGISTER(adc, buffer, len) \
#define STM32_ADC_REGBUF_REGISTER(adc, buffer, len) \
(adc)->llops->regbuf_reg(adc, buffer, len)
#define ADC_REG_STARTCONV(adc, state) \
#define STM32_ADC_REG_STARTCONV(adc, state) \
(adc)->llops->reg_startconv(adc, state)
#define ADC_OFFSET_SET(adc, ch, i, o) \
#define STM32_ADC_OFFSET_SET(adc, ch, i, o) \
(adc)->llops->offset_set(adc, ch, i, o)
#define ADC_INJ_STARTCONV(adc, state) \
#define STM32_ADC_INJ_STARTCONV(adc, state) \
(adc)->llops->inj_startconv(adc, state)
#define ADC_INJDATA_GET(adc, chan) \
#define STM32_ADC_INJDATA_GET(adc, chan) \
(adc)->llops->inj_get(adc, chan)
#define ADC_SAMPLETIME_SET(adc, time_samples) \
#define STM32_ADC_SAMPLETIME_SET(adc, time_samples) \
(adc)->llops->stime_set(adc, time_samples)
#define ADC_SAMPLETIME_WRITE(adc) \
#define STM32_ADC_SAMPLETIME_WRITE(adc) \
(adc)->llops->stime_write(adc)
#define ADC_DUMP_REGS(adc) \
#define STM32_ADC_DUMP_REGS(adc) \
(adc)->llops->dump_regs(adc)
/************************************************************************************

14
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
View File

@ -220,7 +220,7 @@ void adc12_handler(void)
/* Get pending ADC interrupts */
pending = ADC_INT_GET(adc);
pending = STM32_ADC_INT_GET(adc);
if (g_highpri.lock == true)
{
@ -238,7 +238,7 @@ void adc12_handler(void)
/* Get regular data */
g_highpri.r_val[g_highpri.current] = ADC_REGDATA_GET(adc);
g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
/* Do some floating point operations */
@ -269,7 +269,7 @@ void adc12_handler(void)
for (i = 0; i < INJ_NCHANNELS; i += 1)
{
g_highpri.j_val[i] = ADC_INJDATA_GET(adc, i);
g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
}
/* Do some floating point operations */
@ -284,7 +284,7 @@ void adc12_handler(void)
irq_out:
/* Clear ADC pending interrupts */
ADC_INT_ACK(adc, pending);
STM32_ADC_INT_ACK(adc, pending);
}
#endif
@ -478,17 +478,17 @@ int highpri_main(int argc, char *argv[])
#ifndef CONFIG_STM32_ADC1_DMA
/* Enable ADC regular conversion interrupts if no DMA */
ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
#else
/* Register ADC buffer for DMA transfer */
ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
/* Enable ADC injected sequence end interrupts */
ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
#endif
#ifdef HIGHPRI_HAVE_TIM1

14
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
View File

@ -235,7 +235,7 @@ void adc12_handler(void)
/* Get pending ADC interrupts */
pending = ADC_INT_GET(adc);
pending = STM32_ADC_INT_GET(adc);
if (g_highpri.lock == true)
{
@ -253,7 +253,7 @@ void adc12_handler(void)
/* Get regular data */
g_highpri.r_val[g_highpri.current] = ADC_REGDATA_GET(adc);
g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
/* Do some floating point operations */
@ -284,7 +284,7 @@ void adc12_handler(void)
for (i = 0; i < INJ_NCHANNELS; i += 1)
{
g_highpri.j_val[i] = ADC_INJDATA_GET(adc, i);
g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
}
/* Do some floating point operations */
@ -299,7 +299,7 @@ void adc12_handler(void)
irq_out:
/* Clear ADC pending interrupts */
ADC_INT_ACK(adc, pending);
STM32_ADC_INT_ACK(adc, pending);
}
#endif
@ -514,17 +514,17 @@ int highpri_main(int argc, char *argv[])
#ifndef CONFIG_STM32_ADC1_DMA
/* Enable ADC regular conversion interrupts if no DMA */
ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
#else
/* Register ADC buffer for DMA transfer */
ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
/* Enable ADC injected sequence end interrupts */
ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
#endif
#ifdef HIGHPRI_HAVE_HRTIM

20
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
View File

@ -407,8 +407,8 @@ static int smps_setup(FAR struct smps_dev_s *dev)
stime.channels_nbr = ADC1_NCHANNELS;
stime.channel = channels;
ADC_SAMPLETIME_SET(adc, &stime);
ADC_SAMPLETIME_WRITE(adc);
STM32_ADC_SAMPLETIME_SET(adc, &stime);
STM32_ADC_SAMPLETIME_WRITE(adc);
/* TODO: create current limit table */
@ -512,7 +512,7 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Enable ADC JEOS interrupts */
ADC_INT_ENABLE(adc, ADC_INT_JEOS);
STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS);
/* Enable ADC12 interrupts */
@ -520,7 +520,7 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Start injected conversion */
ADC_INJ_STARTCONV(adc, true);
STM32_ADC_INJ_STARTCONV(adc, true);
errout:
return ret;
@ -540,11 +540,11 @@ static int smps_stop(FAR struct smps_dev_s *dev)
/* Stop injected conversion */
ADC_INJ_STARTCONV(adc, false);
STM32_ADC_INJ_STARTCONV(adc, false);
/* Disable ADC JEOS interrupts */
ADC_INT_DISABLE(adc, ADC_INT_JEOS);
STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS);
/* Disable ADC12 interrupts */
@ -948,14 +948,14 @@ static void adc12_handler(void)
float out;
uint8_t mode;
pending = ADC_INT_GET(adc);
pending = STM32_ADC_INT_GET(adc);
if (pending & ADC_INT_JEOC && priv->running == true)
{
/* Get raw ADC values */
priv->v_out_raw = ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL);
priv->v_in_raw = ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL);
priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL);
priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL);
/* Convert raw values to real values */
@ -1010,7 +1010,7 @@ static void adc12_handler(void)
/* Clear pending */
ADC_INT_ACK(adc, pending);
STM32_ADC_INT_ACK(adc, pending);
}
/****************************************************************************

14
boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
View File

@ -205,7 +205,7 @@ void adc_handler(void)
/* Get pending ADC1 interrupts */
pending = ADC_INT_GET(adc);
pending = STM32_ADC_INT_GET(adc);
if (g_highpri.lock == true)
{
@ -223,7 +223,7 @@ void adc_handler(void)
/* Get regular data */
g_highpri.r_val[g_highpri.current] = ADC_REGDATA_GET(adc);
g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
/* Do some floating point operations */
@ -254,7 +254,7 @@ void adc_handler(void)
for (i = 0; i < INJ_NCHANNELS; i += 1)
{
g_highpri.j_val[i] = ADC_INJDATA_GET(adc, i);
g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
}
/* Do some floating point operations */
@ -269,7 +269,7 @@ void adc_handler(void)
irq_out:
/* Clear ADC pending interrupts */
ADC_INT_ACK(adc, pending);
STM32_ADC_INT_ACK(adc, pending);
}
#endif
@ -463,7 +463,7 @@ int highpri_main(int argc, char *argv[])
#ifndef CONFIG_STM32_ADC1_DMA
/* Enable ADC regular conversion interrupts if no DMA */
ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
#else
/* Note: ADC and DMA must be reset after overrun occurs.
* For this example we assume that overrun will not occur.
@ -473,13 +473,13 @@ int highpri_main(int argc, char *argv[])
/* Register ADC buffer for DMA transfer */
ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
/* Enable ADC injected channels end of conversion interrupts */
ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC);
STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC);
#endif
#ifdef HIGHPRI_HAVE_TIM1