continue capture
This commit is contained in:
pnb
parent
2f78c0c1bc
commit
f88e62c8e9
@ -5120,6 +5120,136 @@ config STM32_TIM14_DAC2
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endchoice
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config STM32_TIM1_CAP
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bool "TIM1 Capture
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default n
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depends on STM32_HAVE_TIM1
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---help---
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Reserve timer 1 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM1_CAP
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bool "TIM1 Capture
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default n
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depends on STM32_HAVE_TIM1
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---help---
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Reserve timer 1 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM2_CAP
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bool "TIM2 Capture
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default n
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depends on STM32_HAVE_TIM2
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---help---
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Reserve timer 2 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM3_CAP
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bool "TIM3 Capture
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default n
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depends on STM32_HAVE_TIM3
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---help---
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Reserve timer 3 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM4_CAP
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bool "TIM4 Capture
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default n
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depends on STM32_HAVE_TIM4
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---help---
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Reserve timer 4 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM5_CAP
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bool "TIM5 Capture
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default n
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depends on STM32_HAVE_TIM5
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---help---
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Reserve timer 5 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM8_CAP
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bool "TIM8 Capture
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default n
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depends on STM32_HAVE_TIM8
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---help---
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Reserve timer 8 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM9_CAP
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bool "TIM9 Capture
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default n
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depends on STM32_HAVE_TIM9
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---help---
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Reserve timer 9 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM10_CAP
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bool "TIM10 Capture
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default n
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depends on STM32_HAVE_TIM10
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---help---
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Reserve timer 10 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM11_CAP
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bool "TIM11 Capture
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default n
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depends on STM32_HAVE_TIM11
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---help---
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Reserve timer 11 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM12_CAP
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bool "TIM12 Capture
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default n
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depends on STM32_HAVE_TIM12
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---help---
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Reserve timer 12 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM13_CAP
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bool "TIM13 Capture
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default n
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depends on STM32_HAVE_TIM13
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---help---
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Reserve timer 13 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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config STM32_TIM14_CAP
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bool "TIM14 Capture
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default n
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depends on STM32_HAVE_TIM14
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---help---
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Reserve timer 14 for use by Capture
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Timer devices may be used for different purposes. One special purpose is
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to capture input.
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menu "ADC Configuration"
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depends on STM32_ADC
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692
arch/arm/src/stm32/stm32_capture.c
Normal file
692
arch/arm/src/stm32/stm32_capture.c
Normal file
@ -0,0 +1,692 @@
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/************************************************************************************
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* arm/arm/src/stm32/stm32_capture.c
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*
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* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
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* Author: Bouteville Pierre-Noel <pnb990@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "stm32.h"
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#include "stm32_gpio.h"
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#include "stm32_capture.h"
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/* Configuration ********************************************************************/
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#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \
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defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \
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defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \
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defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN)
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# define HAVE_CH1IN 1
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#endif
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#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \
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defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \
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defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN)
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# define HAVE_CH2IN 1
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#endif
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#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \
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defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN)
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# define HAVE_CH3IN 1
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#endif
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#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \
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defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN)
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# define HAVE_CH4IN 1
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#endif
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#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM1_CAP)
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#define HAVE_ADANCED_TIM 1
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#endif
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/* This module then only compiles if there are enabled timers that are not intended for
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* some other purpose.
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*/
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#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \
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defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || defined(CONFIG_STM32_TIM8_CAP) || \
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defined(CONFIG_STM32_TIM9_CAP) || defined(CONFIG_STM32_TIM10_CAP) || defined(CONFIG_STM32_TIM11_CAP) || \
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defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || defined(CONFIG_STM32_TIM14_CAP)
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/************************************************************************************
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* Private Types
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************************************************************************************/
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struct stm32_cap_channel_s
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{
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uint8_t ch_id;
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uint16_t ccmr;
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uint32_t gpio;
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}
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/* TIM Device Structure */
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struct stm32_cap_priv_s
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{
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const struct stm32_cap_ops_s *ops;
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const uint32_t base; /* TIMn base address */
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const int irq; /* irq vector */
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#define HAVE_ADANCED_TIM 1
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const int irq_of; /* irq timer overflow is deferent in advanced timer */
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#endif
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const stm32_cap_channel_s channels[CAP_NCHANNELS];
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};
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/* Get a 16-bit register value by offset */
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static inline uint16_t stm32_getreg16(FAR struct stm32_cap_priv_s *priv,
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uint8_t offset)
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{
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return getreg16(priv->base + offset);
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}
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/* Put a 16-bit register value by offset */
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static inline void stm32_putreg16(FAR struct stm32_cap_priv_s *priv, uint8_t offset,
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uint16_t value)
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{
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putreg16(value, priv->base + offset);
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}
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/* Modify a 16-bit register value by offset */
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static inline void stm32_modifyreg16(FAR struct stm32_cap_priv_s *priv,
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uint8_t offset, uint16_t clearbits,
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uint16_t setbits)
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{
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modifyreg16(priv->base + offset, clearbits, setbits);
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}
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/* Get a 32-bit register value by offset. This applies only for the STM32 F4
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* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
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*/
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static inline uint32_t stm32_getreg32(FAR struct stm32_cap_priv_s *priv,
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uint8_t offset)
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{
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return getreg32(priv->base + offset);
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}
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/* Put a 32-bit register value by offset. This applies only for the STM32 F4
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* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
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*/
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static inline void stm32_putreg32(FAR struct stm32_cap_priv_s *priv, uint8_t offset,
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uint32_t value)
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{
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putreg32(value, priv->base + offset);
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}
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/************************************************************************************
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* Basic Functions
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************************************************************************************/
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static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src,
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uint32_t prescaler)
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{
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struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
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uint16_t regval = 0;
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if (prescaler == 0)
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{
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//disable Timer
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stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,ATIM_CR1_CEN,0);
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return 0;
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}
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/* We need to decrement value for '1', but only, if we are allowed to
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* not to cause underflow. Check for overflow.
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*/
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if (prescaler > 0)
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prescaler--;
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if (prescaler > 0xffff)
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prescaler = 0xffff;
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switch(clk_src)
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{
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case STM32_CAP_CLK_INT:
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regval = GTIM_SMCR_DISAB;
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break;
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case STM32_CAP_CLK_EXT:
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regval = GTIM_SMCR_EXTCLK1
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break;
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/* TODO: Add other case */
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default:
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return ERROR;
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}
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stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, GTIM_SMCR_SMS_MASK, regval );
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// Set Maximum
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stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, period);
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// Set prescaler
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stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler);
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//reset counter timer
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stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET,0,BTIM_EGR_UG);
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//enable timer
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stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,0,BTIM_CR1_CEN);
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#ifdef HAVE_ADANCED_TIM
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/* Advanced registers require Main Output Enable */
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if ((priv->base == STM32_TIM1_BASE) || (priv->base == STM32_TIM8_BASE))
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{
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stm32_modifyreg16(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
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}
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#endif
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return prescaler;
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}
|
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static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
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{
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struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
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int irq;
|
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#ifdef HAVE_ADANCED_TIM
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int irq_of;
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#endif
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ASSERT(dev);
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irq = priv->irq;
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#ifdef HAVE_ADANCED_TIM
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irq_of = priv->irq_of;
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#endif
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/* Disable interrupt when callback is removed */
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|
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if (!handler)
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{
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up_disable_irq(irq);
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irq_detach(irq);
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#ifdef HAVE_ADANCED_TIM
|
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if (priv->irq_of)
|
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{
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up_disable_irq(irq_of);
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irq_detach(irq_of);
|
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}
|
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#endif
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return OK;
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}
|
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|
||||
/* Otherwise set callback and enable interrupt */
|
||||
|
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irq_attach(irq, handler);
|
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up_enable_irq(irq);
|
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|
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#ifdef HAVE_ADANCED_TIM
|
||||
if (priv->irq_of)
|
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{
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irq_attach(priv->irq_of, handler);
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up_enable_irq(priv->irq_of);
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}
|
||||
#endif
|
||||
|
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#ifdef CONFIG_ARCH_IRQPRIO
|
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/* Set the interrupt priority */
|
||||
|
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up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT);
|
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|
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# ifdef HAVE_ADANCED_TIM
|
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if (priv->irq_of)
|
||||
{
|
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up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT);
|
||||
}
|
||||
# endif
|
||||
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev,
|
||||
stm32_cap_flags_t src, bool on)
|
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{
|
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struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
|
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uint16_t mask;
|
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ASSERT(dev);
|
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|
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if (src & STM32_TIM_FLAG_IRQ_OVERFLOW)
|
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regval |= ATIM_DIER_UIE;
|
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if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1)
|
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regval |= ATIM_DIER_CC1IE;
|
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if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2)
|
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regval |= ATIM_DIER_CC1IE;
|
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if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3)
|
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regval |= ATIM_DIER_CC1IE;
|
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if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4)
|
||||
regval |= ATIM_DIER_CC1IE;
|
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|
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/* Not IRQ on channel overflow */
|
||||
|
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if (on)
|
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stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET,0,mask);
|
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else
|
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stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET,mask,0);
|
||||
|
||||
}
|
||||
|
||||
static void stm32_cap_ackflags(FAR struct stm32_cap_dev_s *dev, int src)
|
||||
{
|
||||
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
|
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uint16_t mask = 0;
|
||||
|
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if (src & STM32_TIM_FLAG_IRQ_OVERFLOW)
|
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regval |= ATIM_SR_UIF;
|
||||
|
||||
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1)
|
||||
regval |= ATIM_SR_CC1IF;
|
||||
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2)
|
||||
regval |= ATIM_SR_CC2IF;
|
||||
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3)
|
||||
regval |= ATIM_SR_CC3IF;
|
||||
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4)
|
||||
regval |= ATIM_SR_CC4IF;
|
||||
|
||||
if (src & STM32_TIM_FLAG_OF_CAPTURE_1)
|
||||
regval |= ATIM_SR_CC1OF;
|
||||
if (src & STM32_TIM_FLAG_OF_CAPTURE_2)
|
||||
regval |= ATIM_SR_CC2OF;
|
||||
if (src & STM32_TIM_FLAG_OF_CAPTURE_3)
|
||||
regval |= ATIM_SR_CC3OF;
|
||||
if (src & STM32_TIM_FLAG_OF_CAPTURE_4)
|
||||
regval |= ATIM_SR_CC4OF;
|
||||
|
||||
stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask);
|
||||
|
||||
}
|
||||
|
||||
static stm32_cap_flags_t stm32_cap_getint(FAR struct stm32_cap_dev_s *dev)
|
||||
{
|
||||
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
|
||||
uint16_t regval = 0;
|
||||
stm32_cap_flags_t src = 0;
|
||||
|
||||
regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET);
|
||||
|
||||
if (regval & ATIM_SR_UIF)
|
||||
src |= STM32_TIM_FLAG_IRQ_OVERFLOW;
|
||||
|
||||
if (regval & ATIM_SR_CC1IF)
|
||||
src |= STM32_TIM_FLAG_IRQ_CAPTURE_1;
|
||||
if (regval & ATIM_SR_CC2IF)
|
||||
src |= STM32_TIM_FLAG_IRQ_CAPTURE_2;
|
||||
if (regval & ATIM_SR_CC3IF)
|
||||
src |= STM32_TIM_FLAG_IRQ_CAPTURE_3;
|
||||
if (regval & ATIM_SR_CC4IF)
|
||||
src |= STM32_TIM_FLAG_IRQ_CAPTURE_4;
|
||||
|
||||
if (regval & ATIM_SR_CC1OF)
|
||||
src |= STM32_TIM_FLAG_OF_CAPTURE_1;
|
||||
if (regval & ATIM_SR_CC2OF)
|
||||
src |= STM32_TIM_FLAG_OF_CAPTURE_2;
|
||||
if (regval & ATIM_SR_CC3OF)
|
||||
src |= STM32_TIM_FLAG_OF_CAPTURE_3;
|
||||
if (regval & ATIM_SR_CC4OF)
|
||||
src |= STM32_TIM_FLAG_OF_CAPTURE_4;
|
||||
|
||||
return src;
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* General Functions
|
||||
************************************************************************************/
|
||||
|
||||
static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel,
|
||||
stm32_cap_ch_cfg_t edge)
|
||||
{
|
||||
int i;
|
||||
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
|
||||
uint32_t gpio = 0;
|
||||
uint16_t mask;
|
||||
uint16_t regval;
|
||||
|
||||
ASSERT(dev);
|
||||
|
||||
i = CAP_NCHANNELS;
|
||||
while(i--)
|
||||
{
|
||||
if ( priv->channels[i].ch_id == channel )
|
||||
{
|
||||
gpio = priv->channels[i].gpio;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ( gpio == 0 )
|
||||
return ERROR;
|
||||
|
||||
/* change to zero base index */
|
||||
channel--;
|
||||
|
||||
|
||||
/* Set ccer */
|
||||
switch (cfg & STM32_CAP_EDGE_MASK)
|
||||
{
|
||||
case STM32_CAP_EDGE_DISABLED:
|
||||
regval = 0;
|
||||
break;
|
||||
case STM32_CAP_EDGE_RISING:
|
||||
regval = GTIM_CCER_CC1E;
|
||||
break;
|
||||
case STM32_CAP_EDGE_FALLING:
|
||||
regval = GTIM_CCER_CC1E | GTIM_CCER_CC1P;
|
||||
break;
|
||||
case STM32_CAP_EDGE_BOTH:
|
||||
regval = GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP;
|
||||
break;
|
||||
default:
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP)
|
||||
mask <<= (channel << 2);
|
||||
regval <<= (channel << 2);
|
||||
stm32_modifyreg16(priv,mask,regval);
|
||||
|
||||
/* Set ccmr */
|
||||
|
||||
ccmr_val = cfg;
|
||||
|
||||
if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 0 )
|
||||
return ERROR; /* configured as output */
|
||||
|
||||
if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 3 )
|
||||
return ERROR; /* Not implemented */
|
||||
|
||||
/* Define its position (shift) and get register offset */
|
||||
|
||||
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK)
|
||||
ccmr_val &= mask
|
||||
|
||||
if (channel & 1)
|
||||
{
|
||||
ccmr_val <<= 8;
|
||||
ccmr_mask <<= 8;
|
||||
}
|
||||
|
||||
if (channel < 2)
|
||||
stm32_modifyreg16(priv,STM32_GTIM_CCMR1_OFFSET,ccmr_mask,ccmr_val);
|
||||
else
|
||||
stm32_modifyreg16(priv,STM32_GTIM_CCMR2_OFFSET,ccmr_mask,ccmr_val);
|
||||
|
||||
/* set GPIO */
|
||||
|
||||
if ( (cfg & STM32_CAP_EDGE_MASK) == STM32_CAP_EDGE_DISABLED)
|
||||
stm32_unconfiggpio(gpio);
|
||||
else
|
||||
stm32_configgpio(gpio);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static int stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel)
|
||||
{
|
||||
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
|
||||
ASSERT(dev);
|
||||
|
||||
switch (channel)
|
||||
{
|
||||
#ifdef HAVE_CH1IN
|
||||
case 1:
|
||||
return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
|
||||
#endif
|
||||
#ifdef HAVE_CH1IN
|
||||
case 2:
|
||||
return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
|
||||
#endif
|
||||
#ifdef HAVE_CH1IN
|
||||
case 3:
|
||||
return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
|
||||
#endif
|
||||
#ifdef HAVE_CH1IN
|
||||
case 4:
|
||||
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Advanced Functions
|
||||
************************************************************************************/
|
||||
|
||||
/* TODO: Advanced functions for the STM32_ATIM */
|
||||
|
||||
/************************************************************************************
|
||||
* Device Structures, Instantiation
|
||||
************************************************************************************/
|
||||
|
||||
struct stm32_cap_ops_s stm32_cap_ops =
|
||||
{
|
||||
.setclock = &stm32_cap_setclock,
|
||||
.setchannel = &stm32_cap_setchannel,
|
||||
.getcapture = &stm32_cap_getcapture,
|
||||
.setisr = &stm32_cap_setisr,
|
||||
.enableint = &stm32_cap_enableint,
|
||||
.ackflags = &stm32_cap_ackflags,
|
||||
.getflags = &stm32_cap_getflags
|
||||
};
|
||||
|
||||
#ifdef CONFIG_STM32_TIM2_CAP
|
||||
const struct stm32_cap_priv_s stm32_tim2_priv =
|
||||
{
|
||||
.ops = &stm32_cap_ops,
|
||||
.base = STM32_TIM2_BASE,
|
||||
.irg = STM32_IRQ_TIM2,
|
||||
#define HAVE_ADANCED_TIM 1
|
||||
.irg_of = -1,
|
||||
#endif
|
||||
.gpio_clk = GPIO_TIM2_CLKIN;
|
||||
.channels = {
|
||||
#if defined(GPIO_TIM2_CH1IN)
|
||||
.gpio = GPIO_TIM2_CH1IN;
|
||||
#endif
|
||||
#if defined(GPIO_TIM2_CH2IN)
|
||||
.gpio = GPIO_TIM2_CH2IN;
|
||||
.ccmr = ( GPIO_TIM2_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
|
||||
( GPIO_TIM2_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
|
||||
#endif
|
||||
#if defined(GPIO_TIM2_CH3IN)
|
||||
.gpio = GPIO_TIM2_CH3IN;
|
||||
.ccmr = ( GPIO_TIM2_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
|
||||
( GPIO_TIM2_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
|
||||
#endif
|
||||
#if defined(GPIO_TIM2_CH4IN)
|
||||
.gpio = GPIO_TIM2_CH4IN;
|
||||
.ccmr = ( GPIO_TIM2_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
|
||||
( GPIO_TIM2_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
|
||||
#endif
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function - Initialization
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct stm32_cap_dev_s *stm32_cap_init(int timer)
|
||||
{
|
||||
struct stm32_cap_priv_s *priv = NULL;
|
||||
|
||||
/* Get structure and enable power */
|
||||
|
||||
switch (timer)
|
||||
{
|
||||
#ifdef CONFIG_STM32_TIM1_CAP
|
||||
case 1:
|
||||
priv = &stm32_tim1_priv;
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM2_CAP
|
||||
case 2:
|
||||
priv = &stm32_tim2_priv;
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM3_CAP
|
||||
case 3:
|
||||
priv = &stm32_tim3_priv;
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM4_CAP
|
||||
case 4:
|
||||
priv = &stm32_tim4_priv;
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM5_CAP
|
||||
case 5:
|
||||
priv = &stm32_tim5_priv;
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
|
||||
break;
|
||||
#endif
|
||||
/* TIM6 and TIM7 cannot be used in capture */
|
||||
#ifdef CONFIG_STM32_TIM8_CAP
|
||||
case 8:
|
||||
priv = &stm32_tim8_priv;
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM9_CAP
|
||||
case 9:
|
||||
priv = &stm32_tim9_priv;
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (priv->gpio_clk)
|
||||
stm32_configgpio(priv->gpio_clk)
|
||||
|
||||
// disable timer while is not configured
|
||||
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
|
||||
|
||||
return (struct stm32_cap_dev_s *)priv;
|
||||
}
|
||||
|
||||
|
||||
int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev)
|
||||
{
|
||||
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
|
||||
ASSERT(dev);
|
||||
|
||||
// disable timer while is not configured
|
||||
stm32_modifyreg16(dev, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
|
||||
|
||||
if (priv->gpio_clk)
|
||||
stm32_unconfiggpio(priv->gpio_clk)
|
||||
|
||||
switch (priv->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32_TIM2_CAP
|
||||
case STM32_TIM2_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM3_CAP
|
||||
case STM32_TIM3_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM4_CAP
|
||||
case STM32_TIM4_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM5_CAP
|
||||
case STM32_TIM5_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM1_CAP
|
||||
case STM32_TIM1_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM8_CAP
|
||||
case STM32_TIM8_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */
|
||||
779
arch/arm/src/stm32/stm32_capture.h
Normal file
779
arch/arm/src/stm32/stm32_capture.h
Normal file
@ -0,0 +1,779 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_capture.h
|
||||
*
|
||||
* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
|
||||
* Author: Bouteville Pierre-Noel <pnb990@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
|
||||
#include "chip.h"
|
||||
#include <arch/board/board.h>
|
||||
#include "chip/stm32_tim.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32_TIM1_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM1_CH1OUT
|
||||
# define CAP_TIM1_CH1CFG GPIO_TIM1_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM1_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM1_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM1_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM1_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM1_CH2OUT
|
||||
# define CAP_TIM1_CH2CFG GPIO_TIM1_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM1_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM1_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM1_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM1_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM1_CH3OUT
|
||||
# define CAP_TIM1_CH3CFG GPIO_TIM1_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM1_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM1_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM1_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM1_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM1_CH4OUT
|
||||
# define CAP_TIM1_CH4CFG GPIO_TIM1_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM1_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM1_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM1_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM1_NCHANNELS (CAP_TIM1_CHANNEL1 + CAP_TIM1_CHANNEL2 + \
|
||||
CAP_TIM1_CHANNEL3 + CAP_TIM1_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM2_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM2_CH1OUT
|
||||
# define CAP_TIM2_CH1CFG GPIO_TIM2_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM2_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM2_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM2_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM2_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM2_CH2OUT
|
||||
# define CAP_TIM2_CH2CFG GPIO_TIM2_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM2_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM2_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM2_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM2_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM2_CH3OUT
|
||||
# define CAP_TIM2_CH3CFG GPIO_TIM2_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM2_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM2_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM2_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM2_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM2_CH4OUT
|
||||
# define CAP_TIM2_CH4CFG GPIO_TIM2_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM2_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM2_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM2_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM2_NCHANNELS (CAP_TIM2_CHANNEL1 + CAP_TIM2_CHANNEL2 + \
|
||||
CAP_TIM2_CHANNEL3 + CAP_TIM2_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM3_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM3_CH1OUT
|
||||
# define CAP_TIM3_CH1CFG GPIO_TIM3_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM3_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM3_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM3_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM3_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM3_CH2OUT
|
||||
# define CAP_TIM3_CH2CFG GPIO_TIM3_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM3_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM3_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM3_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM3_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM3_CH3OUT
|
||||
# define CAP_TIM3_CH3CFG GPIO_TIM3_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM3_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM3_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM3_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM3_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM3_CH4OUT
|
||||
# define CAP_TIM3_CH4CFG GPIO_TIM3_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM3_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM3_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM3_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM3_NCHANNELS (CAP_TIM3_CHANNEL1 + CAP_TIM3_CHANNEL2 + \
|
||||
CAP_TIM3_CHANNEL3 + CAP_TIM3_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM4_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM4_CH1OUT
|
||||
# define CAP_TIM4_CH1CFG GPIO_TIM4_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM4_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM4_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM4_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM4_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM4_CH2OUT
|
||||
# define CAP_TIM4_CH2CFG GPIO_TIM4_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM4_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM4_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM4_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM4_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM4_CH3OUT
|
||||
# define CAP_TIM4_CH3CFG GPIO_TIM4_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM4_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM4_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM4_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM4_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM4_CH4OUT
|
||||
# define CAP_TIM4_CH4CFG GPIO_TIM4_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM4_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM4_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM4_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM4_NCHANNELS (CAP_TIM4_CHANNEL1 + CAP_TIM4_CHANNEL2 + \
|
||||
CAP_TIM4_CHANNEL3 + CAP_TIM4_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM5_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM5_CH1OUT
|
||||
# define CAP_TIM5_CH1CFG GPIO_TIM5_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM5_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM5_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM5_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM5_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM5_CH2OUT
|
||||
# define CAP_TIM5_CH2CFG GPIO_TIM5_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM5_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM5_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM5_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM5_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM5_CH3OUT
|
||||
# define CAP_TIM5_CH3CFG GPIO_TIM5_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM5_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM5_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM5_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM5_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM5_CH4OUT
|
||||
# define CAP_TIM5_CH4CFG GPIO_TIM5_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM5_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM5_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM5_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM5_NCHANNELS (CAP_TIM5_CHANNEL1 + CAP_TIM5_CHANNEL2 + \
|
||||
CAP_TIM5_CHANNEL3 + CAP_TIM5_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM8_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM8_CH1OUT
|
||||
# define CAP_TIM8_CH1CFG GPIO_TIM8_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM8_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM8_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM8_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM8_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM8_CH2OUT
|
||||
# define CAP_TIM8_CH2CFG GPIO_TIM8_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM8_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM8_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM8_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM8_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM8_CH3OUT
|
||||
# define CAP_TIM8_CH3CFG GPIO_TIM8_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM8_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM8_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM8_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM8_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM8_CH4OUT
|
||||
# define CAP_TIM8_CH4CFG GPIO_TIM8_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM8_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM8_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM8_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM8_NCHANNELS (CAP_TIM8_CHANNEL1 + CAP_TIM8_CHANNEL2 + \
|
||||
CAP_TIM8_CHANNEL3 + CAP_TIM8_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM9_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM9_CH1OUT
|
||||
# define CAP_TIM9_CH1CFG GPIO_TIM9_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM9_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM9_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM9_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM9_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM9_CH2OUT
|
||||
# define CAP_TIM9_CH2CFG GPIO_TIM9_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM9_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM9_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM9_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM9_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM9_CH3OUT
|
||||
# define CAP_TIM9_CH3CFG GPIO_TIM9_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM9_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM9_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM9_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM9_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM9_CH4OUT
|
||||
# define CAP_TIM9_CH4CFG GPIO_TIM9_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM9_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM9_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM9_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM9_NCHANNELS (CAP_TIM9_CHANNEL1 + CAP_TIM9_CHANNEL2 + \
|
||||
CAP_TIM9_CHANNEL3 + CAP_TIM9_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM10_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM10_CH1OUT
|
||||
# define CAP_TIM10_CH1CFG GPIO_TIM10_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM10_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM10_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM10_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM10_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM10_CH2OUT
|
||||
# define CAP_TIM10_CH2CFG GPIO_TIM10_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM10_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM10_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM10_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM10_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM10_CH3OUT
|
||||
# define CAP_TIM10_CH3CFG GPIO_TIM10_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM10_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM10_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM10_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM10_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM10_CH4OUT
|
||||
# define CAP_TIM10_CH4CFG GPIO_TIM10_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM10_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM10_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM10_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM10_NCHANNELS (CAP_TIM10_CHANNEL1 + CAP_TIM10_CHANNEL2 + \
|
||||
CAP_TIM10_CHANNEL3 + CAP_TIM10_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM11_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM11_CH1OUT
|
||||
# define CAP_TIM11_CH1CFG GPIO_TIM11_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM11_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM11_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM11_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM11_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM11_CH2OUT
|
||||
# define CAP_TIM11_CH2CFG GPIO_TIM11_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM11_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM11_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM11_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM11_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM11_CH3OUT
|
||||
# define CAP_TIM11_CH3CFG GPIO_TIM11_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM11_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM11_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM11_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM11_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM11_CH4OUT
|
||||
# define CAP_TIM11_CH4CFG GPIO_TIM11_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM11_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM11_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM11_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM11_NCHANNELS (CAP_TIM11_CHANNEL1 + CAP_TIM11_CHANNEL2 + \
|
||||
CAP_TIM11_CHANNEL3 + CAP_TIM11_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM12_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM12_CH1OUT
|
||||
# define CAP_TIM12_CH1CFG GPIO_TIM12_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM12_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM12_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM12_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM12_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM12_CH2OUT
|
||||
# define CAP_TIM12_CH2CFG GPIO_TIM12_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM12_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM12_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM12_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM12_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM12_CH3OUT
|
||||
# define CAP_TIM12_CH3CFG GPIO_TIM12_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM12_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM12_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM12_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM12_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM12_CH4OUT
|
||||
# define CAP_TIM12_CH4CFG GPIO_TIM12_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM12_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM12_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM12_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM12_NCHANNELS (CAP_TIM12_CHANNEL1 + CAP_TIM12_CHANNEL2 + \
|
||||
CAP_TIM12_CHANNEL3 + CAP_TIM12_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM13_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM13_CH1OUT
|
||||
# define CAP_TIM13_CH1CFG GPIO_TIM13_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM13_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM13_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM13_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM13_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM13_CH2OUT
|
||||
# define CAP_TIM13_CH2CFG GPIO_TIM13_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM13_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM13_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM13_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM13_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM13_CH3OUT
|
||||
# define CAP_TIM13_CH3CFG GPIO_TIM13_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM13_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM13_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM13_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM13_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM13_CH4OUT
|
||||
# define CAP_TIM13_CH4CFG GPIO_TIM13_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM13_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM13_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM13_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM13_NCHANNELS (CAP_TIM13_CHANNEL1 + CAP_TIM13_CHANNEL2 + \
|
||||
CAP_TIM13_CHANNEL3 + CAP_TIM13_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM14_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM14_CH1OUT
|
||||
# define CAP_TIM14_CH1CFG GPIO_TIM14_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM14_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM14_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM14_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM14_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM14_CH2OUT
|
||||
# define CAP_TIM14_CH2CFG GPIO_TIM14_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM14_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM14_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM14_CHANNEL2 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM14_CHANNEL3
|
||||
# ifdef CONFIG_STM32_TIM14_CH3OUT
|
||||
# define CAP_TIM14_CH3CFG GPIO_TIM14_CH3OUT
|
||||
# else
|
||||
# define CAP_TIM14_CH3CFG 0
|
||||
# endif
|
||||
# define CAP_TIM14_CHANNEL3 1
|
||||
#else
|
||||
# define CAP_TIM14_CHANNEL3 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM14_CHANNEL4
|
||||
# ifdef CONFIG_STM32_TIM14_CH4OUT
|
||||
# define CAP_TIM14_CH4CFG GPIO_TIM14_CH4OUT
|
||||
# else
|
||||
# define CAP_TIM14_CH4CFG 0
|
||||
# endif
|
||||
# define CAP_TIM14_CHANNEL4 1
|
||||
#else
|
||||
# define CAP_TIM14_CHANNEL4 0
|
||||
#endif
|
||||
#define CAP_TIM14_NCHANNELS (CAP_TIM14_CHANNEL1 + CAP_TIM14_CHANNEL2 + \
|
||||
CAP_TIM14_CHANNEL3 + CAP_TIM14_CHANNEL4)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM15_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM15_CH1OUT
|
||||
# define CAP_TIM15_CH1CFG GPIO_TIM15_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM15_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM15_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM15_CHANNEL1 0
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM15_CHANNEL2
|
||||
# ifdef CONFIG_STM32_TIM15_CH2OUT
|
||||
# define CAP_TIM15_CH2CFG GPIO_TIM15_CH2OUT
|
||||
# else
|
||||
# define CAP_TIM15_CH2CFG 0
|
||||
# endif
|
||||
# define CAP_TIM15_CHANNEL2 1
|
||||
#else
|
||||
# define CAP_TIM15_CHANNEL2 0
|
||||
#endif
|
||||
#define CAP_TIM15_NCHANNELS (CAP_TIM15_CHANNEL1 + CAP_TIM15_CHANNEL2)
|
||||
|
||||
#ifdef CONFIG_STM32_TIM16_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM16_CH1OUT
|
||||
# define CAP_TIM16_CH1CFG GPIO_TIM16_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM16_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM16_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM16_CHANNEL1 0
|
||||
#endif
|
||||
#define CAP_TIM16_NCHANNELS CAP_TIM16_CHANNEL1
|
||||
|
||||
#ifdef CONFIG_STM32_TIM17_CHANNEL1
|
||||
# ifdef CONFIG_STM32_TIM17_CH1OUT
|
||||
# define CAP_TIM17_CH1CFG GPIO_TIM17_CH1OUT
|
||||
# else
|
||||
# define CAP_TIM17_CH1CFG 0
|
||||
# endif
|
||||
# define CAP_TIM17_CHANNEL1 1
|
||||
#else
|
||||
# define CAP_TIM17_CHANNEL1 0
|
||||
#endif
|
||||
#define CAP_TIM17_NCHANNELS CAP_TIM17_CHANNEL1
|
||||
|
||||
#define CAP_MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
|
||||
#define CAP_NCHANNELS CAP_MAX(CAP_TIM1_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM2_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM3_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM4_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM5_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM8_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM9_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM10_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM11_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM12_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM13_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM14_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM15_NCHANNELS, \
|
||||
CAP_MAX(CAP_TIM16_NCHANNELS, \
|
||||
CAP_TIM17_NCHANNELS))))))))))))))
|
||||
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helpers **************************************************************************/
|
||||
|
||||
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
|
||||
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
|
||||
#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
|
||||
#define STM32_TIM_ENABLEINT(d,s,on) ((d)->ops->enableint(d,s,on))
|
||||
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
#define STM32_TIM_GETINT(d) ((d)->ops->getint(d))
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Capture Device Structure */
|
||||
|
||||
struct stm32_cap_dev_s
|
||||
{
|
||||
struct stm32_cap_ops_s *ops;
|
||||
};
|
||||
|
||||
/* Capture input EDGE sources */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
|
||||
/* Mapped */
|
||||
STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK),
|
||||
STM32_CAP_MAPPED_TI1 = (1<<GTIM_CCMR1_CC1S_SHIFT),
|
||||
STM32_CAP_MAPPED_TI2 = (2<<GTIM_CCMR1_CC1S_SHIFT),
|
||||
/*TODO STM32_CAP_MAPPED_TRC = (3<<GTIM_CCMR1_CC1S_SHIFT),*/
|
||||
|
||||
/* Event prescaler */
|
||||
STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK),
|
||||
STM32_CAP_INPSC_NO = (0<<GTIM_CCMR1_IC1PSC_SHIFT),
|
||||
STM32_CAP_INPSC_2EVENTS = (1<<GTIM_CCMR1_IC1PSC_SHIFT),
|
||||
STM32_CAP_INPSC_4EVENTS = (2<<GTIM_CCMR1_IC1PSC_SHIFT),
|
||||
STM32_CAP_INPSC_8EVENTS = (3<<GTIM_CCMR1_IC1PSC_SHIFT),
|
||||
|
||||
/* Event prescaler */
|
||||
STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK),
|
||||
STM32_CAP_FILTER_NO = (0<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
/* internal clock with N time to confirm event */
|
||||
STM32_CAP_FILTER_INT_N2 = (1<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_INT_N4 = (2<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_INT_N8 = (3<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
/* DTS clock div by D with N time to confirm event */
|
||||
STM32_CAP_FILTER_DTS_D2_N6 = (4<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D2_N8 = (5<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D4_N6 = (6<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D4_N8 = (7<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D8_N6 = (8<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D8_N8 = (9<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D16_N5 = (10<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D16_N6 = (11<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D16_N8 = (12<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D32_N5 = (13<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D32_N6 = (14<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
STM32_CAP_FILTER_DTS_D32_N8 = (15<<GTIM_CCMR1_IC1F_SHIFT),
|
||||
|
||||
/* EDGE */
|
||||
STM32_CAP_EDGE_MASK = (3<<8),
|
||||
STM32_CAP_EDGE_DISABLED = (0<<8),
|
||||
STM32_CAP_EDGE_RISING = (1<<8),
|
||||
STM32_CAP_EDGE_FALLING = (2<<8),
|
||||
STM32_CAP_EDGE_BOTH = (3<<8),
|
||||
|
||||
} stm32_cap_ch_cfg_t;
|
||||
|
||||
/* TIM clock sources */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
|
||||
STM32_CAP_CLK_INT= 0,
|
||||
STM32_CAP_CLK_EXT,
|
||||
|
||||
/* TODO: Add other clock */
|
||||
|
||||
} stm32_cap_clk_t;
|
||||
|
||||
/* TIM Sources */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/* One of the following */
|
||||
|
||||
STM32_CAP_FLAG_IRQ_TIMER = (1<< 0),
|
||||
|
||||
STM32_CAP_FLAG_IRQ_CH_1 = (1<< 1),
|
||||
STM32_CAP_FLAG_IRQ_CH_2 = (1<< 2),
|
||||
STM32_CAP_FLAG_IRQ_CH_3 = (1<< 3),
|
||||
STM32_CAP_FLAG_IRQ_CH_4 = (1<< 4),
|
||||
|
||||
STM32_CAP_FLAG_OF_CH_1 = (1<< 9),
|
||||
STM32_CAP_FLAG_OF_CH_2 = (1<<10),
|
||||
STM32_CAP_FLAG_OF_CH_3 = (1<<11),
|
||||
STM32_CAP_FLAG_OF_CH_4 = (1<<12)
|
||||
|
||||
} stm32_cap_flags_t;
|
||||
|
||||
|
||||
/* TIM Operations */
|
||||
|
||||
struct stm32_cap_ops_s
|
||||
{
|
||||
int (*setclock)(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src,
|
||||
uint32_t prescaler);
|
||||
int (*setchannel)(FAR struct stm32_cap_dev_s *dev, uint8_t channel);
|
||||
int (*setisr)(FAR struct stm32_tim_dev_s *dev,xcpt_t handler);
|
||||
void (*enableint)(FAR struct stm32_tim_dev_s *dev, stm32_cap_flags_t src, bool on );
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/* Power-up timer and get its structure */
|
||||
|
||||
FAR struct stm32_cap_dev_s *stm32_cap_init(int timer);
|
||||
|
||||
/* Power-down timer, mark it as unused */
|
||||
|
||||
int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev);
|
||||
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */
|
||||
Loading…
Reference in New Issue
Block a user