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FIxed STM32F& DMA stm32_dmacapable

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This commit is contained in:
David Sidrane 2016-07-07 15:49:21 -10:00
parent c16500dfdb
commit f8d3a872ee
2 changed files with 12 additions and 7 deletions
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17
arch/arm/src/stm32f7/stm32_dma.c
View File

@ -609,7 +609,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
paddr, maddr, ntransfers, scr);
#ifdef CONFIG_STM32_DMACAPABLE
#ifdef CONFIG_STM32F7_DMACAPABLE
DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr));
#endif
@ -865,7 +865,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
*
****************************************************************************/
#ifdef CONFIG_STM32_DMACAPABLE
#ifdef CONFIG_STM32F7_DMACAPABLE
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
{
uint32_t transfer_size, burst_length;
@ -965,17 +965,22 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
case STM32_FSMC_BANK3:
case STM32_FSMC_BANK4:
case STM32_SRAM_BASE:
/* All RAM is supported */
break;
case STM32_CODE_BASE:
/* Everything except the CCM ram is supported */
if (maddr >= STM32_CCMRAM_BASE &&
(maddr - STM32_CCMRAM_BASE) < 65536)
/* Everything except the ITCM ram is supported per the manual
* The ITCM bus is not accessible on AHBS. So the DMA data transfer
* to/from ITCM RAM is not supported.
*/
if (maddr >= STM32_INSTRAM_BASE &&
(maddr - STM32_INSTRAM_BASE) < 0x3fff)
{
dmainfo("stm32_dmacapable: transfer targets CCMRAM\n");
dmainfo("stm32_dmacapable: transfer targets ITCM RAM\n");
return false;
}
break;

2
arch/arm/src/stm32f7/stm32_dma.h
View File

@ -246,7 +246,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
*
****************************************************************************/
#ifdef CONFIG_STM32_DMACAPABLE
#ifdef CONFIG_STM32F7_DMACAPABLE
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
#else
# define stm32_dmacapable(maddr, count, ccr) (true)