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riscv: Dump trap val in exception handler

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-08-30 03:39:53 +00:00 committed by Xiang Xiao
parent a0ee5d3747
commit f93964ad3c
2 changed files with 5 additions and 9 deletions
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2
arch/risc-v/include/mode.h
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@ -41,6 +41,7 @@
# define CSR_EPC sepc /* Exception program counter */
# define CSR_IE sie /* Interrupt enable register */
# define CSR_CAUSE scause /* Interrupt cause register */
# define CSR_TVAL stval /* Trap value register */
/* In status register */
@ -74,6 +75,7 @@
# define CSR_EPC mepc /* Exception program counter */
# define CSR_IE mie /* Interrupt enable register */
# define CSR_CAUSE mcause /* Interrupt cause register */
# define CSR_TVAL mtval /* Trap value register */
/* In status register */

12
arch/risc-v/src/common/riscv_exception.c
View File

@ -73,15 +73,9 @@ int riscv_exception(int mcause, void *regs, void *args)
{
uintptr_t cause = mcause & RISCV_IRQ_MASK;
if (mcause > RISCV_MAX_EXCEPTION)
{
_alert("EXCEPTION: Unknown. MCAUSE: %" PRIxREG "\n", cause);
}
else
{
_alert("EXCEPTION: %s. MCAUSE: %" PRIxREG "\n",
g_reasons_str[cause], cause);
}
_alert("EXCEPTION: %s. MCAUSE: %" PRIxREG ", MTVAL: %" PRIxREG "\n",
mcause > RISCV_MAX_EXCEPTION ? "Unknown" : g_reasons_str[cause],
cause, READ_CSR(CSR_TVAL));
_alert("PANIC!!! Exception = %" PRIxREG "\n", cause);
up_irq_save();