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risc-v/toolchain: add "V" Standard Extension into command line

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"V" Standard Extension for Vector Operations

Signed-off-by: chao an <anchao@lixiang.com>
This commit is contained in:
chao an 2024-01-16 08:33:53 +08:00 committed by Xiang Xiao
parent 0cb09ce0ab
commit f95bbb2949
2 changed files with 17 additions and 1 deletions
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5
arch/risc-v/Kconfig
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@ -283,6 +283,11 @@ config ARCH_RV_ISA_C
bool
default n
config ARCH_RV_ISA_V
bool
default n
depends on ARCH_FPU
config ARCH_RV_MMIO_BITS
int
# special cases

13
arch/risc-v/src/common/Toolchain.defs
View File

@ -146,7 +146,14 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
endif
endif
# Detect cpu ISA support flags
# Detect cpu ISA support flags:
#
# Naming Convention
# RISC-V defines an exact order that must be used to define the RISC-V ISA subset:
#
# RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N
#
# For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.
ARCHCPUEXTFLAGS = i
@ -174,6 +181,10 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)c
endif
ifeq ($(CONFIG_ARCH_RV_ISA_V),y)
ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)v
endif
GCC_VERSION = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 }
ifeq ($(shell expr $(GCC_VERSION) \>= 12), 1)
ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_zicsr_zifencei