diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index 8938931e00..5956c84252 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -283,6 +283,11 @@ config ARCH_RV_ISA_C
 	bool
 	default n
 
+config ARCH_RV_ISA_V
+	bool
+	default n
+	depends on ARCH_FPU
+
 config ARCH_RV_MMIO_BITS
 	int
 	# special cases
diff --git a/arch/risc-v/src/common/Toolchain.defs b/arch/risc-v/src/common/Toolchain.defs
index 8a2f969c04..391f90b5ad 100644
--- a/arch/risc-v/src/common/Toolchain.defs
+++ b/arch/risc-v/src/common/Toolchain.defs
@@ -146,7 +146,14 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
     endif
   endif
 
-  # Detect cpu ISA support flags
+  # Detect cpu ISA support flags:
+  #
+  # Naming Convention
+  # RISC-V defines an exact order that must be used to define the RISC-V ISA subset:
+  #
+  # RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N
+  #
+  # For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.
 
   ARCHCPUEXTFLAGS = i
 
@@ -174,6 +181,10 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
     ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)c
   endif
 
+  ifeq ($(CONFIG_ARCH_RV_ISA_V),y)
+    ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)v
+  endif
+
   GCC_VERSION = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 }
   ifeq ($(shell expr $(GCC_VERSION) \>= 12), 1)
     ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_zicsr_zifencei