Tiva Ethernet: Add basic clock/power controls for Ethernet and internal PHY
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@ -151,8 +151,8 @@
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/* μDMA Power Control */
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#ifdef TIVA_SYSCON_PCDMA
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# define tiva_udma_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCDMA,SYSCON_PCDMA_R0)
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# define tiva_udma_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCDMA,SYSCON_PCDMA_R0)
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# define tiva_udma_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCDMA,SYSCON_PCDMA_P0)
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# define tiva_udma_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCDMA,SYSCON_PCDMA_P0)
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#else
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# define tiva_udma_enablepwr()
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# define tiva_udma_disablepwr()
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@ -161,8 +161,8 @@
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/* EPI Power Control */
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#ifdef TIVA_SYSCON_PCEPI
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# define tiva_epi_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPI,SYSCON_PCEPI_R0)
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# define tiva_epi_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPI,SYSCON_PCEPI_R0)
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# define tiva_epi_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPI,SYSCON_PCEPI_P0)
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# define tiva_epi_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPI,SYSCON_PCEPI_P0)
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#else
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# define tiva_epi_enablepwr()
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# define tiva_epi_disablepwr()
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@ -171,8 +171,8 @@
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/* Hibernation Power Control */
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#ifdef TIVA_SYSCON_PCHIB
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# define tiva_hib_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCHIB,SYSCON_PCHIB_R0)
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# define tiva_hib_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCHIB,SYSCON_PCHIB_R0)
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# define tiva_hib_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCHIB,SYSCON_PCHIB_P0)
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# define tiva_hib_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCHIB,SYSCON_PCHIB_P0)
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#else
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# define tiva_hib_enablepwr()
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# define tiva_hib_disablepwr()
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@ -261,8 +261,8 @@
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/* USB Power Control */
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#ifdef TIVA_SYSCON_PCUSB
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# define tiva_usb_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCUSB,SYSCON_PCUSB_R0)
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# define tiva_usb_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCUSB,SYSCON_PCUSB_R0)
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# define tiva_usb_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCUSB,SYSCON_PCUSB_P0)
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# define tiva_usb_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCUSB,SYSCON_PCUSB_P0)
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#else
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# define tiva_usb_enablepwr()
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# define tiva_usb_disablepwr()
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@ -271,8 +271,8 @@
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/* Ethernet PHY Power Control */
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#ifdef TIVA_SYSCON_PCEPHY
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# define tiva_ephy_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPHY,SYSCON_PCEPHY_R0)
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# define tiva_ephy_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPHY,SYSCON_PCEPHY_R0)
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# define tiva_ephy_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEPHY,SYSCON_PCEPHY_P0)
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# define tiva_ephy_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEPHY,SYSCON_PCEPHY_P0)
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#else
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# define tiva_ephy_enablepwr()
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# define tiva_ephy_disablepwr()
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@ -313,8 +313,8 @@
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/* ACMP Power Control */
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#ifdef TIVA_SYSCON_PCACMP
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# define tiva_acmp_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCACMP,SYSCON_PCACMP_R0)
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# define tiva_acmp_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCACMP,SYSCON_PCACMP_R0)
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# define tiva_acmp_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCACMP,SYSCON_PCACMP_P0)
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# define tiva_acmp_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCACMP,SYSCON_PCACMP_P0)
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#else
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# define tiva_acmp_enablepwr()
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# define tiva_acmp_disablepwr()
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@ -355,8 +355,8 @@
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/* EEPROM Power Control */
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#ifdef TIVA_SYSCON_PCEEPROM
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# define tiva_eeprom_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEEPROM,SYSCON_PCEEPROM_R0)
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# define tiva_eeprom_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEEPROM,SYSCON_PCEEPROM_R0)
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# define tiva_eeprom_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEEPROM,SYSCON_PCEEPROM_P0)
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# define tiva_eeprom_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEEPROM,SYSCON_PCEEPROM_P0)
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#else
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# define tiva_eeprom_enablepwr()
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# define tiva_eeprom_disablepwr()
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@ -389,8 +389,8 @@
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/* CRC/Crypto Modules RunMode ClockGating Control */
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#ifdef TIVA_SYSCON_PCCCM
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# define tiva_ccm_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCCCM,SYSCON_PCCCM_R0)
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# define tiva_ccm_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCCCM,SYSCON_PCCCM_R0)
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# define tiva_ccm_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCCCM,SYSCON_PCCCM_P0)
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# define tiva_ccm_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCCCM,SYSCON_PCCCM_P0)
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#else
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# define tiva_ccm_enablepwr()
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# define tiva_ccm_disablepwr()
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@ -399,8 +399,8 @@
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/* LCD Controller Power Control */
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#ifdef TIVA_SYSCON_PCLCD
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# define tiva_lcd_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCLCD,SYSCON_PCLCD_R0)
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# define tiva_lcd_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCLCD,SYSCON_PCLCD_R0)
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# define tiva_lcd_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCLCD,SYSCON_PCLCD_P0)
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# define tiva_lcd_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCLCD,SYSCON_PCLCD_P0)
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#else
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# define tiva_lcd_enablepwr()
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# define tiva_lcd_disablepwr()
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@ -409,8 +409,8 @@
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/* 1-Wire Power Control */
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#ifdef TIVA_SYSCON_PCOWIRE
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# define tiva_owire_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCOWIRE,SYSCON_PCOWIRE_R0)
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# define tiva_owire_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCOWIRE,SYSCON_PCOWIRE_R0)
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# define tiva_owire_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCOWIRE,SYSCON_PCOWIRE_P0)
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# define tiva_owire_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCOWIRE,SYSCON_PCOWIRE_P0)
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#else
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# define tiva_owire_enablepwr()
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# define tiva_owire_disablepwr()
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@ -419,8 +419,8 @@
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/* Ethernet MAC Power Control */
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#ifdef TIVA_SYSCON_PCEMAC
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# define tiva_emac_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEMAC,SYSCON_PCEMAC_R0)
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# define tiva_emac_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEMAC,SYSCON_PCEMAC_R0)
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# define tiva_emac_enablepwr() tiva_enablepwr(TIVA_SYSCON_PCEMAC,SYSCON_PCEMAC_P0)
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# define tiva_emac_disablepwr() tiva_disablepwr(TIVA_SYSCON_PCEMAC,SYSCON_PCEMAC_P0)
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#else
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# define tiva_emac_enablepwr()
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# define tiva_emac_disablepwr()
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@ -3369,6 +3369,20 @@ int tiva_ethinitialize(int intf)
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priv->txpoll = wd_create(); /* Create periodic poll timer */
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priv->txtimeout = wd_create(); /* Create TX timeout timer */
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/* Enable power and clocking to the Ethernet MAC
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*
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* - Enable Power: Applies power (only) to the UART peripheral. This is not
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* an essential step since enabling clocking will also apply power. The
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* only significance is that the EMAC state will be retained if the EMAC
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* clocking is subsequently disabled.
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* - Enable Clocking: Applies both power and clocking to the EMAC peripheral,
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* bringing it a fully functional state.
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*/
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tiva_emac_enablepwr(); /* Ethernet MAC Power Control */
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tiva_emac_enableclk(); /* Ethernet MAC Run Mode Clock Gating Control */
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#ifdef CONFIG_TIVA_PHY_INTERNAL
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/* Integrated PHY:
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*
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* "The Ethernet Controller Module and Integrated PHY receive two clock inputs:
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@ -3386,9 +3400,15 @@ int tiva_ethinitialize(int intf)
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* External PHY support is not yet implemented.
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*/
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/* Enable power and clocking to the Integrated PHY */
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tiva_ephy_enablepwr(); /* Ethernet PHY Power Control */
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tiva_ephy_enableclk(); /* Ethernet PHY Run Mode Clock Gating Control */
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#else
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/* Configure GPIO pins to support Ethernet */
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tiva_ethgpioconfig(priv);
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#endif
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/* Attach the IRQ to the driver */
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