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arch/risc-v/src/mpfs/mpfs_ddr.c: Make sure that DDRC is in reset when starting the training

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Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen 2023-08-24 11:07:24 +03:00 committed by Petro Karashchenko
parent 6baeb7217e
commit f9b5918462
1 changed files with 13 additions and 10 deletions
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23
arch/risc-v/src/mpfs/mpfs_ddr.c
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@ -812,6 +812,19 @@ void mpfs_setup_ddr_segments(enum seg_setup_e option)
static void mpfs_init_ddrc(void)
{
/* Turn on DDRC clock */
modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
SYSREG_SUBBLK_CLOCK_CR_DDRC);
/* Remove soft reset */
modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0,
SYSREG_SUBBLK_CLOCK_CR_DDRC);
modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
SYSREG_SUBBLK_CLOCK_CR_DDRC, 0);
putreg32(LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP,
MPFS_DDR_CSR_APB_CFG_MANUAL_ADDRESS_MAP);
putreg32(LIBERO_SETTING_CFG_CHIPADDR_MAP,
@ -3130,16 +3143,6 @@ static int mpfs_set_mode_vs_bits(struct mpfs_ddr_priv_s *priv)
mpfs_setup_ddr_segments(DEFAULT_SEG_SETUP);
/* Turn on DDRC clock */
modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
SYSREG_SUBBLK_CLOCK_CR_DDRC);
/* Remove soft reset */
modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
SYSREG_SUBBLK_CLOCK_CR_DDRC, 0);
/* Set-up DDRC */
mpfs_init_ddrc();