From ecbf20065c7524021cae3a8d6aa756d1896bb052 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Tue, 1 Mar 2016 10:08:38 -0500 Subject: [PATCH] STM32F429I-Disco: Update STM32_RCC_DCKCFGR_PLLSAIDIVR --- configs/stm32f429i-disco/include/board.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/configs/stm32f429i-disco/include/board.h b/configs/stm32f429i-disco/include/board.h index 04f48cf04e..adcd72adde 100644 --- a/configs/stm32f429i-disco/include/board.h +++ b/configs/stm32f429i-disco/include/board.h @@ -312,7 +312,10 @@ #define BOARD_LTDC_PLLSAIN 192 #define BOARD_LTDC_PLLSAIR 4 #define BOARD_LTDC_PLLSAIQ 7 -#define BOARD_LTDC_PLLSAIDIVR RCC_PLLSAIDIVR_DIV8 + +/* Division factor for LCD clock */ + +#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV8 /* Pixel Clock Polarity */ #define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ @@ -369,7 +372,10 @@ #define BOARD_LTDC_PLLSAIN ??? #define BOARD_LTDC_PLLSAIR ??? #define BOARD_LTDC_PLLSAIQ ??? -#define BOARD_LTDC_PLLSAIDIVR ??? + +/* Division factor for LCD clock */ + +#define STM32_RCC_DCKCFGR_PLLSAIDIVR ??? /* Pixel Clock Polarity */ #define BOARD_LTDC_GCR_PCPOL ??? @@ -418,12 +424,6 @@ #define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) -/* Configure division factor for LCD clock */ - -#define STM32_RCC_DCKCFGR_PLLSAIDIVR \ - RCC_DCKCFGR_PLLSAIDIVR(BOARD_LTDC_PLLSAIDIVR) - - #endif /* CONFIG_STM32_LTDC */ /************************************************************************************