diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index 0d0da346c7..3f04a4738a 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -520,7 +520,7 @@ config RISCV_MISALIGNED_HANDLER
 
 config RISCV_PERCPU_SCRATCH
 	bool "Enable Scratch-based Per-CPU storage"
-	default n
+	default y if LIB_SYSCALL
 	---help---
 		In some special chipsets, multiple CPUs may be bundled in one hardware
 		thread cluster, which results in hartid and cpuindex not being exactly
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index 7bcf2d2d72..bbec8a61b2 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -55,6 +55,14 @@
 #  endif
 #endif
 
+/* System calls require the per CPU scratch area */
+
+#ifdef CONFIG_LIB_SYSCALL
+#  ifndef CONFIG_RISCV_PERCPU_SCRATCH
+#    error "CONFIG_RISCV_PERCPU_SCRATCH is needed for handling system calls"
+#  endif
+#endif
+
 /* Provide a default section for the exeception handler. */
 
 #ifndef EXCEPTION_SECTION
diff --git a/arch/risc-v/src/common/riscv_fork.c b/arch/risc-v/src/common/riscv_fork.c
index 6b7705028c..54aeca33b5 100644
--- a/arch/risc-v/src/common/riscv_fork.c
+++ b/arch/risc-v/src/common/riscv_fork.c
@@ -246,9 +246,9 @@ pid_t riscv_fork(const struct fork_s *context)
   fregs[REG_FS11]               = context->fs11; /* Saved register fs11 */
 #endif
 
-#ifdef CONFIG_BUILD_PROTECTED
+#ifdef CONFIG_LIB_SYSCALL
   /* Forked task starts at `dispatch_syscall()`, which requires TP holding
-   * TCB pointer as per e6973c764c, so we please it here to support vfork.
+   * TCB, in this case the child's TCB is needed.
    */
 
   child->cmn.xcp.regs[REG_TP]   = (uintptr_t)child;