sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

stm32l4: clocking fixes (would hang for MSI@48MHz on STM32L476)

Browse Source
This commit is contained in:
Matias Nitsche 2020-06-07 15:11:58 -03:00 committed by Alan Carvalho de Assis
parent 8013f66ecd
commit fa97e216e4
1 changed files with 27 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
View File

@ -723,11 +723,19 @@ static void stm32l4_stdclockconfig(void)
} }
} }
/* Enable MSI and choosing frequency */ /* Choose MSI frequency */
regval = getreg32(STM32L4_RCC_CR); regval = getreg32(STM32L4_RCC_CR);
regval &= ~RCC_CR_MSIRANGE_MASK; regval &= ~RCC_CR_MSIRANGE_MASK;
regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION | RCC_CR_MSIRGSEL); regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSIRGSEL);
putreg32(regval, STM32L4_RCC_CR);
if (!(regval & RCC_CR_MSION))
{
/* Enable MSI */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_MSION;
putreg32(regval, STM32L4_RCC_CR); putreg32(regval, STM32L4_RCC_CR);
/* Wait until the MSI is ready (or until a timeout elapsed) */ /* Wait until the MSI is ready (or until a timeout elapsed) */
@ -743,6 +751,7 @@ static void stm32l4_stdclockconfig(void)
break; break;
} }
} }
}
#elif defined(STM32L4_BOARD_USEHSE) #elif defined(STM32L4_BOARD_USEHSE)
/* Enable External High-Speed Clock (HSE) */ /* Enable External High-Speed Clock (HSE) */
@ -777,17 +786,17 @@ static void stm32l4_stdclockconfig(void)
if (timeout > 0) if (timeout > 0)
{ {
/* Ensure Power control is enabled before modifying it. */
stm32l4_pwr_enableclk(true);
if (STM32L4_SYSCLK_FREQUENCY > 24000000ul) if (STM32L4_SYSCLK_FREQUENCY > 24000000ul)
{ {
/* Select regulator voltage output Scale 1 mode to support system /* Select regulator voltage output Scale 1 mode to support system
* frequencies up to 168 MHz. * frequencies up to 168 MHz.
*/ */
/* TODO: this seems to hang on STM32L476, at least for MSI@48MHz */
#if 0
stm32l4_pwr_enableclk(true);
stm32_pwr_setvos(1); stm32_pwr_setvos(1);
#endif
} }
else else
{ {
@ -795,6 +804,7 @@ static void stm32l4_stdclockconfig(void)
* frequencies below 24 MHz * frequencies below 24 MHz
*/ */
stm32l4_pwr_enableclk(true);
stm32_pwr_setvos(2); stm32_pwr_setvos(2);
} }
@ -828,6 +838,7 @@ static void stm32l4_stdclockconfig(void)
putreg32(regval, STM32L4_RCC_CFGR); putreg32(regval, STM32L4_RCC_CFGR);
#endif #endif
#ifndef STM32L4_BOARD_NOPLL
/* Set the PLL source and main divider */ /* Set the PLL source and main divider */
regval = getreg32(STM32L4_RCC_PLLCFG); regval = getreg32(STM32L4_RCC_PLLCFG);
@ -864,7 +875,6 @@ static void stm32l4_stdclockconfig(void)
regval |= RCC_PLLCFG_PLLSRC_HSE; regval |= RCC_PLLCFG_PLLSRC_HSE;
#endif #endif
#ifndef STM32L4_BOARD_NOPLL
/* Use the main PLL as SYSCLK, so enable it first */ /* Use the main PLL as SYSCLK, so enable it first */
putreg32(regval, STM32L4_RCC_PLLCFG); putreg32(regval, STM32L4_RCC_PLLCFG);