TMS570: Add a FLASH controller header file
This commit is contained in:
Gregory Nutt
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1ddabf9ff1
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fac00f04d0
233
arch/arm/src/tms570/chip/tms570_flash.h
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233
arch/arm/src/tms570/chip/tms570_flash.h
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/****************************************************************************************************
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* arch/arm/src/tms570/chip/tms570_flash.h
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* FLASH Module Controller Register Definitions
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas
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* Instruments, Literature Number: SPNU517A, September 2013
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H
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#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/tms570_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define TMS570_FLASH_FRDCNTL_OFFSET 0x000 /* Flash Option Control Register */
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#define TMS570_FLASH_FEDACTRL1_OFFSET 0x008 /* Flash Error Detection and Correction Control Register 1 */
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#define TMS570_FLASH_FEDACTRL2_OFFSET 0x00c /* Flash Error Detection and Correction Control Register 2 */
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#define TMS570_FLASH_FCORERRCNT_OFFSET 0x010 /* Flash Correctable Error Count Register */
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#define TMS570_FLASH_FCORERRADD_OFFSET 0x014 /* Flash Correctable Error Address Register */
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#define TMS570_FLASH_FCORERRPOS_OFFSET 0x018 /* Flash Correctable Error Position Register */
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#define TMS570_FLASH_FEDACSTATUS_OFFSET 0x01c /* Flash Error Detection and Correction Status Register */
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#define TMS570_FLASH_FUNCERRADD_OFFSET 0x020 /* Flash Un-Correctable Error Address Register */
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#define TMS570_FLASH_FEDACSDIS_OFFSET 0x024 /* Flash Error Detection and Correction Sector Disable Register */
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#define TMS570_FLASH_FPRIMADDTAG_OFFSET 0x028 /* Flash Primary Address Tag Register */
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#define TMS570_FLASH_FDUPDDTAG_OFFSET 0x02c /* Flash Duplicate Address Tag Register */
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#define TMS570_FLASH_FBPROT_OFFSET 0x030 /* Flash Bank Protection Register */
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#define TMS570_FLASH_FBSE_OFFSET 0x034 /* Flash Bank Sector Enable Register */
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#define TMS570_FLASH_FBBUSY_OFFSET 0x038 /* Flash Bank Busy Register */
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#define TMS570_FLASH_FBAC_OFFSET 0x03c /* Flash Bank Access Control Register */
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#define TMS570_FLASH_FBFALLBACK_OFFSET 0x040 /* Flash Bank Fallback Power Register */
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#define TMS570_FLASH_FBPRDY_OFFSET 0x044 /* Flash Bank/Pump Ready Register */
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#define TMS570_FLASH_FPAC1_OFFSET 0x048 /* Flash Pump Access Control Register 1 */
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#define TMS570_FLASH_FPAC2_OFFSET 0x04c /* Flash Pump Access Control Register 2 */
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#define TMS570_FLASH_FMAC_OFFSET 0x050 /* Flash Module Access Control Register */
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#define TMS570_FLASH_FMSTAT_OFFSET 0x054 /* Flash Module Status Register */
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#define TMS570_FLASH_FEMUDMSW_OFFSET 0x058 /* EEPROM Emulation Data MSW Register */
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#define TMS570_FLASH_FEMUDLSW_OFFSET 0x05c /* EEPROM Emulation Data LSW Register */
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#define TMS570_FLASH_FEMUECC_OFFSET 0x060 /* EEPROM Emulation ECC Register */
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#define TMS570_FLASH_FEMUADDR_OFFSET 0x068 /* EEPROM Emulation Address Register */
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#define TMS570_FLASH_FDIAGCTRL_OFFSET 0x06c /* Diagnostic Control Register */
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#define TMS570_FLASH_FRAWDATAH_OFFSET 0x070 /* Uncorrected Raw Data High Register */
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#define TMS570_FLASH_FRAWDATAL_OFFSET 0x074 /* Uncorrected Raw Data Low Register */
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#define TMS570_FLASH_FRAWECC_OFFSET 0x078 /* Uncorrected Raw ECC Register */
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#define TMS570_FLASH_FPAROVR_OFFSET 0x07c /* Parity Override Register */
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#define TMS570_FLASH_FEDACSDIS2_OFFSET 0x0c0 /* Flash Error Detection and Correction Sector Disable Register 2 */
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#define TMS570_FLASH_FSMWRENA_OFFSET 0x288 /* FSM Register Write Enable */
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#define TMS570_FLASH_FSMSECTOR_OFFSET 0x2a4 /* FSM Sector Register */
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#define TMS570_FLASH_EEPROMCONFIG_OFFSET 0x2b8 /* EEPROM Emulation Configuration Register */
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#define TMS570_FLASH_EECTRL1_OFFSET 0x308 /* EEPROM Emulation Error Detection and Correction Control Register 1 */
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#define TMS570_FLASH_EECTRL2_OFFSET 0x30c /* EEPROM Emulation Error Detection and Correction Control Register 2 */
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#define TMS570_FLASH_EECORERRCNT_OFFSET 0x310 /* EEPROM Emulation Correctable Error Count Register */
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#define TMS570_FLASH_EECORERRADD_OFFSET 0x314 /* EEPROM Emulation Correctable Error Address Register */
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#define TMS570_FLASH_EECORERRPOS_OFFSET 0x318 /* EEPROM Emulation Correctable Error Bit Position Register */
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#define TMS570_FLASH_EESTATUS_OFFSET 0x31c /* EEPROM Emulation Error Status Register */
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#define TMS570_FLASH_EEUNCERRADD_OFFSET 0x320 /* EEPROM Emulation Un-Correctable Error Address Register */
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#define TMS570_FLASH_FCFGBANK_OFFSET 0x400 /* Flash Bank Configuration Register */
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/* Register Addresses *******************************************************************************/
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#define TMS570_FLASH_FRDCNTL (TMS570_FWRAP_BASE+TMS570_FLASH_FRDCNTL_OFFSET)
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#define TMS570_FLASH_FEDACTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL1_OFFSET)
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#define TMS570_FLASH_FEDACTRL2 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL2_OFFSET)
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#define TMS570_FLASH_FCORERRCNT (TMS570_FWRAP_BASE+TMS570_FLASH_FCORERRCNT_OFFSET)
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#define TMS570_FLASH_FCORERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_FCORERRADD_OFFSET)
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#define TMS570_FLASH_FCORERRPOS (TMS570_FWRAP_BASE+TMS570_FLASH_FCORERRPOS_OFFSET)
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#define TMS570_FLASH_FEDACSTATUS (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSTATUS_OFFSET)
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#define TMS570_FLASH_FUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_FUNCERRADD_OFFSET)
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#define TMS570_FLASH_FEDACSDIS (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSDIS_OFFSET)
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#define TMS570_FLASH_FPRIMADDTAG (TMS570_FWRAP_BASE+TMS570_FLASH_FPRIMADDTAG_OFFSET)
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#define TMS570_FLASH_FDUPDDTAG (TMS570_FWRAP_BASE+TMS570_FLASH_FDUPDDTAG_OFFSET)
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#define TMS570_FLASH_FBPROT (TMS570_FWRAP_BASE+TMS570_FLASH_FBPROT_OFFSET)
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#define TMS570_FLASH_FBSE (TMS570_FWRAP_BASE+TMS570_FLASH_FBSE_OFFSET)
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#define TMS570_FLASH_FBBUSY (TMS570_FWRAP_BASE+TMS570_FLASH_FBBUSY_OFFSET)
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#define TMS570_FLASH_FBAC (TMS570_FWRAP_BASE+TMS570_FLASH_FBAC_OFFSET)
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#define TMS570_FLASH_FBFALLBACK (TMS570_FWRAP_BASE+TMS570_FLASH_FBFALLBACK_OFFSET)
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#define TMS570_FLASH_FBPRDY (TMS570_FWRAP_BASE+TMS570_FLASH_FBPRDY_OFFSET)
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#define TMS570_FLASH_FPAC1 (TMS570_FWRAP_BASE+TMS570_FLASH_FPAC1_OFFSET)
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#define TMS570_FLASH_FPAC2 (TMS570_FWRAP_BASE+TMS570_FLASH_FPAC2_OFFSET)
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#define TMS570_FLASH_FMAC (TMS570_FWRAP_BASE+TMS570_FLASH_FMAC_OFFSET)
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#define TMS570_FLASH_FMSTAT (TMS570_FWRAP_BASE+TMS570_FLASH_FMSTAT_OFFSET)
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#define TMS570_FLASH_FEMUDMSW (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUDMSW_OFFSET)
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#define TMS570_FLASH_FEMUDLSW (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUDLSW_OFFSET)
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#define TMS570_FLASH_FEMUECC (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUECC_OFFSET)
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#define TMS570_FLASH_FEMUADDR (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUADDR_OFFSET)
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#define TMS570_FLASH_FDIAGCTRL (TMS570_FWRAP_BASE+TMS570_FLASH_FDIAGCTRL_OFFSET)
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#define TMS570_FLASH_FRAWDATAH (TMS570_FWRAP_BASE+TMS570_FLASH_FRAWDATAH_OFFSET)
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#define TMS570_FLASH_FRAWDATAL (TMS570_FWRAP_BASE+TMS570_FLASH_FRAWDATAL_OFFSET)
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#define TMS570_FLASH_FRAWECC (TMS570_FWRAP_BASE+TMS570_FLASH_FRAWECC_OFFSET)
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#define TMS570_FLASH_FPAROVR (TMS570_FWRAP_BASE+TMS570_FLASH_FPAROVR_OFFSET)
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#define TMS570_FLASH_FEDACSDIS2 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSDIS2_OFFSET)
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#define TMS570_FLASH_FSMWRENA (TMS570_FWRAP_BASE+TMS570_FLASH_FSMWRENA_OFFSET)
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#define TMS570_FLASH_FSMSECTOR (TMS570_FWRAP_BASE+TMS570_FLASH_FSMSECTOR_OFFSET)
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#define TMS570_FLASH_EEPROMCONFIG (TMS570_FWRAP_BASE+TMS570_FLASH_EEPROMCONFIG_OFFSET)
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#define TMS570_FLASH_EECTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_EECTRL1_OFFSET)
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#define TMS570_FLASH_EECTRL2 (TMS570_FWRAP_BASE+TMS570_FLASH_EECTRL2_OFFSET)
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#define TMS570_FLASH_EECORERRCNT (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRCNT_OFFSET)
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#define TMS570_FLASH_EECORERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRADD_OFFSET)
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#define TMS570_FLASH_EECORERRPOS (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRPOS_OFFSET)
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#define TMS570_FLASH_EESTATUS (TMS570_FWRAP_BASE+TMS570_FLASH_EESTATUS_OFFSET)
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#define TMS570_FLASH_EEUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EEUNCERRADD_OFFSET)
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#define TMS570_FLASH_FCFGBANK (TMS570_FWRAP_BASE+TMS570_FLASH_FCFGBANK_OFFSET)
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/* Register Bit-Field Definitions *******************************************************************/
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/* Flash Option Control Register */
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#define FLASH_FRDCNTL_
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/* Flash Error Detection and Correction Control Register 1 */
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#define FLASH_FEDACTRL1_
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/* Flash Error Detection and Correction Control Register 2 */
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#define FLASH_FEDACTRL2_
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/* Flash Correctable Error Count Register */
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#define FLASH_FCORERRCNT_
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/* Flash Correctable Error Address Register */
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#define FLASH_FCORERRADD_
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/* Flash Correctable Error Position Register */
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#define FLASH_FCORERRPOS_
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/* Flash Error Detection and Correction Status Register */
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#define FLASH_FEDACSTATUS_
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/* Flash Un-Correctable Error Address Register */
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#define FLASH_FUNCERRADD_
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/* Flash Error Detection and Correction Sector Disable Register */
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#define FLASH_FEDACSDIS_
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/* Flash Primary Address Tag Register */
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#define FLASH_FPRIMADDTAG_
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/* Flash Duplicate Address Tag Register */
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#define FLASH_FDUPDDTAG_
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/* Flash Bank Protection Register */
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#define FLASH_FBPROT_
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/* Flash Bank Sector Enable Register */
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#define FLASH_FBSE_
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/* Flash Bank Busy Register */
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#define FLASH_FBBUSY_
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/* Flash Bank Access Control Register */
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#define FLASH_FBAC_
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/* Flash Bank Fallback Power Register */
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#define FLASH_FBFALLBACK_
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/* Flash Bank/Pump Ready Register */
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#define FLASH_FBPRDY_
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/* Flash Pump Access Control Register 1 */
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#define FLASH_FPAC1_
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/* Flash Pump Access Control Register 2 */
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#define FLASH_FPAC2_
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/* Flash Module Access Control Register */
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#define FLASH_FMAC_
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/* Flash Module Status Register */
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#define FLASH_FMSTAT_
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/* EEPROM Emulation Data MSW Register */
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#define FLASH_FEMUDMSW_
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/* EEPROM Emulation Data LSW Register */
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#define FLASH_FEMUDLSW_
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/* EEPROM Emulation ECC Register */
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#define FLASH_FEMUECC_
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/* EEPROM Emulation Address Register */
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#define FLASH_FEMUADDR_
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/* Diagnostic Control Register */
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#define FLASH_FDIAGCTRL_
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/* Uncorrected Raw Data High Register */
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#define FLASH_FRAWDATAH_
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/* Uncorrected Raw Data Low Register */
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#define FLASH_FRAWDATAL_
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/* Uncorrected Raw ECC Register */
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#define FLASH_FRAWECC_
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/* Parity Override Register */
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#define FLASH_FPAROVR_
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/* Flash Error Detection and Correction Sector Disable Register 2 */
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#define FLASH_FEDACSDIS2_
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/* FSM Register Write Enable */
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#define FLASH_FSMWRENA_
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/* FSM Sector Register */
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#define FLASH_FSMSECTOR_
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/* EEPROM Emulation Configuration Register */
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#define FLASH_EEPROMCONFIG_
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/* EEPROM Emulation Error Detection and Correction Control Register 1 */
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#define FLASH_EECTRL1_
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/* EEPROM Emulation Error Detection and Correction Control Register 2 */
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#define FLASH_EECTRL2_
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/* EEPROM Emulation Correctable Error Count Register */
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#define FLASH_EECORERRCNT_
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/* EEPROM Emulation Correctable Error Address Register */
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#define FLASH_EECORERRADD_
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/* EEPROM Emulation Correctable Error Bit Position Register */
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#define FLASH_EECORERRPOS_
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/* EEPROM Emulation Error Status Register */
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#define FLASH_EESTATUS_
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/* EEPROM Emulation Un-Correctable Error Address Register */
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#define FLASH_EEUNCERRADD_
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/* Flash Bank Configuration Register */
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#define FLASH_FCFGBANK_
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#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H */
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@ -111,34 +111,49 @@
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/* Peripheral Memory Protection Set Register 0 */
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#define PCR_PMPROTSET0_
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/* Peripheral Memory Protection Set Register 1 */
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#define PCR_PMPROTSET1_
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/* Peripheral Memory Protection Clear Register 0 */
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#define PCR_PMPROTCLR0_
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/* Peripheral Memory Protection Clear Register 1 */
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#define PCR_PMPROTCLR1_
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/* Peripheral Protection Set Register 0 */
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#define PCR_PPROTSET0_
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/* Peripheral Protection Set Register 1 */
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#define PCR_PPROTSET1_
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/* Peripheral Protection Set Register 2 */
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#define PCR_PPROTSET2_
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/* Peripheral Protection Set Register 3 */
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#define PCR_PPROTSET3_
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/* Peripheral Protection Clear Register 0 */
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#define PCR_PPROTCLR0_
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/* Peripheral Protection Clear Register 1 */
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#define PCR_PPROTCLR1_
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/* Peripheral Protection Clear Register 2 */
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#define PCR_PPROTCLR2_
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/* Peripheral Protection Clear Register 3 */
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#define PCR_PPROTCLR3_
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/* Peripheral Memory Power-Down Set Register 0 */
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#define PCR_PCSPWRDWNSET0_
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/* Peripheral Memory Power-Down Set Register 1 */
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#define PCR_PCSPWRDWNSET1_
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/* Peripheral Memory Power-Down Clear Register 0 */
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#define PCR_PCSPWRDWNCLR0_
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/* Peripheral Memory Power-Down Clear Register 1 */
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#define PCR_PCSPWRDWNCLR1_
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@ -183,11 +183,6 @@ static void tms570_memory_initialize(uint32_t ramset)
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void arm_boot(void)
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{
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#ifdef CONFIG_ARCH_RAMFUNCS
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const uint32_t *src;
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uint32_t *dest;
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#endif
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/* Enable CPU Event Export.
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*
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* This allows the CPU to signal any single-bit or double-bit errors
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@ -290,10 +285,10 @@ void arm_boot(void)
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#endif
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#ifdef CONFIG_ARMV7R_MEMINIT
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/* If .data and .bss reside in SDRAM, then initialize the data sections
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/* Initialize the .bss and .data sections as well as RAM functions
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* now after RAM has been initialized.
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*
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* NOTE that is SDRAM were supported, this call might have to be
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* NOTE that if SDRAM were supported, this call might have to be
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* performed after returning from tms570_board_initialize()
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*/
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