diff --git a/arch/arm/src/tms570/chip/tms570_flash.h b/arch/arm/src/tms570/chip/tms570_flash.h new file mode 100644 index 0000000000..95db4a3d86 --- /dev/null +++ b/arch/arm/src/tms570/chip/tms570_flash.h @@ -0,0 +1,233 @@ +/**************************************************************************************************** + * arch/arm/src/tms570/chip/tms570_flash.h + * FLASH Module Controller Register Definitions + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * + * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas + * Instruments, Literature Number: SPNU517A, September 2013 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H +#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/tms570_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define TMS570_FLASH_FRDCNTL_OFFSET 0x000 /* Flash Option Control Register */ +#define TMS570_FLASH_FEDACTRL1_OFFSET 0x008 /* Flash Error Detection and Correction Control Register 1 */ +#define TMS570_FLASH_FEDACTRL2_OFFSET 0x00c /* Flash Error Detection and Correction Control Register 2 */ +#define TMS570_FLASH_FCORERRCNT_OFFSET 0x010 /* Flash Correctable Error Count Register */ +#define TMS570_FLASH_FCORERRADD_OFFSET 0x014 /* Flash Correctable Error Address Register */ +#define TMS570_FLASH_FCORERRPOS_OFFSET 0x018 /* Flash Correctable Error Position Register */ +#define TMS570_FLASH_FEDACSTATUS_OFFSET 0x01c /* Flash Error Detection and Correction Status Register */ +#define TMS570_FLASH_FUNCERRADD_OFFSET 0x020 /* Flash Un-Correctable Error Address Register */ +#define TMS570_FLASH_FEDACSDIS_OFFSET 0x024 /* Flash Error Detection and Correction Sector Disable Register */ +#define TMS570_FLASH_FPRIMADDTAG_OFFSET 0x028 /* Flash Primary Address Tag Register */ +#define TMS570_FLASH_FDUPDDTAG_OFFSET 0x02c /* Flash Duplicate Address Tag Register */ +#define TMS570_FLASH_FBPROT_OFFSET 0x030 /* Flash Bank Protection Register */ +#define TMS570_FLASH_FBSE_OFFSET 0x034 /* Flash Bank Sector Enable Register */ +#define TMS570_FLASH_FBBUSY_OFFSET 0x038 /* Flash Bank Busy Register */ +#define TMS570_FLASH_FBAC_OFFSET 0x03c /* Flash Bank Access Control Register */ +#define TMS570_FLASH_FBFALLBACK_OFFSET 0x040 /* Flash Bank Fallback Power Register */ +#define TMS570_FLASH_FBPRDY_OFFSET 0x044 /* Flash Bank/Pump Ready Register */ +#define TMS570_FLASH_FPAC1_OFFSET 0x048 /* Flash Pump Access Control Register 1 */ +#define TMS570_FLASH_FPAC2_OFFSET 0x04c /* Flash Pump Access Control Register 2 */ +#define TMS570_FLASH_FMAC_OFFSET 0x050 /* Flash Module Access Control Register */ +#define TMS570_FLASH_FMSTAT_OFFSET 0x054 /* Flash Module Status Register */ +#define TMS570_FLASH_FEMUDMSW_OFFSET 0x058 /* EEPROM Emulation Data MSW Register */ +#define TMS570_FLASH_FEMUDLSW_OFFSET 0x05c /* EEPROM Emulation Data LSW Register */ +#define TMS570_FLASH_FEMUECC_OFFSET 0x060 /* EEPROM Emulation ECC Register */ +#define TMS570_FLASH_FEMUADDR_OFFSET 0x068 /* EEPROM Emulation Address Register */ +#define TMS570_FLASH_FDIAGCTRL_OFFSET 0x06c /* Diagnostic Control Register */ +#define TMS570_FLASH_FRAWDATAH_OFFSET 0x070 /* Uncorrected Raw Data High Register */ +#define TMS570_FLASH_FRAWDATAL_OFFSET 0x074 /* Uncorrected Raw Data Low Register */ +#define TMS570_FLASH_FRAWECC_OFFSET 0x078 /* Uncorrected Raw ECC Register */ +#define TMS570_FLASH_FPAROVR_OFFSET 0x07c /* Parity Override Register */ +#define TMS570_FLASH_FEDACSDIS2_OFFSET 0x0c0 /* Flash Error Detection and Correction Sector Disable Register 2 */ +#define TMS570_FLASH_FSMWRENA_OFFSET 0x288 /* FSM Register Write Enable */ +#define TMS570_FLASH_FSMSECTOR_OFFSET 0x2a4 /* FSM Sector Register */ +#define TMS570_FLASH_EEPROMCONFIG_OFFSET 0x2b8 /* EEPROM Emulation Configuration Register */ +#define TMS570_FLASH_EECTRL1_OFFSET 0x308 /* EEPROM Emulation Error Detection and Correction Control Register 1 */ +#define TMS570_FLASH_EECTRL2_OFFSET 0x30c /* EEPROM Emulation Error Detection and Correction Control Register 2 */ +#define TMS570_FLASH_EECORERRCNT_OFFSET 0x310 /* EEPROM Emulation Correctable Error Count Register */ +#define TMS570_FLASH_EECORERRADD_OFFSET 0x314 /* EEPROM Emulation Correctable Error Address Register */ +#define TMS570_FLASH_EECORERRPOS_OFFSET 0x318 /* EEPROM Emulation Correctable Error Bit Position Register */ +#define TMS570_FLASH_EESTATUS_OFFSET 0x31c /* EEPROM Emulation Error Status Register */ +#define TMS570_FLASH_EEUNCERRADD_OFFSET 0x320 /* EEPROM Emulation Un-Correctable Error Address Register */ +#define TMS570_FLASH_FCFGBANK_OFFSET 0x400 /* Flash Bank Configuration Register */ + +/* Register Addresses *******************************************************************************/ + +#define TMS570_FLASH_FRDCNTL (TMS570_FWRAP_BASE+TMS570_FLASH_FRDCNTL_OFFSET) +#define TMS570_FLASH_FEDACTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL1_OFFSET) +#define TMS570_FLASH_FEDACTRL2 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACTRL2_OFFSET) +#define TMS570_FLASH_FCORERRCNT (TMS570_FWRAP_BASE+TMS570_FLASH_FCORERRCNT_OFFSET) +#define TMS570_FLASH_FCORERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_FCORERRADD_OFFSET) +#define TMS570_FLASH_FCORERRPOS (TMS570_FWRAP_BASE+TMS570_FLASH_FCORERRPOS_OFFSET) +#define TMS570_FLASH_FEDACSTATUS (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSTATUS_OFFSET) +#define TMS570_FLASH_FUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_FUNCERRADD_OFFSET) +#define TMS570_FLASH_FEDACSDIS (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSDIS_OFFSET) +#define TMS570_FLASH_FPRIMADDTAG (TMS570_FWRAP_BASE+TMS570_FLASH_FPRIMADDTAG_OFFSET) +#define TMS570_FLASH_FDUPDDTAG (TMS570_FWRAP_BASE+TMS570_FLASH_FDUPDDTAG_OFFSET) +#define TMS570_FLASH_FBPROT (TMS570_FWRAP_BASE+TMS570_FLASH_FBPROT_OFFSET) +#define TMS570_FLASH_FBSE (TMS570_FWRAP_BASE+TMS570_FLASH_FBSE_OFFSET) +#define TMS570_FLASH_FBBUSY (TMS570_FWRAP_BASE+TMS570_FLASH_FBBUSY_OFFSET) +#define TMS570_FLASH_FBAC (TMS570_FWRAP_BASE+TMS570_FLASH_FBAC_OFFSET) +#define TMS570_FLASH_FBFALLBACK (TMS570_FWRAP_BASE+TMS570_FLASH_FBFALLBACK_OFFSET) +#define TMS570_FLASH_FBPRDY (TMS570_FWRAP_BASE+TMS570_FLASH_FBPRDY_OFFSET) +#define TMS570_FLASH_FPAC1 (TMS570_FWRAP_BASE+TMS570_FLASH_FPAC1_OFFSET) +#define TMS570_FLASH_FPAC2 (TMS570_FWRAP_BASE+TMS570_FLASH_FPAC2_OFFSET) +#define TMS570_FLASH_FMAC (TMS570_FWRAP_BASE+TMS570_FLASH_FMAC_OFFSET) +#define TMS570_FLASH_FMSTAT (TMS570_FWRAP_BASE+TMS570_FLASH_FMSTAT_OFFSET) +#define TMS570_FLASH_FEMUDMSW (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUDMSW_OFFSET) +#define TMS570_FLASH_FEMUDLSW (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUDLSW_OFFSET) +#define TMS570_FLASH_FEMUECC (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUECC_OFFSET) +#define TMS570_FLASH_FEMUADDR (TMS570_FWRAP_BASE+TMS570_FLASH_FEMUADDR_OFFSET) +#define TMS570_FLASH_FDIAGCTRL (TMS570_FWRAP_BASE+TMS570_FLASH_FDIAGCTRL_OFFSET) +#define TMS570_FLASH_FRAWDATAH (TMS570_FWRAP_BASE+TMS570_FLASH_FRAWDATAH_OFFSET) +#define TMS570_FLASH_FRAWDATAL (TMS570_FWRAP_BASE+TMS570_FLASH_FRAWDATAL_OFFSET) +#define TMS570_FLASH_FRAWECC (TMS570_FWRAP_BASE+TMS570_FLASH_FRAWECC_OFFSET) +#define TMS570_FLASH_FPAROVR (TMS570_FWRAP_BASE+TMS570_FLASH_FPAROVR_OFFSET) +#define TMS570_FLASH_FEDACSDIS2 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSDIS2_OFFSET) +#define TMS570_FLASH_FSMWRENA (TMS570_FWRAP_BASE+TMS570_FLASH_FSMWRENA_OFFSET) +#define TMS570_FLASH_FSMSECTOR (TMS570_FWRAP_BASE+TMS570_FLASH_FSMSECTOR_OFFSET) +#define TMS570_FLASH_EEPROMCONFIG (TMS570_FWRAP_BASE+TMS570_FLASH_EEPROMCONFIG_OFFSET) +#define TMS570_FLASH_EECTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_EECTRL1_OFFSET) +#define TMS570_FLASH_EECTRL2 (TMS570_FWRAP_BASE+TMS570_FLASH_EECTRL2_OFFSET) +#define TMS570_FLASH_EECORERRCNT (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRCNT_OFFSET) +#define TMS570_FLASH_EECORERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRADD_OFFSET) +#define TMS570_FLASH_EECORERRPOS (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRPOS_OFFSET) +#define TMS570_FLASH_EESTATUS (TMS570_FWRAP_BASE+TMS570_FLASH_EESTATUS_OFFSET) +#define TMS570_FLASH_EEUNCERRADD (TMS570_FWRAP_BASE+TMS570_FLASH_EEUNCERRADD_OFFSET) +#define TMS570_FLASH_FCFGBANK (TMS570_FWRAP_BASE+TMS570_FLASH_FCFGBANK_OFFSET) + +/* Register Bit-Field Definitions *******************************************************************/ + +/* Flash Option Control Register */ +#define FLASH_FRDCNTL_ +/* Flash Error Detection and Correction Control Register 1 */ +#define FLASH_FEDACTRL1_ +/* Flash Error Detection and Correction Control Register 2 */ +#define FLASH_FEDACTRL2_ +/* Flash Correctable Error Count Register */ +#define FLASH_FCORERRCNT_ +/* Flash Correctable Error Address Register */ +#define FLASH_FCORERRADD_ +/* Flash Correctable Error Position Register */ +#define FLASH_FCORERRPOS_ +/* Flash Error Detection and Correction Status Register */ +#define FLASH_FEDACSTATUS_ +/* Flash Un-Correctable Error Address Register */ +#define FLASH_FUNCERRADD_ +/* Flash Error Detection and Correction Sector Disable Register */ +#define FLASH_FEDACSDIS_ +/* Flash Primary Address Tag Register */ +#define FLASH_FPRIMADDTAG_ +/* Flash Duplicate Address Tag Register */ +#define FLASH_FDUPDDTAG_ +/* Flash Bank Protection Register */ +#define FLASH_FBPROT_ +/* Flash Bank Sector Enable Register */ +#define FLASH_FBSE_ +/* Flash Bank Busy Register */ +#define FLASH_FBBUSY_ +/* Flash Bank Access Control Register */ +#define FLASH_FBAC_ +/* Flash Bank Fallback Power Register */ +#define FLASH_FBFALLBACK_ +/* Flash Bank/Pump Ready Register */ +#define FLASH_FBPRDY_ +/* Flash Pump Access Control Register 1 */ +#define FLASH_FPAC1_ +/* Flash Pump Access Control Register 2 */ +#define FLASH_FPAC2_ +/* Flash Module Access Control Register */ +#define FLASH_FMAC_ +/* Flash Module Status Register */ +#define FLASH_FMSTAT_ +/* EEPROM Emulation Data MSW Register */ +#define FLASH_FEMUDMSW_ +/* EEPROM Emulation Data LSW Register */ +#define FLASH_FEMUDLSW_ +/* EEPROM Emulation ECC Register */ +#define FLASH_FEMUECC_ +/* EEPROM Emulation Address Register */ +#define FLASH_FEMUADDR_ +/* Diagnostic Control Register */ +#define FLASH_FDIAGCTRL_ +/* Uncorrected Raw Data High Register */ +#define FLASH_FRAWDATAH_ +/* Uncorrected Raw Data Low Register */ +#define FLASH_FRAWDATAL_ +/* Uncorrected Raw ECC Register */ +#define FLASH_FRAWECC_ +/* Parity Override Register */ +#define FLASH_FPAROVR_ +/* Flash Error Detection and Correction Sector Disable Register 2 */ +#define FLASH_FEDACSDIS2_ +/* FSM Register Write Enable */ +#define FLASH_FSMWRENA_ +/* FSM Sector Register */ +#define FLASH_FSMSECTOR_ +/* EEPROM Emulation Configuration Register */ +#define FLASH_EEPROMCONFIG_ +/* EEPROM Emulation Error Detection and Correction Control Register 1 */ +#define FLASH_EECTRL1_ +/* EEPROM Emulation Error Detection and Correction Control Register 2 */ +#define FLASH_EECTRL2_ +/* EEPROM Emulation Correctable Error Count Register */ +#define FLASH_EECORERRCNT_ +/* EEPROM Emulation Correctable Error Address Register */ +#define FLASH_EECORERRADD_ +/* EEPROM Emulation Correctable Error Bit Position Register */ +#define FLASH_EECORERRPOS_ +/* EEPROM Emulation Error Status Register */ +#define FLASH_EESTATUS_ +/* EEPROM Emulation Un-Correctable Error Address Register */ +#define FLASH_EEUNCERRADD_ +/* Flash Bank Configuration Register */ +#define FLASH_FCFGBANK_ + +#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H */ diff --git a/arch/arm/src/tms570/chip/tms570_pcr.h b/arch/arm/src/tms570/chip/tms570_pcr.h index 4c4df2ca44..c928da5e6c 100644 --- a/arch/arm/src/tms570/chip/tms570_pcr.h +++ b/arch/arm/src/tms570/chip/tms570_pcr.h @@ -111,34 +111,49 @@ /* Peripheral Memory Protection Set Register 0 */ #define PCR_PMPROTSET0_ + /* Peripheral Memory Protection Set Register 1 */ #define PCR_PMPROTSET1_ + /* Peripheral Memory Protection Clear Register 0 */ #define PCR_PMPROTCLR0_ + /* Peripheral Memory Protection Clear Register 1 */ #define PCR_PMPROTCLR1_ + /* Peripheral Protection Set Register 0 */ #define PCR_PPROTSET0_ + /* Peripheral Protection Set Register 1 */ #define PCR_PPROTSET1_ + /* Peripheral Protection Set Register 2 */ #define PCR_PPROTSET2_ + /* Peripheral Protection Set Register 3 */ #define PCR_PPROTSET3_ + /* Peripheral Protection Clear Register 0 */ #define PCR_PPROTCLR0_ + /* Peripheral Protection Clear Register 1 */ #define PCR_PPROTCLR1_ + /* Peripheral Protection Clear Register 2 */ #define PCR_PPROTCLR2_ + /* Peripheral Protection Clear Register 3 */ #define PCR_PPROTCLR3_ + /* Peripheral Memory Power-Down Set Register 0 */ #define PCR_PCSPWRDWNSET0_ + /* Peripheral Memory Power-Down Set Register 1 */ #define PCR_PCSPWRDWNSET1_ + /* Peripheral Memory Power-Down Clear Register 0 */ #define PCR_PCSPWRDWNCLR0_ + /* Peripheral Memory Power-Down Clear Register 1 */ #define PCR_PCSPWRDWNCLR1_ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index b1b9b6ed1f..593c243213 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -183,11 +183,6 @@ static void tms570_memory_initialize(uint32_t ramset) void arm_boot(void) { -#ifdef CONFIG_ARCH_RAMFUNCS - const uint32_t *src; - uint32_t *dest; -#endif - /* Enable CPU Event Export. * * This allows the CPU to signal any single-bit or double-bit errors @@ -290,10 +285,10 @@ void arm_boot(void) #endif #ifdef CONFIG_ARMV7R_MEMINIT - /* If .data and .bss reside in SDRAM, then initialize the data sections + /* Initialize the .bss and .data sections as well as RAM functions * now after RAM has been initialized. * - * NOTE that is SDRAM were supported, this call might have to be + * NOTE that if SDRAM were supported, this call might have to be * performed after returning from tms570_board_initialize() */