arch/arm/src/stm32l4/stm32l4xrxx_rcc.c: Use Range 1 Boost mode if SYSCLK is higher than 80 MHz
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@ -74,6 +74,9 @@
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#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
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#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */
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#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */
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#endif
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/* Register Addresses ***************************************************************/
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@ -102,6 +105,9 @@
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#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET)
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#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET)
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#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET)
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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@ -114,6 +120,9 @@
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# define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
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# define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
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# define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define PWR_CR1_RRSTP (1 << 4) /* Bit 4: SRAM3 retention in Stop 2 mode */
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#endif
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#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */
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#define PWR_CR1_VOS_SHIFT 9
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#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) /* Bits 9-10: Voltage scaling range selection */
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@ -154,6 +163,9 @@
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#define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */
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#define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */
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#define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define PWR_CR3_DSIPDEN (1 << 12) /* Bit 12: Enable Pull-down activation on DSI pins */
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#endif
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#define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */
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/* Power control register 4 */
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@ -202,4 +214,10 @@
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/* Port X pull-up/down registers have one bit per port line, with a few exceptions */
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/* Power control register 5 */
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define PWR_CR5_R1MODE (1 << 8) /* Bit 8: Main regulator in Range 1 normal mode. */
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#endif
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#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H */
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@ -726,21 +726,20 @@ static void stm32l4_stdclockconfig(void)
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if (timeout > 0)
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{
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#warning todo: regulator voltage according to clock freq
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#if 0
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/* Ensure Power control is enabled before modifying it. */
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regval = getreg32(STM32L4_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32L4_RCC_APB1ENR);
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regval = getreg32(STM32L4_RCC_APB1ENR1);
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regval |= RCC_APB1ENR1_PWREN;
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putreg32(regval, STM32L4_RCC_APB1ENR1);
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/* Select regulator voltage output Scale 1 mode to support system
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* frequencies up to 168 MHz.
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/* Switch to Range 1 boost mode to support system
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* frequencies up to 120 MHz. Range 2 is not supported.
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*/
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regval = getreg32(STM32L4_PWR_CR);
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regval &= ~PWR_CR_VOS_MASK;
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regval |= PWR_CR_VOS_SCALE_1;
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putreg32(regval, STM32L4_PWR_CR);
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#if STM32L4_SYSCLK_FREQUENCY > 80000000
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regval = getreg32(STM32L4_PWR_CR5);
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regval &= ~PWR_CR5_R1MODE;
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putreg32(regval, STM32L4_PWR_CR5);
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#endif
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/* Set the HCLK source/divider */
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@ -933,15 +932,6 @@ static void stm32l4_stdclockconfig(void)
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* XXX and other cases, like automatic trimming of MSI for USB use
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*/
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/* ensure Power control is enabled since it is indirectly required
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* to alter the LSE parameters.
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*/
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stm32l4_pwr_enableclk(true);
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/* XXX other LSE settings must be made before turning on the oscillator
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* and we need to ensure it is first off before doing so.
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*/
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/* Turn on the LSE oscillator
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* XXX this will almost surely get moved since we also want to use
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* this for automatically trimming MSI, etc.
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