Add support for the SAM4CM. From Max Neklyudov
This commit is contained in:
Gregory Nutt
parent
11896e1481
commit
fae790a6dc
@ -355,6 +355,55 @@
|
||||
# define SAM34_NUDPFS 0 /* No USB full speed device */
|
||||
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
|
||||
|
||||
/* AT91SAM4C Family *****************************************************************/
|
||||
/* FEATURE SAM4CMP16B
|
||||
* ----------- ---------
|
||||
* Flash 1024KB
|
||||
* SRAM 128KB
|
||||
* SMC Yes
|
||||
* GMCC 2KB
|
||||
* Package LQFP144
|
||||
* LFBGA144
|
||||
* No. PIOs 117
|
||||
* SHDN Pin No
|
||||
* EMAC MII
|
||||
* CAN 2
|
||||
* EBI Yes
|
||||
* EBI data 8
|
||||
* EBI ch 4
|
||||
* EBI addr 24
|
||||
* SDRAM ---
|
||||
* DMA 4
|
||||
* 16-bit ADC0 16ch
|
||||
* 16-bit ADC1 8ch
|
||||
* 12-bit DAC 2ch
|
||||
* Timer 9
|
||||
* PDC Channels 24+9
|
||||
* USART 2
|
||||
* UART 2
|
||||
* SPI 1
|
||||
* HSMCI 4 bit
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_ATSAM4CMP16B)
|
||||
/* Internal memory */
|
||||
|
||||
# define SAM34_FLASH_SIZE (1024*1024) /* 1024KB */
|
||||
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
|
||||
# define SAM34_SRAM1_SIZE 0 /* None */
|
||||
# define SAM34_NFCSRAM_SIZE 0 /* None */
|
||||
|
||||
/* Peripherals */
|
||||
|
||||
# define SAM34_NDMACHAN 21 /* 21 PDC Channels */
|
||||
# define SAM34_NMCI2 0 /* No memory card interface */
|
||||
# define SAM32_NSLCD 1 /* 1 segment LCD interface */
|
||||
# define SAM32_NAESA 1 /* 1 advanced encryption standard */
|
||||
# define SAM32_NUDPHS 0 /* No USB high speed device */
|
||||
# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
|
||||
# define SAM32_NUDPFS 0 /* No USB full speed device */
|
||||
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
|
||||
|
||||
/* AT91SAM4L Family *****************************************************************/
|
||||
/* Sub-family differences:
|
||||
*
|
||||
|
||||
@ -86,6 +86,8 @@
|
||||
# include <arch/sam34/sam4s_irq.h>
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include <arch/sam34/sam4e_irq.h>
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include <arch/sam34/sam4cm_irq.h>
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
#endif
|
||||
|
||||
305
arch/arm/include/sam34/sam4cm_irq.h
Normal file
305
arch/arm/include/sam34/sam4cm_irq.h
Normal file
@ -0,0 +1,305 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/include/sam34/sam4cm_irq.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly through
|
||||
* nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4CM_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_SAM34_SAM4CM_IRQ_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************************/
|
||||
|
||||
/* SAM4CM Peripheral Identifiers */
|
||||
|
||||
#define SAM_PID_SUPC (0) /* Supply Controller */
|
||||
#define SAM_PID_RSTC (1) /* Reset Controller */
|
||||
#define SAM_PID_RTC (2) /* Real Time Clock */
|
||||
#define SAM_PID_RTT (3) /* Real Time Timer */
|
||||
#define SAM_PID_WDT (4) /* Watchdog Timer */
|
||||
#define SAM_PID_PMC (5) /* Power Management Controller */
|
||||
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
|
||||
#define SAM_PID_RESERVED_7 (7) /* Reserved */
|
||||
#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */
|
||||
#define SAM_PID_RESERVED_9 (9) /* Reserved */
|
||||
#define SAM_PID_SMC (10) /* Static Memory Controller */
|
||||
#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */
|
||||
#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */
|
||||
#define SAM_PID_RESERVED_13 (13) /* Reserved */
|
||||
#define SAM_PID_USART0 (14) /* USART 0 */
|
||||
#define SAM_PID_USART1 (15) /* USART 1 */
|
||||
#define SAM_PID_USART2 (16) /* USART 2 */
|
||||
#define SAM_PID_USART3 (17) /* USART 3 */
|
||||
#define SAM_PID_RESERVED_18 (18) /* Reserved */
|
||||
#define SAM_PID_TWI0 (19) /* Two-Wire Interface 0 */
|
||||
#define SAM_PID_TWI1 (20) /* Two-Wire Interface 1 */
|
||||
#define SAM_PID_SPI0 (21) /* Serial Peripheral Interface */
|
||||
#define SAM_PID_RESERVED_22 (22) /* Reserved */
|
||||
#define SAM_PID_TC0 (23) /* Timer Counter 0 */
|
||||
#define SAM_PID_TC1 (24) /* Timer Counter 1 */
|
||||
#define SAM_PID_TC2 (25) /* Timer Counter 2 */
|
||||
#define SAM_PID_TC3 (26) /* Timer Counter 3 */
|
||||
#define SAM_PID_TC4 (27) /* Timer Counter 4 */
|
||||
#define SAM_PID_TC5 (28) /* Timer Counter 5 */
|
||||
#define SAM_PID_ADC (29) /* Analog To Digital Converter */
|
||||
#define SAM_PID_ARM (30) /* FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
|
||||
#define SAM_PID_IPC0 (31) /* Interprocessor communication 0 */
|
||||
#define SAM_PID_SLCDC (32) /* Segment LCD Controller */
|
||||
#define SAM_PID_TRNG (33) /* True Random Generator */
|
||||
#define SAM_PID_ICM (34) /* Integrity Check Module */
|
||||
#define SAM_PID_CPKCC (35) /* Classical Public Key Cryptography Controller */
|
||||
#define SAM_PID_AES (36) /* Advanced Enhanced Standard */
|
||||
#define SAM_PID_PIOC (37) /* Parallel I/O Controller C */
|
||||
#define SAM_PID_UART1 (38) /* Universal Asynchronous Receiver Transmitter 1 */
|
||||
#define SAM_PID_IPC1 (39) /* Interprocessor communication 1 */
|
||||
#define SAM_PID_RESERVED_40 (40) /* Reserved */
|
||||
#define SAM_PID_PWM (41) /* Pulse Width Modulation */
|
||||
#define SAM_PID_SRAM (42) /* SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
|
||||
#define SAM_PID_SMC1 (43) /* Static Memory Controller 1 */
|
||||
#define NR_PIDS (44) /* Number of peripheral identifiers */
|
||||
|
||||
/* External interrupts (vectors >= 16) */
|
||||
|
||||
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* PID 0: Supply Controller */
|
||||
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* PID 1: Reset Controller */
|
||||
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* PID 2: Real Time Clock */
|
||||
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* PID 3: Real Time Timer */
|
||||
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* PID 4: Watchdog Timer */
|
||||
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* PID 5: Power Management Controller */
|
||||
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* PID 6: Enhanced Embedded Flash Controller 0 */
|
||||
#define SAM_IRQ_RESERVED_7 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_7) /* PID 7: Reserved */
|
||||
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* PID 8: Universal Asynchronous Receiver Transmitter 0 */
|
||||
#define SAM_IRQ_RESERVED_9 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_9) /* PID 9: Reserved */
|
||||
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* PID 10: Static Memory Controller */
|
||||
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* PID 11: Parallel I/O Controller A */
|
||||
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* PID 12: Parallel I/O Controller B */
|
||||
#define SAM_IRQ_RESERVED_13 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_13) /* PID 13: Reserved */
|
||||
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* PID 14: USART 0 */
|
||||
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* PID 15: USART 1 */
|
||||
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* PID 16: USART 2 */
|
||||
#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* PID 17: USART 3 */
|
||||
#define SAM_IRQ_RESERVED_18 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_18) /* PID 18: Reserved */
|
||||
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* PID 19: Two-Wire Interface 0 */
|
||||
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* PID 20: Two-Wire Interface 1 */
|
||||
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* PIC 21: Serial Peripheral Interface */
|
||||
#define SAM_IRQ_RESERVED_22 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_22) /* PID 22: Reserved */
|
||||
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* PID 23: Timer Counter 0 */
|
||||
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* PID 24: Timer Counter 1 */
|
||||
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* PID 25: Timer Counter 2 */
|
||||
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* PID 26: Timer Counter 3 */
|
||||
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* PID 27: Timer Counter 4 */
|
||||
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */
|
||||
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */
|
||||
#define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* PID 30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
|
||||
#define SAM_IRQ_IPC0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */
|
||||
#define SAM_IRQ_SLCDC (SAM_IRQ_EXTINT+SAM_PID_SLCDC) /* PID 32: Segment LCD Controller */
|
||||
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* PID 33: True Random Generator */
|
||||
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+SAM_PID_ICM) /* PID 34: Integrity Check Module */
|
||||
#define SAM_IRQ_CPKCC (SAM_IRQ_EXTINT+SAM_PID_CPKCC) /* PID 35: Classical Public Key Cryptography Controller */
|
||||
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* PID 36: Advanced Enhanced Standard */
|
||||
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 37: Parallel I/O Controller C */
|
||||
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 38: Universal Asynchronous Receiver Transmitter 1 */
|
||||
#define SAM_IRQ_IPC1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */
|
||||
#define SAM_IRQ_RESERVED_40 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_40) /* PID 40: Reserved */
|
||||
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 41: Pulse Width Modulation */
|
||||
#define SAM_IRQ_SRAM (SAM_IRQ_EXTINT+SAM_PID_SRAM) /* PID 42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
|
||||
#define SAM_IRQ_SMC1 (SAM_IRQ_EXTINT+SAM_PID_SMC1) /* PID 43: Static Memory Controller 1 */
|
||||
|
||||
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
|
||||
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT + NR_PIDS) /* The number of real IRQs */
|
||||
|
||||
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
|
||||
|
||||
#ifdef CONFIG_GPIOA_IRQ
|
||||
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
|
||||
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
|
||||
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
|
||||
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
|
||||
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
|
||||
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
|
||||
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
|
||||
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
|
||||
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
|
||||
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
|
||||
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
|
||||
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
|
||||
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
|
||||
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
|
||||
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
|
||||
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
|
||||
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
|
||||
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
|
||||
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
|
||||
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
|
||||
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
|
||||
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
|
||||
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
|
||||
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
|
||||
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
|
||||
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
|
||||
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
|
||||
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
|
||||
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
|
||||
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
|
||||
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
|
||||
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
|
||||
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
|
||||
# define SAM_NGPIOAIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOAIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIOB_IRQ
|
||||
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
|
||||
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
|
||||
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
|
||||
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
|
||||
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
|
||||
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
|
||||
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
|
||||
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
|
||||
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
|
||||
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
|
||||
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
|
||||
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
|
||||
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
|
||||
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
|
||||
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
|
||||
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
|
||||
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
|
||||
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
|
||||
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
|
||||
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
|
||||
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
|
||||
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
|
||||
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
|
||||
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
|
||||
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
|
||||
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
|
||||
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
|
||||
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
|
||||
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
|
||||
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
|
||||
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
|
||||
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
|
||||
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
|
||||
# define SAM_NGPIOBIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOBIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIOC_IRQ
|
||||
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
|
||||
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
|
||||
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
|
||||
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
|
||||
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
|
||||
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
|
||||
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
|
||||
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
|
||||
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
|
||||
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
|
||||
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
|
||||
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
|
||||
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
|
||||
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
|
||||
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
|
||||
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
|
||||
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
|
||||
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
|
||||
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
|
||||
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
|
||||
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
|
||||
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
|
||||
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
|
||||
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
|
||||
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
|
||||
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
|
||||
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
|
||||
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
|
||||
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
|
||||
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
|
||||
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
|
||||
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
|
||||
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
|
||||
# define SAM_NGPIOCIRQS 32
|
||||
#else
|
||||
# define SAM_NGPIOCIRQS 0
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_VECTORS SAM_IRQ_NIRQS
|
||||
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
|
||||
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4CM_IRQ_H */
|
||||
@ -78,6 +78,11 @@ config ARCH_CHIP_ATSAM3A4C
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_CHIP_SAM3A
|
||||
|
||||
config ARCH_CHIP_ATSAM4CMP16B
|
||||
bool "ATSAM4CMP16B"
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_CHIP_SAM4CM
|
||||
|
||||
config ARCH_CHIP_ATSAM4LC2C
|
||||
bool "ATSAM4LC2C"
|
||||
select ARCH_CORTEXM4
|
||||
@ -226,6 +231,10 @@ config ARCH_CHIP_SAM3A
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARCH_CHIP_SAM4CM
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARCH_CHIP_SAM4L
|
||||
bool
|
||||
default n
|
||||
@ -388,6 +397,11 @@ config SAM34_IISC
|
||||
default n
|
||||
depends on ARCH_CHIP_SAM4L
|
||||
|
||||
config SAM34_SLCDC
|
||||
bool "Segment LCD Controller (SLCDC)"
|
||||
default n
|
||||
depends on ARCH_CHIP_SAM4CM
|
||||
|
||||
config SAM34_LCDCA
|
||||
bool "LCD Controller A (LCDCA)"
|
||||
default n
|
||||
@ -558,13 +572,13 @@ config SAM34_TWIM3
|
||||
config SAM34_UART0
|
||||
bool "UART 0"
|
||||
default y
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
select ARCH_HAVE_UART0
|
||||
|
||||
config SAM34_UART1
|
||||
bool "UART 1"
|
||||
default n
|
||||
depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
depends on ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
select ARCH_HAVE_UART1
|
||||
|
||||
config SAM34_UDP
|
||||
@ -602,13 +616,13 @@ config SAM34_USART2
|
||||
bool "USART 2"
|
||||
default n
|
||||
select ARCH_HAVE_USART2
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L
|
||||
|
||||
config SAM34_USART3
|
||||
bool "USART 3"
|
||||
default n
|
||||
select ARCH_HAVE_USART3
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L
|
||||
|
||||
config SAM34_WDT
|
||||
bool "Watchdog Timer (WDT)"
|
||||
|
||||
@ -86,6 +86,10 @@ CHIP_CSRCS += sam_serial.c sam_start.c sam_timerisr.c
|
||||
|
||||
# Configuration-dependent SAM3/4 files
|
||||
|
||||
ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
|
||||
CHIP_CSRCS += sam4cm_supc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
|
||||
CHIP_CSRCS += sam4l_clockconfig.c sam4l_periphclks.c sam4l_gpio.c
|
||||
else
|
||||
|
||||
@ -58,6 +58,8 @@
|
||||
# include "chip/sam3u_vectors.h"
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "chip/sam3x_vectors.h"
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "chip/sam4cm_vectors.h"
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_vectors.h"
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
175
arch/arm/src/sam34/chip/sam4cm_memorymap.h
Normal file
175
arch/arm/src/sam34/chip/sam4cm_memorymap.h
Normal file
@ -0,0 +1,175 @@
|
||||
/************************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam4cm_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
|
||||
/* Address regions */
|
||||
|
||||
#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
|
||||
#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
|
||||
#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
|
||||
#define SAM_EXTRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External RAM */
|
||||
#define SAM_EXTDEV_BASE 0xa0000000 /* 0xa0000000-0xdfffffff: External device */
|
||||
#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
|
||||
|
||||
/* Code memory region */
|
||||
|
||||
#define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x00ffffff: Boot Memory */
|
||||
#define SAM_INTFLASH_BASE 0x01000000 /* 0x01000000-0x01ffffff: Internal FLASH */
|
||||
#define SAM_INTROM_BASE 0x02000000 /* 0x02000000-0x02ffffff: Internal ROM */
|
||||
|
||||
/* Internal SRAM memory region */
|
||||
|
||||
#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */
|
||||
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */
|
||||
/* 0x24000000-0x3fffffff: Undefined */
|
||||
/* Peripherals address region */
|
||||
|
||||
#define SAM_AES_BASE 0x40000000
|
||||
#define SAM_SPI0_BASE 0x40008000
|
||||
#define SAM_TC0_BASE 0x40010000
|
||||
#define SAM_TC1_BASE 0x40010040
|
||||
#define SAM_TC2_BASE 0x40010080
|
||||
#define SAM_TC3_BASE 0x40014000
|
||||
#define SAM_TC4_BASE 0x40014040
|
||||
#define SAM_TC5_BASE 0x40014080
|
||||
#define SAM_TWI0_BASE 0x40018000
|
||||
#define SAM_TWI1_BASE 0x4001C000
|
||||
#define SAM_USART0_BASE 0x40024000
|
||||
#define SAM_USART1_BASE 0x40028000
|
||||
#define SAM_USART2_BASE 0x4002C000
|
||||
#define SAM_USART3_BASE 0x40030000
|
||||
#define SAM_ADC_BASE 0x40038000
|
||||
#define SAM_SLCDC_BASE 0x4003C000
|
||||
#define SAM_CPKCC_BASE 0x40040000
|
||||
#define SAM_ICM_BASE 0x40044000
|
||||
#define SAM_TRNG_BASE 0x40048000
|
||||
#define SAM_IPC0_BASE 0x4004C000
|
||||
#define SAM_CMCC0_BASE 0x4007C000
|
||||
#define SAM_SMC0_BASE 0x400E0000
|
||||
#define SAM_MATRIX_BASE 0x400E0200
|
||||
# define SAM_MATRIX0_BASE 0x400E0200
|
||||
#define SAM_PMC_BASE 0x400E0400
|
||||
#define SAM_UART0_BASE 0x400E0600
|
||||
#define SAM_CHIPID_BASE 0x400E0740
|
||||
#define SAM_EEFC0_BASE 0x400E0A00
|
||||
#define SAM_EEFC1_BASE 0x400E0C00
|
||||
#define SAM_PIOA_BASE 0x400E0E00
|
||||
#define SAM_PIOB_BASE 0x400E1000
|
||||
#define SAM_RSTC_BASE 0x400E1400
|
||||
#define SAM_SUPC_BASE 0x400E1410
|
||||
#define SAM_RTT_BASE 0x400E1430
|
||||
#define SAM_WDT_BASE 0x400E1450
|
||||
#define SAM_RTC_BASE 0x400E1460
|
||||
#define SAM_GPBR_BASE 0x400E1490
|
||||
#define SAM_UART1_BASE 0x48004000
|
||||
#define SAM_PWM_BASE 0x48008000
|
||||
#define SAM_PIOC_BASE 0x4800C000
|
||||
#define SAM_MATRIX1_BASE 0x48010000
|
||||
#define SAM_IPC1_BASE 0x48014000
|
||||
#define SAM_CMCC1_BASE 0x48018000
|
||||
#define SAM_SMC1_BASE 0x4801C000
|
||||
|
||||
/* External RAM memory region */
|
||||
|
||||
#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
|
||||
# define SAM_EXTCSN_BASE(n) (0x60000000*((n)<<24))
|
||||
# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */
|
||||
# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */
|
||||
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
|
||||
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
|
||||
/* 0x64000000-0x9fffffff: Reserved */
|
||||
/* System memory region */
|
||||
|
||||
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
|
||||
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
static inline unsigned long SAM_PION_BASE(int n)
|
||||
{
|
||||
switch(n) {
|
||||
case 0:
|
||||
return SAM_PIOA_BASE;
|
||||
case 1:
|
||||
return SAM_PIOB_BASE;
|
||||
case 2:
|
||||
return SAM_PIOC_BASE;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H */
|
||||
322
arch/arm/src/sam34/chip/sam4cm_pinmap.h
Normal file
322
arch/arm/src/sam34/chip/sam4cm_pinmap.h
Normal file
@ -0,0 +1,322 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam4cm_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* GPIO pin definitions *************************************************************/
|
||||
/* Alternate Pin Functions.
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if we
|
||||
* wanted the programmable clock output PCK0 on PA6, then the following definition
|
||||
* should appear in the board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_PCK0 GPIO_PCK0_1
|
||||
*
|
||||
* The driver will then automatically configure PA6 as the PCK0 pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
* Additional effort is required to select specific GPIO options such as frequency,
|
||||
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
|
||||
* pins in this file.
|
||||
*/
|
||||
|
||||
/* 12-bit Analog-to-Digital Converter (ADC) */
|
||||
|
||||
#define GPIO_ADC0_AD0 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12)
|
||||
#define GPIO_ADC0_AD1 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4)
|
||||
#define GPIO_ADC0_AD2 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5)
|
||||
#define GPIO_ADC0_AD3 (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
|
||||
|
||||
/* Programmable Clock Output */
|
||||
|
||||
#define GPIO_PCK0_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6)
|
||||
#define GPIO_PCK0_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
|
||||
#define GPIO_PCK1_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17)
|
||||
#define GPIO_PCK1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21)
|
||||
#define GPIO_PCK2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18)
|
||||
#define GPIO_PCK2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31)
|
||||
#define GPIO_PCK2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3)
|
||||
|
||||
/* Pulse Width Modulation (PWM) */
|
||||
|
||||
#define GPIO_PWM0_FI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9)
|
||||
#define GPIO_PWM0_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0)
|
||||
#define GPIO_PWM0_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN0)
|
||||
#define GPIO_PWM0_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11)
|
||||
#define GPIO_PWM0_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
|
||||
#define GPIO_PWM0_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18)
|
||||
#define GPIO_PWM0_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19)
|
||||
#define GPIO_PWM0_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5)
|
||||
#define GPIO_PWM0_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0)
|
||||
#define GPIO_PWM0_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13)
|
||||
#define GPIO_PWM1_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1)
|
||||
#define GPIO_PWM1_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1)
|
||||
#define GPIO_PWM1_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12)
|
||||
#define GPIO_PWM1_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24)
|
||||
#define GPIO_PWM1_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19)
|
||||
#define GPIO_PWM1_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15)
|
||||
#define GPIO_PWM1_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12)
|
||||
#define GPIO_PWM1_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20)
|
||||
#define GPIO_PWM1_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1)
|
||||
#define GPIO_PWM2_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2)
|
||||
#define GPIO_PWM2_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13)
|
||||
#define GPIO_PWM2_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25)
|
||||
#define GPIO_PWM2_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4)
|
||||
#define GPIO_PWM2_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20)
|
||||
#define GPIO_PWM2_L_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30)
|
||||
#define GPIO_PWM2_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
|
||||
#define GPIO_PWM2_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2)
|
||||
#define GPIO_PWM2_L_4 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16)
|
||||
#define GPIO_PWM3_H_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14)
|
||||
#define GPIO_PWM3_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7)
|
||||
#define GPIO_PWM3_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14)
|
||||
#define GPIO_PWM3_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21)
|
||||
#define GPIO_PWM3_H_5 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17)
|
||||
#define GPIO_PWM3_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22)
|
||||
#define GPIO_PWM3_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3)
|
||||
#define GPIO_PWM3_L_3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15)
|
||||
|
||||
/* Static Memory Controller (SMC) */
|
||||
|
||||
#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN18)
|
||||
#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN19)
|
||||
#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN20)
|
||||
#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN21)
|
||||
#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN22)
|
||||
#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN23)
|
||||
#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN24)
|
||||
#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN25)
|
||||
#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN26)
|
||||
#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN27)
|
||||
#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN28)
|
||||
#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN29)
|
||||
#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN30)
|
||||
#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN31)
|
||||
#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN18)
|
||||
#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN19)
|
||||
#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN20)
|
||||
#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN0)
|
||||
#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN1)
|
||||
#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN23)
|
||||
#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN24)
|
||||
#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN16)
|
||||
#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN17)
|
||||
#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN25)
|
||||
#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN0)
|
||||
#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN1)
|
||||
#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN2)
|
||||
#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN3)
|
||||
#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN4)
|
||||
#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN5)
|
||||
#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN6)
|
||||
#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN7)
|
||||
#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN16)
|
||||
#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN17)
|
||||
#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN9)
|
||||
#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN10)
|
||||
#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN14)
|
||||
#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN15)
|
||||
#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN22)
|
||||
#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN12)
|
||||
#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN11)
|
||||
#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN13)
|
||||
#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN8)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) */
|
||||
|
||||
#define GPIO_SPI0_MISO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN12)
|
||||
#define GPIO_SPI0_MOSI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN13)
|
||||
#define GPIO_SPI0_NPCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN11)
|
||||
#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31)
|
||||
#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14)
|
||||
#define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN9)
|
||||
#define GPIO_SPI0_NPCS1_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4)
|
||||
#define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10)
|
||||
#define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30)
|
||||
#define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
|
||||
#define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
|
||||
#define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3)
|
||||
#define GPIO_SPI0_NPCS3_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5)
|
||||
#define GPIO_SPI0_SPCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN14)
|
||||
|
||||
/* Synchronous Serial Controller (SSC) */
|
||||
|
||||
#define GPIO_SSC_RD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18)
|
||||
#define GPIO_SSC_RF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20)
|
||||
#define GPIO_SSC_RK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19)
|
||||
#define GPIO_SSC_TD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17)
|
||||
#define GPIO_SSC_TF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15)
|
||||
#define GPIO_SSC_TK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16)
|
||||
|
||||
/* Timer/Counters (TC) */
|
||||
|
||||
#define GPIO_TC0_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4)
|
||||
#define GPIO_TC0_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0)
|
||||
#define GPIO_TC0_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1)
|
||||
#define GPIO_TC1_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28)
|
||||
#define GPIO_TC1_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN15)
|
||||
#define GPIO_TC1_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN16)
|
||||
#define GPIO_TC2_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29)
|
||||
#define GPIO_TC2_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26)
|
||||
#define GPIO_TC2_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27)
|
||||
#define GPIO_TC3_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25)
|
||||
#define GPIO_TC3_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23)
|
||||
#define GPIO_TC3_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24)
|
||||
#define GPIO_TC4_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28)
|
||||
#define GPIO_TC4_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26)
|
||||
#define GPIO_TC4_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27)
|
||||
#define GPIO_TC5_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31)
|
||||
#define GPIO_TC5_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29)
|
||||
#define GPIO_TC5_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30)
|
||||
|
||||
/* Two Wire Interface (TWI) */
|
||||
|
||||
#define GPIO_TWI0_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4)
|
||||
#define GPIO_TWI0_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN3)
|
||||
#define GPIO_TWI1_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5)
|
||||
#define GPIO_TWI1_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4)
|
||||
|
||||
/* Universal Asynchronous Receiver Transceiver (UART) */
|
||||
|
||||
#define GPIO_UART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4)
|
||||
#define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5)
|
||||
#define GPIO_UART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1)
|
||||
#define GPIO_UART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0)
|
||||
|
||||
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||||
|
||||
#define GPIO_USART0_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8)
|
||||
#define GPIO_USART0_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN7)
|
||||
#define GPIO_USART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5)
|
||||
#define GPIO_USART0_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN2)
|
||||
#define GPIO_USART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6)
|
||||
|
||||
#define GPIO_USART1_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25)
|
||||
#define GPIO_USART1_DCD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26)
|
||||
#define GPIO_USART1_DSR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28)
|
||||
#define GPIO_USART1_DTR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27)
|
||||
#define GPIO_USART1_RI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN29)
|
||||
|
||||
#define GPIO_USART1_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24)
|
||||
#define GPIO_USART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21)
|
||||
#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
|
||||
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
|
||||
|
||||
/* Segment LCD Controller (SLCDC) */
|
||||
//TODO: add rest of segment pins
|
||||
|
||||
#define GPIO_SLCDC_COM0 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN0)
|
||||
#define GPIO_SLCDC_COM1 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN1)
|
||||
#define GPIO_SLCDC_COM2 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN2)
|
||||
#define GPIO_SLCDC_COM3 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN3)
|
||||
#define GPIO_SLCDC_COM4 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN4)
|
||||
#define GPIO_SLCDC_COM5 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN5)
|
||||
|
||||
#define GPIO_SLCDC_SEG0 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN6)
|
||||
#define GPIO_SLCDC_SEG1 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN7)
|
||||
#define GPIO_SLCDC_SEG2 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN8)
|
||||
#define GPIO_SLCDC_SEG3 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN9)
|
||||
#define GPIO_SLCDC_SEG4 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN10)
|
||||
#define GPIO_SLCDC_SEG5 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN11)
|
||||
#define GPIO_SLCDC_SEG6 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN12)
|
||||
#define GPIO_SLCDC_SEG7 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN13)
|
||||
#define GPIO_SLCDC_SEG8 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN14)
|
||||
#define GPIO_SLCDC_SEG9 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN15)
|
||||
#define GPIO_SLCDC_SEG10 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN16)
|
||||
#define GPIO_SLCDC_SEG11 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN17)
|
||||
#define GPIO_SLCDC_SEG12 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN18)
|
||||
#define GPIO_SLCDC_SEG13 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN19)
|
||||
#define GPIO_SLCDC_SEG14 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN20)
|
||||
#define GPIO_SLCDC_SEG15 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN21)
|
||||
#define GPIO_SLCDC_SEG16 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN22)
|
||||
#define GPIO_SLCDC_SEG17 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN23)
|
||||
#define GPIO_SLCDC_SEG18 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN24)
|
||||
#define GPIO_SLCDC_SEG19 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN25)
|
||||
#define GPIO_SLCDC_SEG20 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN26)
|
||||
#define GPIO_SLCDC_SEG21 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN27)
|
||||
#define GPIO_SLCDC_SEG22 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN28)
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H */
|
||||
182
arch/arm/src/sam34/chip/sam4cm_slcdc.h
Normal file
182
arch/arm/src/sam34/chip/sam4cm_slcdc.h
Normal file
@ -0,0 +1,182 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam4cm_slcdc.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SLCDC_H
|
||||
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SLCDC_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/sam_memorymap.h"
|
||||
|
||||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
|
||||
/* SLCDC register offsets ************************************************************/
|
||||
|
||||
#define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define SAM_SLCDC_MR_OFFSET 0x0004 /* Mode Register */
|
||||
#define SAM_SLCDC_FRR_OFFSET 0x0008 /* Frame Rate Register */
|
||||
#define SAM_SLCDC_DR_OFFSET 0x000C /* Display Register */
|
||||
#define SAM_SLCDC_SR_OFFSET 0x0010 /* Status Register */
|
||||
#define SAM_SLCDC_IER_OFFSET 0x0020 /* Interrupt Enable Register */
|
||||
#define SAM_SLCDC_IDR_OFFSET 0x0024 /* Interrupt Disable Register */
|
||||
#define SAM_SLCDC_IMR_OFFSET 0x0028 /* Interrupt Mask Register */
|
||||
#define SAM_SLCDC_ISR_OFFSET 0x002C /* Interrupt Status Register */
|
||||
#define SAM_SLCDC_SMR0_OFFSET 0x0030 /* Segment Map Register 0 */
|
||||
#define SAM_SLCDC_SMR1_OFFSET 0x0034 /* Segment Map Register 1 */
|
||||
# define SAM_SLCDC_SMR_OFFSET(n) (SAM_SLCDC_SMR0_OFFSET + (n) * 4)
|
||||
#define SAM_SLCDC_WPMR_OFFSET 0x0034 /* Write Protect Mode Register */
|
||||
#define SAM_SLCDC_WPSR_OFFSET 0x0034 /* Write Protect Status Register */
|
||||
|
||||
#define SAM_SLCDC_LMEMR_OFFSET(com) (0x200 + (com)*8 + 0x0)
|
||||
#define SAM_SLCDC_MMEMR_OFFSET(com) (0x200 + (com)*8 + 0x4)
|
||||
|
||||
/* SLCDC register adresses ***********************************************************/
|
||||
|
||||
#define SAM_SLCDC_CR (SAM_SLCDC_BASE + SAM_SLCDC_CR_OFFSET)
|
||||
#define SAM_SLCDC_MR (SAM_SLCDC_BASE + SAM_SLCDC_MR_OFFSET)
|
||||
#define SAM_SLCDC_FRR (SAM_SLCDC_BASE + SAM_SLCDC_FRR_OFFSET)
|
||||
#define SAM_SLCDC_DR (SAM_SLCDC_BASE + SAM_SLCDC_DR_OFFSET)
|
||||
#define SAM_SLCDC_SR (SAM_SLCDC_BASE + SAM_SLCDC_SR_OFFSET)
|
||||
#define SAM_SLCDC_IER (SAM_SLCDC_BASE + SAM_SLCDC_IER_OFFSET)
|
||||
#define SAM_SLCDC_IDR (SAM_SLCDC_BASE + SAM_SLCDC_IDR_OFFSET)
|
||||
#define SAM_SLCDC_IMR (SAM_SLCDC_BASE + SAM_SLCDC_IMR_OFFSET)
|
||||
#define SAM_SLCDC_ISR (SAM_SLCDC_BASE + SAM_SLCDC_ISR_OFFSET)
|
||||
#define SAM_SLCDC_SMR0 (SAM_SLCDC_BASE + SAM_SLCDC_SMR0_OFFSET)
|
||||
#define SAM_SLCDC_SMR1 (SAM_SLCDC_BASE + SAM_SLCDC_SMR1_OFFSET)
|
||||
# define SAM_SLCDC_SMR(n) (SAM_SLCDC_BASE + SAM_SLCDC_SMR_OFFSET(n))
|
||||
#define SAM_SLCDC_WPMR (SAM_SLCDC_BASE + SAM_SLCDC_WPMR_OFFSET)
|
||||
#define SAM_SLCDC_WPSR (SAM_SLCDC_BASE + SAM_SLCDC_WPSR_OFFSET)
|
||||
|
||||
#define SAM_SLCDC_LMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_LMEMR_OFFSET(com))
|
||||
#define SAM_SLCDC_MMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_MMEMR_OFFSET(com))
|
||||
|
||||
/* SLCDC register bit definitions ****************************************************/
|
||||
|
||||
/* Control Register */
|
||||
|
||||
#define SLCDC_CR_LCDEN (1 << 0)
|
||||
#define SLCDC_CR_LCDDIS (1 << 1)
|
||||
#define SLCDC_CR_SWRST (1 << 3)
|
||||
|
||||
/* Mode Register */
|
||||
|
||||
#define SLCDC_MR_COMSEL(N) (((N) - 1) << 0)
|
||||
#define SLCDC_MR_SEGSEL(N) (((N) - 1) << 8)
|
||||
|
||||
#define SLCDC_MR_BUFFTIME_OFFSET (16)
|
||||
#define SLCDC_MR_BUFFTIME_MASK (0xF << SLCDC_MR_BUFFTIME_OFFSET)
|
||||
# define SLCDC_MR_BUFFTIME_OFF (0 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 0% of SCLK period */
|
||||
# define SLCDC_MR_BUFFTIME_X2_SCLK (1 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 2 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_X4_SCLK (2 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 4 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_X8_SCLK (3 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 8 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_X16_SCLK (4 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 16 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_X32_SCLK (5 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 32 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_X64_SCLK (6 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 64 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_X128_SCLK (7 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 128 periods of SCLK clock */
|
||||
# define SLCDC_MR_BUFFTIME_PERCENT_50 (8 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 50% of SCLK period */
|
||||
# define SLCDC_MR_BUFFTIME_PERCENT_100 (9 << SLCDC_MR_BUFFTIME_OFFSET) /* Nominal drive time is 100% of SCLK period */
|
||||
|
||||
#define SLCDC_MR_BIAS_OFFSET (20)
|
||||
#define SLCDC_MR_BIAS_MASK (0x3 << SLCDC_MR_BIAS_OFFSET)
|
||||
# define SLCDC_MR_BIAS_STATIC (0 << SLCDC_MR_BIAS_OFFSET) /* Static */
|
||||
# define SLCDC_MR_BIAS_1_2 (1 << SLCDC_MR_BIAS_OFFSET) /* Bias 1/2 */
|
||||
# define SLCDC_MR_BIAS_1_3 (2 << SLCDC_MR_BIAS_OFFSET) /* Bias 1/3 */
|
||||
|
||||
#define SLCD_MR_LPMODE_LOW_POWER (1 << 24)
|
||||
|
||||
/* Frame Rate Register */
|
||||
|
||||
#define SLCDC_FRR_PRESC_OFFSET (0)
|
||||
#define SLCDC_FRR_PRESC_MASK (0x7 << SLCDC_FRR_PRESC_OFFSET)
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV8 (0x0 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 8 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV16 (0x1 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 16 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV32 (0x2 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 32 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV64 (0x3 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 64 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV128 (0x4 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 128 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV256 (0x5 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 256 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV512 (0x6 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 512 */
|
||||
# define SLCDC_FRR_PRESC_SCLK_DIV1024 (0x7 << SLCDC_FRR_PRESC_OFFSET) /* Slow clock is divided by 1024 */
|
||||
|
||||
#define SLCDC_FRR_DIV_OFFSET (8)
|
||||
#define SLCDC_FRR_DIV_MASK (0x7 << SLCDC_FRR_DIV_OFFSET)
|
||||
# define SLCDC_FRR_DIV(N) (((N) - 1) << SLCDC_FRR_DIV_OFFSET) /* Clock output from prescaler is divided by N */
|
||||
|
||||
/* Display Register */
|
||||
|
||||
#define SLCDC_DR_DISPMODE_OFFSET (0)
|
||||
#define SLCDC_DR_DISPMODE_MASK (0x7 << SLCDC_DR_DISPMODE_OFFSET)
|
||||
# define SLCDC_DR_DISPMODE_NORMAL (0x0 << SLCDC_DR_DISPMODE_OFFSET) /* Latched data are displayed */
|
||||
# define SLCDC_DR_DISPMODE_FORCE_OFF (0x1 << SLCDC_DR_DISPMODE_OFFSET) /* All pixels are invisible. (The SLCDC memory is unchanged.) */
|
||||
# define SLCDC_DR_DISPMODE_FORCE_ON (0x2 << SLCDC_DR_DISPMODE_OFFSET) /* All pixels are visible. (The SLCDC memory is unchanged.) */
|
||||
# define SLCDC_DR_DISPMODE_BLINKING (0x3 << SLCDC_DR_DISPMODE_OFFSET) /* All pixels are alternately turned off to the predefined state in SLCDC memory at LCDBLKFREQ frequency */
|
||||
# define SLCDC_DR_DISPMODE_INVERTED (0x4 << SLCDC_DR_DISPMODE_OFFSET) /* All pixels are set in the inverted state as defined in SLCDC memory */
|
||||
# define SLCDC_DR_DISPMODE_INVERTED_BLINK (0x5 << SLCDC_DR_DISPMODE_OFFSET) /* All pixels are alternately turned off to the predefined opposite state in SLCDC memory at LCDBLKFREQ frequency */
|
||||
# define SLCDC_DR_DISPMODE_USER_BUFFER_LOAD (0x6 << SLCDC_DR_DISPMODE_OFFSET) /* Blocks the automatic transfer from User Buffer to Display Buffer */
|
||||
# define SLCDC_DR_DISPMODE_BUFFERS_SWAP (0x7 << SLCDC_DR_DISPMODE_OFFSET) /* All pixels are alternatively assigned to the state defined in the User Buffer, then to the state defined in the Display Buffer at LCDBLKFREQ frequency */
|
||||
|
||||
#define SLCDC_DR_LCDBLKFREQ(F) ((F) << 8) /* Blinking frequency = Frame Frequency/F */
|
||||
|
||||
/* Status Register */
|
||||
|
||||
#define SLCDC_SR_ENA (1 << 0) /* The SLCDC is enabled/disabled */
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
|
||||
#define SLCDC_IER_ENDFRAME (1 << 0) /* End of Frame Interrupt Enable */
|
||||
#define SLCDC_IER_DIS (1 << 2) /* Enables the "Disable" interrupt */
|
||||
|
||||
/* Interrupt Disable Register */
|
||||
|
||||
#define SLCDC_IDR_ENDFRAME (1 << 0) /* End of Frame Interrupt Disable */
|
||||
#define SLCDC_IDR_DIS (1 << 2) /* Disables the "Disable" interrupt */
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
|
||||
#define SLCDC_IMR_ENDFRAME (1 << 0) /* End of Frame Interrupt mask (0 - disable, 1 - enable) */
|
||||
#define SLCDC_IMR_DIS (1 << 2) /* The "Disable" interrupt mask (0 - disable, 1 - enable) */
|
||||
|
||||
/* Interrupt Status Register */
|
||||
|
||||
#define SLCDC_ISR_ENDFRAME (1 << 0) /* End of Frame Interrupt occurred */
|
||||
#define SLCDC_ISR_DIS (1 << 2) /* The "Disable" interrupt occurred */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SLCDC_H */
|
||||
222
arch/arm/src/sam34/chip/sam4cm_supc.h
Normal file
222
arch/arm/src/sam34/chip/sam4cm_supc.h
Normal file
@ -0,0 +1,222 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam4cm_supc.h
|
||||
* Supply Controller (SUPC) definitions for the SAM4CM
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SUPC_H
|
||||
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SUPC_H
|
||||
|
||||
/****************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/sam_memorymap.h"
|
||||
|
||||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
|
||||
/* SUPC register offsets ****************************************************************/
|
||||
|
||||
#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
|
||||
#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
|
||||
#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */
|
||||
#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */
|
||||
#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
|
||||
#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
|
||||
|
||||
/* SUPC register adresses ***************************************************************/
|
||||
|
||||
#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
|
||||
#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
|
||||
#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET)
|
||||
#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET)
|
||||
#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET)
|
||||
#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET)
|
||||
|
||||
/* SUPC register bit definitions ********************************************************/
|
||||
/* Supply Controller Control Register */
|
||||
|
||||
#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */
|
||||
#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */
|
||||
#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
|
||||
#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT)
|
||||
# define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT)
|
||||
|
||||
/* Supply Controller Supply Monitor Mode Register */
|
||||
|
||||
#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */
|
||||
#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT)
|
||||
# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */
|
||||
# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */
|
||||
# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */
|
||||
# define SUPC_SMMR_SMTH_2p0V (3 << SUPC_SMMR_SMTH_SHIFT) /* 1.91 < 1.96 < 2.01 */
|
||||
# define SUPC_SMMR_SMTH_2p1V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.03 < 2.08 < 2.13 */
|
||||
# define SUPC_SMMR_SMTH_2p2V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.15 < 2.2 < 2.23 */
|
||||
# define SUPC_SMMR_SMTH_2p3V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.26 < 2.32 < 2.38 */
|
||||
# define SUPC_SMMR_SMTH_2p4V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.38 < 2.44 < 2.50 */
|
||||
# define SUPC_SMMR_SMTH_2p6V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.50 < 2.56 < 2.62 */
|
||||
# define SUPC_SMMR_SMTH_2p7V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.61 < 2.68 < 2.75 */
|
||||
# define SUPC_SMMR_SMTH_2p8V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.73 < 2.8 < 2.87 */
|
||||
# define SUPC_SMMR_SMTH_2p9V (11 << SUPC_SMMR_SMTH_SHIFT) /* 2.85 < 2.92 < 2.99 */
|
||||
# define SUPC_SMMR_SMTH_3p0V (12 << SUPC_SMMR_SMTH_SHIFT) /* 2.96 < 3.04 < 3.12 */
|
||||
# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */
|
||||
# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */
|
||||
# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */
|
||||
|
||||
#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */
|
||||
#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT)
|
||||
# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */
|
||||
# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */
|
||||
# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
|
||||
# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
|
||||
# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
|
||||
#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */
|
||||
#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */
|
||||
|
||||
/* Supply Controller Mode Register */
|
||||
|
||||
#define SUPC_MR_
|
||||
#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
|
||||
#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */
|
||||
#endif
|
||||
|
||||
#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */
|
||||
#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */
|
||||
#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT)
|
||||
# define SUPR_MR_KEY (0xa5 << SUPC_MR_KEY_SHIFT)
|
||||
|
||||
/* Supply Controller Wake Up Mode Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */
|
||||
#endif
|
||||
|
||||
#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */
|
||||
#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */
|
||||
#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */
|
||||
# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */
|
||||
# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */
|
||||
# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT)
|
||||
# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */
|
||||
# define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */
|
||||
# define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */
|
||||
# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */
|
||||
# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */
|
||||
# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
|
||||
#endif
|
||||
|
||||
#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
|
||||
#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
|
||||
# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
|
||||
# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */
|
||||
# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */
|
||||
# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */
|
||||
# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
|
||||
# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */
|
||||
# define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT)
|
||||
# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */
|
||||
# define SUPC_WUMR_LPDBC_2_RTCOUT0 (1 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 2 RTCOUT0 */
|
||||
# define SUPC_WUMR_LPDBC_3_RTCOUT0 (2 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 3 RTCOUT0 */
|
||||
# define SUPC_WUMR_LPDBC_4_RTCOUT0 (3 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 4 RTCOUT0 */
|
||||
# define SUPC_WUMR_LPDBC_5_RTCOUT0 (4 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 5 RTCOUT0 */
|
||||
# define SUPC_WUMR_LPDBC_6_RTCOUT0 (5 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 6 RTCOUT0 */
|
||||
# define SUPC_WUMR_LPDBC_7_RTCOUT0 (6 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 7 RTCOUT0 */
|
||||
# define SUPC_WUMR_LPDBC_8_RTCOUT0 (7 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 8 RTCOUT0 */
|
||||
#endif
|
||||
|
||||
/* System Controller Wake Up Inputs Register */
|
||||
|
||||
#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */
|
||||
#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT)
|
||||
# define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT)
|
||||
#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */
|
||||
#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT)
|
||||
# define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT)
|
||||
|
||||
/* Supply Controller Status Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */
|
||||
#endif
|
||||
|
||||
#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */
|
||||
#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */
|
||||
#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */
|
||||
#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */
|
||||
#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */
|
||||
#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
|
||||
#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */
|
||||
# define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */
|
||||
#endif
|
||||
|
||||
#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */
|
||||
#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SUPC_H */
|
||||
101
arch/arm/src/sam34/chip/sam4cm_vectors.h
Normal file
101
arch/arm/src/sam34/chip/sam4cm_vectors.h
Normal file
@ -0,0 +1,101 @@
|
||||
/************************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam4cm_vectors.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************/
|
||||
|
||||
/************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
/* This file is included by sam_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
|
||||
* sam_vectors.S will defined the VECTOR in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
/* If the common ARMv7-M vector handling is used, then all it needs is the following
|
||||
* definition that provides the number of supported vectors.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
/* Reserve 35 interrupt table entries for I/O interrupts. */
|
||||
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 35
|
||||
|
||||
#else
|
||||
VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */
|
||||
VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */
|
||||
VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */
|
||||
VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */
|
||||
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */
|
||||
VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */
|
||||
VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
|
||||
UNUSED(SAM_IRQ_RESERVED_7) /* Vector 16+7: Reserved */
|
||||
VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */
|
||||
UNUSED(SAM_IRQ_RESERVED_9) /* Vector 16+9: Reserved */
|
||||
//VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+10: Static Memory Controller */
|
||||
VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */
|
||||
VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */
|
||||
UNUSED(SAM_IRQ_RESERVED_13) /* Vector 16+13: Reserved */
|
||||
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */
|
||||
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */
|
||||
VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+16: USART 2 */
|
||||
VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+17: USART 3 */
|
||||
UNUSED(SAM_IRQ_RESERVED_18) /* Vector 16+18: Reserved */
|
||||
VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */
|
||||
VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */
|
||||
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+21: Serial Peripheral Interface */
|
||||
UNUSED(SAM_IRQ_RESERVED_22) /* Vector 16+22: Reserved */
|
||||
VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */
|
||||
VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */
|
||||
VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+25: Timer Counter 2 */
|
||||
VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+26: Timer Counter 3 */
|
||||
VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+27: Timer Counter 4 */
|
||||
VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+28: Timer Counter 5 */
|
||||
VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+29: Analog To Digital Converter */
|
||||
VECTOR(sam_arm, SAM_IRQ_ARM) /* Vector 16+30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
|
||||
VECTOR(sam_ipc0, SAM_IRQ_IPC0) /* Vector 16+31: Interprocessor communication 0 */
|
||||
VECTOR(sam_slcdc, SAM_IRQ_SLCDC) /* Vector 16+32: Segment LCD Controller */
|
||||
VECTOR(sam_trng, SAM_IRQ_TRNG) /* Vector 16+33: True Random Generator */
|
||||
VECTOR(sam_icm, SAM_IRQ_ICM) /* Vector 16+34: Integrity Check Module */
|
||||
VECTOR(sam_cpkcc, SAM_IRQ_CPKCC) /* Vector 16+35: Classical Public Key Cryptography Controller */
|
||||
VECTOR(sam_aes, SAM_IRQ_AES) /* Vector 16+36: Advanced Enhanced Standard */
|
||||
VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+37: Parallel I/O Controller C */
|
||||
VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+38: Universal Asynchronous Receiver Transmitter 1 */
|
||||
VECTOR(sam_ipc1, SAM_IRQ_IPC1) /* Vector 16+39: Interprocessor communication 1 */
|
||||
UNUSED(SAM_IRQ_RESERVED_40) /* Vector 16+40: Reserved */
|
||||
VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+41: Pulse Width Modulation */
|
||||
//VECTOR(sam_sram, SAM_IRQ_SRAM) /* Vector 16+42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
|
||||
//VECTOR(sam_smc1, SAM_IRQ_SMC1) /* Vector 16+43: Static Memory Controller 1 */
|
||||
#endif
|
||||
@ -47,6 +47,8 @@
|
||||
# include "chip/sam3u_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "chip/sam3x_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "chip/sam4cm_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -47,6 +47,8 @@
|
||||
# include "chip/sam3u_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "chip/sam3x_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "chip/sam4cm_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam_pmc.h
|
||||
* Power Management Controller (PMC) for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
|
||||
* Power Management Controller (PMC) for the SAM3U, SAM3X, SAM3A, SAM4CM, SAM4E, and
|
||||
* SAM4S
|
||||
*
|
||||
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@ -57,7 +58,8 @@
|
||||
#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
|
||||
/* 0x000c: Reserved */
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */
|
||||
# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */
|
||||
# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */
|
||||
@ -76,7 +78,7 @@
|
||||
#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
|
||||
#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */
|
||||
#endif
|
||||
/* 0x002c: Reserved (SAM3U)*/
|
||||
@ -106,7 +108,8 @@
|
||||
#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
/* 0x00ec-0x00fc Reserved */
|
||||
# define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */
|
||||
# define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */
|
||||
@ -132,7 +135,8 @@
|
||||
#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET)
|
||||
# define SAM_PMC_PCDR0 (SAM_PMC_BASE+SAM_PMC_PCDR0_OFFSET)
|
||||
# define SAM_PMC_PCSR0 (SAM_PMC_BASE+SAM_PMC_PCSR0_OFFSET)
|
||||
@ -151,7 +155,7 @@
|
||||
#define SAM_PMC_CKGR_MCFR (SAM_PMC_BASE+SAM_PMC_CKGR_MCFR_OFFSET)
|
||||
#define SAM_PMC_CKGR_PLLAR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLAR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define SAM_PMC_CKGR_PLLBR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLBR_OFFSET)
|
||||
#endif
|
||||
|
||||
@ -176,7 +180,8 @@
|
||||
#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET)
|
||||
# define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET)
|
||||
# define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET)
|
||||
@ -213,6 +218,12 @@
|
||||
#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */
|
||||
#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define PMC_CPCK (1 << 16)
|
||||
# define PMC_CPBMCK (1 << 17)
|
||||
# define PMC_CPKEY (0xa << 20)
|
||||
#endif
|
||||
|
||||
/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
|
||||
* Peripheral Clock Status Register common bit-field definitions.
|
||||
*/
|
||||
@ -317,7 +328,7 @@
|
||||
|
||||
/* PLLB Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_CKGR_PLLBR_DIV_SHIFT (0) /* Bits 0-7: Divider */
|
||||
# define PMC_CKGR_PLLBR_DIV_MASK (0xff << PMC_CKGR_PLLBR_DIV_SHIFT)
|
||||
# define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */
|
||||
@ -327,6 +338,13 @@
|
||||
# define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT)
|
||||
# define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
|
||||
# define PMC_CKGR_PLLBR_MUL_MASK (0x7ff << PMC_CKGR_PLLBR_MUL_SHIFT)
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define PMC_CKGR_PLLBR_SRCB_SHIFT (29)
|
||||
# define PMC_CKGR_PLLBR_SRCB_MASK (1 << PMC_CKGR_PLLBR_SRCB_SHIFT)
|
||||
# define PMC_CKGR_PLLBR_SRCB_MAIN (0 << PMC_CKGR_PLLBR_SRCB_SHIFT)
|
||||
# define PMC_CKGR_PLLBR_SRCB_PLLA (1 << PMC_CKGR_PLLBR_SRCB_SHIFT)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* USB Clock Register PMC_USB */
|
||||
@ -350,12 +368,12 @@
|
||||
# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */
|
||||
# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
|
||||
# endif
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
|
||||
#endif
|
||||
|
||||
#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */
|
||||
#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT)
|
||||
@ -373,13 +391,26 @@
|
||||
# define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_MCKR_PLLBDIV2 (1 << 13) /* Bit 13: PLLB Divider */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define PMC_MCKR_UPLLDIV2 (1 << 13) /* Bit 13: UPLL Divider */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define PMC_MCKR_CPCSS_SHIFT (16)
|
||||
# define PMC_MCKR_CPCSS_MASK (0x7 << PMC_MCKR_CPCSS_SHIFT)
|
||||
# define PMC_MCKR_CPCSS_SLOW (0 << PMC_MCKR_CPCSS_SHIFT) /* Slow Clock */
|
||||
# define PMC_MCKR_CCPSS_MAIN (1 << PMC_MCKR_CPCSS_SHIFT) /* Main Clock */
|
||||
# define PMC_MCKR_CCPSS_PLLA (2 << PMC_MCKR_CPCSS_SHIFT) /* PLLA Clock */
|
||||
# define PMC_MCKR_CCPSS_PLLB (3 << PMC_MCKR_CPCSS_SHIFT) /* PLLB Clock */
|
||||
# define PMC_MCKR_CCPSS_MCK (4 << PMC_MCKR_CPCSS_SHIFT) /* Master Clock */
|
||||
# define PMC_MCKR_CPPRES_SHIFT (20)
|
||||
# define PMC_MCKR_CPPRES_MASK (0xF << PMC_MCKR_CPPRES_SHIFT)
|
||||
# define PMC_MCKR_CPPRES(D) (((D) - 1) << PMC_MCKR_CPPRES_SHIFT)
|
||||
#endif
|
||||
|
||||
/* PMC Programmable Clock Register (0,1,2) */
|
||||
|
||||
#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
|
||||
@ -414,7 +445,7 @@
|
||||
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
|
||||
#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# define PMC_INT_LOCKB (1 << 2) /* Bit 2: PLL B Lock Interrupt */
|
||||
#endif
|
||||
|
||||
|
||||
@ -56,12 +56,20 @@
|
||||
#define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */
|
||||
#define SAM_RSTC_MR_OFFSET 0x08 /* Mode Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define SAM_RSTC_CPMR_OFFSET 0x0c /* Coprocessor Mode Register */
|
||||
#endif
|
||||
|
||||
/* RSTC register addresses **************************************************************/
|
||||
|
||||
#define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET)
|
||||
#define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET)
|
||||
#define SAM_RSTC_MR (SAM_RSTC_BASE+SAM_RSTC_MR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define SAM_RSTC_CPMR (SAM_RSTC_BASE+SAM_RSTC_CPMR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* RSTC register bit definitions ********************************************************/
|
||||
|
||||
/* Reset Controller Control Register */
|
||||
@ -97,6 +105,14 @@
|
||||
#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
|
||||
# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
/* Coprocessor Mode Register */
|
||||
|
||||
# define RSTC_CPMR_CPROCEN (1 << 0) /* Coprocessor (second processor) Enable */
|
||||
# define RSTC_CPMR_CPEREN (1 << 4) /* Coprocessor Peripheral Enable */
|
||||
# define RSTC_CPMR_CPKEY (0x5a << 24) /* Key */
|
||||
#endif
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
@ -83,7 +83,8 @@
|
||||
#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT)
|
||||
# define SUPC_SMMR_SMTH(n) ((uint32_t)(n) << SUPC_SMMR_SMTH_SHIFT)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */
|
||||
# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */
|
||||
# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */
|
||||
@ -132,6 +133,35 @@
|
||||
|
||||
/* Supply Controller Mode Register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
|
||||
#define SUPC_MR_LCDVROUT_SHIFT (0)
|
||||
#define SUPC_MR_LCDVROUT_MASK (15 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p92V (0 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p85V (1 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p77V (2 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p70V (3 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p63V (4 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p55V (5 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p48V (6 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_2p41V (7 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p51V (8 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p44V (9 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p36V (10 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p29V (11 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p22V (12 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p14V (13 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p07V (14 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
# define SUPC_MR_LCDVROUT_3p00V (15 << SUPC_MR_LCDVROUT_SHIFT)
|
||||
|
||||
#define SUPC_MR_LCDMODE_SHIFT (4)
|
||||
#define SUPC_MR_LCDMODE_MASK (3 << SUPC_MR_LCDMODE_SHIFT)
|
||||
# define SUPC_MR_LCDMODE_LCDOFF (0 << SUPC_MR_LCDMODE_SHIFT) /* The internal supply source and the external supply source are both deselected */
|
||||
# define SUPC_MR_LCDMODE_LCDON_EXTVR (2 << SUPC_MR_LCDMODE_SHIFT) /* The external supply source for LCD (VDDLCD) is selected (the LCD voltage regulator is in Hi-Z Mode) */
|
||||
# define SUPC_MR_LCDMODE_LCDON_INVR (3 << SUPC_MR_LCDMODE_SHIFT) /* The internal supply source for LCD (the LCD Voltage Regulator) is selected (Active Mode) */
|
||||
|
||||
#endif
|
||||
|
||||
#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
|
||||
#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
|
||||
|
||||
@ -224,6 +254,10 @@
|
||||
#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
|
||||
#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define SUPC_SR_LCDS (1 << 8) /* Bit 8: LCD Status */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */
|
||||
|
||||
207
arch/arm/src/sam34/sam4cm_gpio.h
Normal file
207
arch/arm/src/sam34/sam4cm_gpio.h
Normal file
@ -0,0 +1,207 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/sam4cm_gpio.h
|
||||
* General Purpose Input/Output (GPIO) definitions for the SAM4CM
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_GPIO_H
|
||||
#define __ARCH_ARM_SRC_SAM34_SAM4CM_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#define GPIO_HAVE_PULLDOWN 1
|
||||
#define GPIO_HAVE_PERIPHCD 1
|
||||
#define GPIO_HAVE_SCHMITT 1
|
||||
#undef GPIO_HAVE_DELAYR
|
||||
|
||||
/* Bit-encoded input to sam_configgpio() ********************************************/
|
||||
|
||||
/* 32-bit Encoding:
|
||||
*
|
||||
* MMMC CCCC III. VPPB BBBB
|
||||
*/
|
||||
|
||||
/* Input/Output mode:
|
||||
*
|
||||
* MMM. .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (17) /* Bits 17-19: GPIO mode */
|
||||
#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */
|
||||
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */
|
||||
# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
|
||||
# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
|
||||
# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */
|
||||
# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */
|
||||
|
||||
/* These bits set the configuration of the pin:
|
||||
* NOTE: No definitions for parallel capture mode
|
||||
*
|
||||
* ...C CCCC .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_CFG_SHIFT (12) /* Bits 12-16: GPIO configuration bits */
|
||||
#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT)
|
||||
# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
|
||||
# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
|
||||
# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
|
||||
# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
|
||||
# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
|
||||
# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
|
||||
|
||||
/* Additional interrupt modes:
|
||||
*
|
||||
* .... .... III. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_INT_SHIFT (9) /* Bits 9-11: GPIO interrupt bits */
|
||||
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
|
||||
# define _GIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
|
||||
# define _GPIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
|
||||
# define _GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
|
||||
# define _GPIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
|
||||
# define _GPIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
|
||||
|
||||
# define GPIO_INT_HIGHLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH)
|
||||
# define GPIO_INT_LOWLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_FL)
|
||||
# define GPIO_INT_RISING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_RH)
|
||||
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
|
||||
# define GPIO_INT_BOTHEDGES (0)
|
||||
|
||||
/* If the pin is an GPIO output, then this identifies the initial output value:
|
||||
*
|
||||
* .... .... .... V... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Initial value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
*
|
||||
* .... .... .... .PP. ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
|
||||
#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
*
|
||||
* .... .... .... ...B BBBB
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/* Must be big enough to hold the 32-bit encoding */
|
||||
|
||||
typedef uint32_t gpio_pinset_t;
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H */
|
||||
169
arch/arm/src/sam34/sam4cm_periphclks.h
Normal file
169
arch/arm/src/sam34/sam4cm_periphclks.h
Normal file
@ -0,0 +1,169 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/sam4cm_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAM34_SAM4CM_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/irq.h>
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helper macros */
|
||||
|
||||
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
|
||||
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
|
||||
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
|
||||
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
|
||||
|
||||
#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC)
|
||||
#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC)
|
||||
#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC)
|
||||
#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT)
|
||||
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
|
||||
#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC)
|
||||
#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0)
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
|
||||
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
|
||||
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
|
||||
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
|
||||
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
|
||||
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
|
||||
#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2)
|
||||
#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3)
|
||||
#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4)
|
||||
#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5)
|
||||
#define sam_adc_enableclk() sam_enableperiph0(SAM_PID_ADC)
|
||||
#define sam_arm_enableclk() sam_enableperiph0(SAM_PID_ARM)
|
||||
#define sam_ipc0_enableclk() sam_enableperiph0(SAM_PID_IPC0)
|
||||
#define sam_slcdc_enableclk() sam_enableperiph1(SAM_PID_SLCDC)
|
||||
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
|
||||
#define sam_icm_enableclk() sam_enableperiph1(SAM_PID_ICM)
|
||||
#define sam_cpkcc_enableclk() sam_enableperiph1(SAM_PID_CPKCC)
|
||||
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
|
||||
#define sam_pioc_enableclk() sam_enableperiph1(SAM_PID_PIOC)
|
||||
#define sam_uart1_enableclk() sam_enableperiph1(SAM_PID_UART1)
|
||||
#define sam_ipc1_enableclk() sam_enableperiph1(SAM_PID_IPC1)
|
||||
#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
|
||||
#define sam_sram_enableclk() sam_enableperiph1(SAM_PID_SRAM)
|
||||
#define sam_smc1_enableclk() sam_enableperiph1(SAM_PID_SMC1)
|
||||
|
||||
#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC)
|
||||
#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC)
|
||||
#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC)
|
||||
#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT)
|
||||
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
|
||||
#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC)
|
||||
#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0)
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
|
||||
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
|
||||
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
|
||||
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
|
||||
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
|
||||
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
|
||||
#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2)
|
||||
#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3)
|
||||
#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4)
|
||||
#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5)
|
||||
#define sam_adc_disableclk() sam_disableperiph0(SAM_PID_ADC)
|
||||
#define sam_arm_disableclk() sam_disableperiph0(SAM_PID_ARM)
|
||||
#define sam_ipc0_disableclk() sam_disableperiph0(SAM_PID_IPC0)
|
||||
#define sam_slcdc_disableclk() sam_disableperiph1(SAM_PID_SLCDC)
|
||||
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
|
||||
#define sam_icm_disableclk() sam_disableperiph1(SAM_PID_ICM)
|
||||
#define sam_cpkcc_disableclk() sam_disableperiph1(SAM_PID_CPKCC)
|
||||
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
|
||||
#define sam_pioc_disableclk() sam_disableperiph1(SAM_PID_PIOC)
|
||||
#define sam_uart1_disableclk() sam_disableperiph1(SAM_PID_UART1)
|
||||
#define sam_ipc1_disableclk() sam_disableperiph1(SAM_PID_IPC1)
|
||||
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
|
||||
#define sam_sram_disableclk() sam_disableperiph1(SAM_PID_SRAM)
|
||||
#define sam_smc1_disableclk() sam_disableperiph1(SAM_PID_SMC1)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H */
|
||||
102
arch/arm/src/sam34/sam4cm_supc.c
Normal file
102
arch/arm/src/sam34/sam4cm_supc.c
Normal file
@ -0,0 +1,102 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sam34/sam4cm_supc.c
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/sam_supc.h"
|
||||
|
||||
#include "sam4cm_supc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t supc_get_slcd_power_mode(void)
|
||||
{
|
||||
return getreg32(SAM_SUPC_MR) & SUPC_MR_LCDMODE_MASK;
|
||||
}
|
||||
|
||||
void supc_set_slcd_power_mode(uint32_t mode)
|
||||
{
|
||||
uint32_t regval = getreg32(SAM_SUPC_MR);
|
||||
regval &= ~SUPC_MR_LCDMODE_MASK;
|
||||
regval |= SUPC_MR_KEY | mode;
|
||||
putreg32(regval, SAM_SUPC_MR);
|
||||
|
||||
if (mode == SUPC_MR_LCDMODE_LCDOFF)
|
||||
{
|
||||
while(getreg32(SAM_SUPC_SR) & SUPC_SR_LCDS);
|
||||
}
|
||||
else
|
||||
{
|
||||
while(!(getreg32(SAM_SUPC_SR) & SUPC_SR_LCDS));
|
||||
}
|
||||
}
|
||||
|
||||
void supc_set_slcd_ldo_output(uint32_t vrout)
|
||||
{
|
||||
uint32_t regval = getreg32(SAM_SUPC_MR);
|
||||
regval &= ~SUPC_MR_LCDVROUT_MASK;
|
||||
regval |= SUPC_MR_KEY | vrout;
|
||||
putreg32(regval, SAM_SUPC_MR);
|
||||
}
|
||||
84
arch/arm/src/sam34/sam4cm_supc.h
Normal file
84
arch/arm/src/sam34/sam4cm_supc.h
Normal file
@ -0,0 +1,84 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/sam_rtc.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Doiron
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H
|
||||
#define __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
uint32_t supc_get_slcd_power_mode(void);
|
||||
void supc_set_slcd_power_mode(uint32_t mode);
|
||||
void supc_set_slcd_ldo_output(uint32_t vrout);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H */
|
||||
@ -113,7 +113,7 @@
|
||||
* .... .... .... V... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
|
||||
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Initial value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
@ -198,7 +198,7 @@ extern "C"
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -73,6 +73,11 @@
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3X)
|
||||
# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
|
||||
BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
|
||||
BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
|
||||
# define BOARD_CKGR_PLLBR (BOARD_CKGR_PLLBR_DIV | BOARD_CKGR_PLLBR_MUL | \
|
||||
BOARD_CKGR_PLLBR_COUNT | BOARD_CKGR_PLLBR_SRCB)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
|
||||
BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
|
||||
@ -234,10 +239,17 @@ static inline void sam_pmcsetup(void)
|
||||
//putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4CM
|
||||
/* Setup PLLB and wait for LOCKB */
|
||||
|
||||
putreg32(BOARD_CKGR_PLLBR, SAM_PMC_CKGR_PLLBR);
|
||||
sam_pmcwait(PMC_INT_LOCKB);
|
||||
#else
|
||||
/* Setup PLLA and wait for LOCKA */
|
||||
|
||||
putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
|
||||
sam_pmcwait(PMC_INT_LOCKA);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
/* Setup UTMI for USB and wait for LOCKU */
|
||||
|
||||
@ -59,7 +59,7 @@
|
||||
# include "chip/sam3u_pio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_pio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# include "chip/sam4s_pio.h"
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
|
||||
@ -51,6 +51,8 @@
|
||||
# include "sam3u_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "sam3x_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "sam4cm_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "sam4e_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
@ -52,8 +52,8 @@
|
||||
#include "sam_lowputc.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam_uart.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# include "chip/sam4l_usart.h"
|
||||
@ -155,8 +155,8 @@
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
|
||||
# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
# elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
@ -46,6 +46,8 @@
|
||||
# include "sam3u_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "sam3x_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "sam4cm_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "sam4e_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
@ -62,8 +62,8 @@
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam_uart.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# include "chip/sam4l_usart.h"
|
||||
@ -323,8 +323,8 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
|
||||
# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
@ -66,8 +66,8 @@
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# define SAM_SYSTICK_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
|
||||
@ -166,6 +166,8 @@ _vectors:
|
||||
# include "chip/sam3u_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "chip/sam3x_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "chip/sam4cm_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
@ -207,6 +209,8 @@ handlers:
|
||||
# include "chip/sam3u_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "chip/sam3x_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
|
||||
# include "chip/sam4cm_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user