diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h index c2340092a0..a204c1aa78 100644 --- a/arch/arm/src/kinetis/chip.h +++ b/arch/arm/src/kinetis/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,33 +16,34 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_CHIP_H #define __ARCH_ARM_SRC_KINETIS_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the memory map and the chip definitions file. Other chip hardware files - * should then include this file for the proper setup. +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. */ #include #include #include "hardware/kinetis_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* If the common ARMv7-M vector handling logic is used, then it expects the - * following definition in this file that provides the number of supported external - * interrupts which, for this architecture, is provided in the arch/kinetis/chip.h - * header file. + * following definition in this file that provides the number of supported + * external interrupts which, for this architecture, is provided in the + * arch/kinetis/chip.h header file. */ #define ARMV7M_PERIPHERAL_INTERRUPTS KINETIS_IRQ_NEXTINTS diff --git a/arch/arm/src/kinetis/hardware/kinetis_adc.h b/arch/arm/src/kinetis/hardware/kinetis_adc.h index 50bb8480d6..484a9c38a6 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_adc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_adc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_ADC_SC1A_OFFSET 0x0000 /* ADC status and control registers 1 */ #define KINETIS_ADC_SC1B_OFFSET 0x0004 /* ADC status and control registers 1 */ @@ -66,7 +66,7 @@ #define KINETIS_ADC_CLM1_OFFSET 0x0068 /* ADC minus-side general calibration value register */ #define KINETIS_ADC_CLM0_OFFSET 0x006c /* ADC minus-side general calibration value register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_ADC0_SC1A (KINETIS_ADC0_BASE+KINETIS_ADC_SC1A_OFFSET) #define KINETIS_ADC0_SC1B (KINETIS_ADC0_BASE+KINETIS_ADC_SC1B_OFFSET) @@ -130,7 +130,7 @@ #define KINETIS_ADC1_CLM1 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM1_OFFSET) #define KINETIS_ADC1_CLM0 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM0_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* ADC status and control registers 1 */ @@ -166,10 +166,12 @@ # define ADC_SC1_ADCH_VREFSH (29 << ADC_SC1_ADCH_SHIFT) /* VREFSH */ # define ADC_SC1_ADCH_VREFSL (30 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 VREFSL; DIFF=1 reserved */ # define ADC_SC1_ADCH_DISABLED (31 << ADC_SC1_ADCH_SHIFT) /* Module disabled */ + #define ADC_SC1_DIFF (1 << 5) /* Bit 5: Differential mode enable */ #define ADC_SC1_AIEN (1 << 6) /* Bit 6: Interrupt enable */ #define ADC_SC1_COCO (1 << 7) /* Bit 7: Conversion complete flag */ /* Bits 8-31: Reserved */ + /* ADC configuration register 1 */ #define ADC_CFG1_ADICLK_SHIFT (0) /* Bits 0-1: Input clock select */ @@ -178,12 +180,14 @@ # define ADC_CFG1_ADICLK_BUSDIV2 (1 << ADC_CFG1_ADICLK_SHIFT) /* Bus clock/ 2 */ # define ADC_CFG1_ADICLK_ALTCLK (2 << ADC_CFG1_ADICLK_SHIFT) /* Alternate clock */ # define ADC_CFG1_ADICLK_ADACK (3 << ADC_CFG1_ADICLK_SHIFT) /* Asynchronous clock */ + #define ADC_CFG1_MODE_SHIFT (2) /* Bits 2-3: Conversion mode selection */ #define ADC_CFG1_MODE_MASK (3 << ADC_CFG1_MODE_SHIFT) # define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */ # define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */ # define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */ # define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */ + #define ADC_CFG1_ADLSMP (1 << 4) /* Bit 4: Sample time configuration */ #define ADC_CFG1_ADIV_SHIFT (5) /* Bits 5-6: Clock divide select */ #define ADC_CFG1_ADIV_MASK (3 << ADC_CFG1_ADIV_SHIFT) @@ -191,8 +195,10 @@ # define ADC_CFG1_ADIV_DIV2 (1 << ADC_CFG1_ADIV_SHIFT) /* Divider=2 rate=input clock/2 */ # define ADC_CFG1_ADIV_DIV4 (2 << ADC_CFG1_ADIV_SHIFT) /* Divider=4 rate=input clock/4 */ # define ADC_CFG1_ADIV_DIV8 (3 << ADC_CFG1_ADIV_SHIFT) /* Divider=8 rate=input clock/8 */ + #define ADC_CFG1_ADLPC (1 << 7) /* Bit 7: Low-power configuration */ /* Bits 8-31: Reserved */ + /* Configuration register 2 */ #define ADC_CFG2_ADLSTS_SHIFT (0) /* Bits 0-1: Long sample time select */ @@ -201,10 +207,12 @@ # define ADC_CFG2_ADLSTS_PLUS12 (1 << ADC_CFG2_ADLSTS_SHIFT) /* 12 extra ADCK cycles */ # define ADC_CFG2_ADLSTS_PLUS6 (2 << ADC_CFG2_ADLSTS_SHIFT) /* 6 extra ADCK cycles */ # define ADC_CFG2_ADLSTS_PLUS2 (3 << ADC_CFG2_ADLSTS_SHIFT) /* 2 extra ADCK cycles */ + #define ADC_CFG2_ADHSC (1 << 2) /* Bit 2: High speed configuration */ #define ADC_CFG2_ADACKEN (1 << 3) /* Bit 3: Asynchronous clock output enable */ #define ADC_CFG2_MUXSEL (1 << 4) /* Bit 4: ADC Mux select */ /* Bits 5-31: Reserved */ + /* ADC data result register */ #define ADC_R_MASK (0xffff) /* 16-bit signed or unsigned data */ @@ -219,6 +227,7 @@ #define ADC_SC2_REFSEL_MASK (3 << ADC_SC2_REFSEL_SHIFT) # define ADC_SC2_REFSEL_DEFAULT (0 << ADC_SC2_REFSEL_SHIFT) /* Default reference: V REFH and V REFL */ # define ADC_SC2_REFSEL_ALT (1 << ADC_SC2_REFSEL_SHIFT) /* Alternate reference: V ALTH and V ALTL */ + #define ADC_SC2_DMAEN (1 << 2) /* Bit 2: DMA enable */ #define ADC_SC2_ACREN (1 << 3) /* Bit 3: Compare function range enable */ #define ADC_SC2_ACFGT (1 << 4) /* Bit 4: Compare function greater than enable */ @@ -226,6 +235,7 @@ #define ADC_SC2_ADTRG (1 << 6) /* Bit 6: Conversion trigger select */ #define ADC_SC2_ADACT (1 << 7) /* Bit 7: Conversion active */ /* Bits 8-31: Reserved */ + /* Status and control register 3 */ #define ADC_SC3_AVGS_SHIFT (0) /* Bits 0-1: Hardware average select */ @@ -234,12 +244,14 @@ # define ADC_SC3_AVGS_8SMPLS (1 << ADC_SC3_AVGS_SHIFT) /* 8 samples averaged */ # define ADC_SC3_AVGS_16SMPLS (2 << ADC_SC3_AVGS_SHIFT) /* 18 samples averaged */ # define ADC_SC3_AVGS_32SMPLS (3 << ADC_SC3_AVGS_SHIFT) /* 32 samples averaged */ + #define ADC_SC3_AVGE (1 << 2) /* Bit 2: Hardware average enable */ #define ADC_SC3_ADCO (1 << 3) /* Bit 3: Continuous conversion enable */ /* Bits 4-5: Reserved */ #define ADC_SC3_CALF (1 << 6) /* Bit 6: Calibration failed flag */ #define ADC_SC3_CAL (1 << 7) /* Bit 7: Calibration */ /* Bits 8-31: Reserved */ + /* ADC offset correction register */ #define ADC_OFS_MASK (0xffff) /* Bits 0-15: Offset error correction value */ @@ -293,16 +305,16 @@ #define ADC_CLM1_MASK (0x7f) /* Bits 0-6: Calibration value */ #define ADC_CLM0_MASK (0x3f) /* Bits 0-5: Calibration value */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_aips.h b/arch/arm/src/kinetis/hardware/kinetis_aips.h index f96faf4b7a..86bf4f5846 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_aips.h +++ b/arch/arm/src/kinetis/hardware/kinetis_aips.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_aips.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Register Offsets *****************************************************************/ + ****************************************************************************/ + +/* Register Offsets *********************************************************/ #define KINETIS_AIPS_MPRA_OFFSET 0x0000 /* Master Privilege Register A */ @@ -57,7 +58,7 @@ # define KINETIS_AIPS_PACRU_OFFSET 0x0080 /* Peripheral Access Control Register */ #endif -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_AIPS0_MPRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_MPRA_OFFSET) #define KINETIS_AIPS0_PACRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRA_OFFSET) @@ -101,7 +102,7 @@ # define KINETIS_AIPS1_PACRU (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRU_OFFSET) #endif -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Master Privilege Register A */ @@ -131,7 +132,8 @@ #define AIPS_MPRA_MTR0 (1 << 30) /* Bit 30: Master trusted for read */ /* Bit 31: Reserved */ -/* Peripheral Access Control Register. Naming here is only accurate for PACRA. +/* Peripheral Access Control Register. + * Naming here is only accurate for PACRA. * PACRA: PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 * PACRB: PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 * PACRC: PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 @@ -187,16 +189,16 @@ #define AIPS_PACR_SP0 (1 << 30) /* Bit 30: Supervisor protect */ /* Bit 31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_axbs.h b/arch/arm/src/kinetis/hardware/kinetis_axbs.h index fec01c3342..4ae0f62abf 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_axbs.h +++ b/arch/arm/src/kinetis/hardware/kinetis_axbs.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_axbs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_AXBS_PRS_OFFSET(n) (0x0000 + ((n) << 8)) #define KINETIS_AXBS_CRS_OFFSET(n) (0x0010 + ((n) << 8)) @@ -64,7 +64,7 @@ #define KINETIS_AXBS_MGPCR6_OFFSET 0x0e00 /* Master General Purpose Control Register */ #define KINETIS_AXBS_MGPCR7_OFFSET 0x0f00 /* Master General Purpose Control Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_AXBS_PRS(n) (KINETIS_XBAR_BASE+KINETIS_AXBS_PRS_OFFSET(n)) #define KINETIS_AXBS_CRS(n) (KINETIS_XBAR_BASE+KINETIS_AXBS_CRS_OFFSET(n)) @@ -95,7 +95,7 @@ #define KINETIS_AXBS_MGPCR6 (KINETIS_XBAR_BASE+KINETIS_AXBS_MGPCR6_OFFSET) #define KINETIS_AXBS_MGPCR7 (KINETIS_XBAR_BASE+KINETIS_AXBS_MGPCR7_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Priority Registers Slave */ @@ -109,6 +109,7 @@ # define AXBS_PRS_M0_PRI6 (5 << AXBS_PRS_M0_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M0_PRI7 (6 << AXBS_PRS_M0_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M0_PRI8 (7 << AXBS_PRS_M0_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 3: Reserved */ #define AXBS_PRS_M1_SHIFT (4) /* Bits 4-6: Master 1 priority */ #define AXBS_PRS_M1_MASK (7 << AXBS_PRS_M1_SHIFT) @@ -120,6 +121,7 @@ # define AXBS_PRS_M1_PRI6 (5 << AXBS_PRS_M1_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M1_PRI7 (6 << AXBS_PRS_M1_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M1_PRI8 (7 << AXBS_PRS_M1_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 7: Reserved */ #define AXBS_PRS_M2_SHIFT (8) /* Bits 8-10: Master 2 priority */ #define AXBS_PRS_M2_MASK (7 << AXBS_PRS_M2_SHIFT) @@ -131,6 +133,7 @@ # define AXBS_PRS_M2_PRI6 (5 << AXBS_PRS_M2_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M2_PRI7 (6 << AXBS_PRS_M2_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M2_PRI8 (7 << AXBS_PRS_M2_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 11: Reserved */ #define AXBS_PRS_M3_SHIFT (12) /* Bits 12-14: Master 3 priority */ #define AXBS_PRS_M3_MASK (7 << AXBS_PRS_M3_SHIFT) @@ -142,6 +145,7 @@ # define AXBS_PRS_M3_PRI6 (5 << AXBS_PRS_M3_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M3_PRI7 (6 << AXBS_PRS_M3_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M3_PRI8 (7 << AXBS_PRS_M3_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 15: Reserved */ #define AXBS_PRS_M4_SHIFT (16) /* Bits 16-18: Master 4 priority */ #define AXBS_PRS_M4_MASK (7 << AXBS_PRS_M4_SHIFT) @@ -153,6 +157,7 @@ # define AXBS_PRS_M4_PRI6 (5 << AXBS_PRS_M4_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M4_PRI7 (6 << AXBS_PRS_M4_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M4_PRI8 (7 << AXBS_PRS_M4_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 19: Reserved */ #define AXBS_PRS_M5_SHIFT (20) /* Bits 20-22: Master 5 priority */ #define AXBS_PRS_M5_MASK (7 << AXBS_PRS_M5_SHIFT) @@ -164,6 +169,7 @@ # define AXBS_PRS_M5_PRI6 (5 << AXBS_PRS_M5_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M5_PRI7 (6 << AXBS_PRS_M5_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M5_PRI8 (7 << AXBS_PRS_M5_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 23: Reserved */ #define AXBS_PRS_M6_SHIFT (24) /* Bits 24-26: Master 6 priority */ #define AXBS_PRS_M6_MASK (7 << AXBS_PRS_M6_SHIFT) @@ -175,6 +181,7 @@ # define AXBS_PRS_M6_PRI6 (5 << AXBS_PRS_M6_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M6_PRI7 (6 << AXBS_PRS_M6_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M6_PRI8 (7 << AXBS_PRS_M6_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 27: Reserved */ #define AXBS_PRS_M7_SHIFT (28) /* Bits 28-30: Master 7 priority */ #define AXBS_PRS_M7_MASK (7 << AXBS_PRS_M7_SHIFT) @@ -186,7 +193,9 @@ # define AXBS_PRS_M7_PRI6 (5 << AXBS_PRS_M7_SHIFT) /* Master has pri 6 access to slave port */ # define AXBS_PRS_M7_PRI7 (6 << AXBS_PRS_M7_SHIFT) /* Master has pri 7 access to slave port */ # define AXBS_PRS_M7_PRI8 (7 << AXBS_PRS_M7_SHIFT) /* Master has pri 8 (lowest) access to slave port */ + /* Bit 31: Reserved */ + /* Control Register */ #define AXBS_CRS_PARK_SHIFT (0) /* Bits 0-2: Park */ @@ -197,15 +206,18 @@ # define AXBS_CRS_PARK_M3 (3 << AXBS_CRS_PARK_SHIFT) /* Park on master port M3 */ # define AXBS_CRS_PARK_M4 (4 << AXBS_CRS_PARK_SHIFT) /* Park on master port M4 */ # define AXBS_CRS_PARK_M5 (5 << AXBS_CRS_PARK_SHIFT) /* Park on master port M5 */ + #define AXBS_CRS_PCTL_SHIFT (4) /* Bits 4-5: Parking control */ #define AXBS_CRS_PCTL_MASK (2 << AXBS_CRS_PCTL_SHIFT) # define AXBS_CRS_PCTL_PARK (0 << AXBS_CRS_PCTL_SHIFT) /* Defined by the PARK bit field */ # define AXBS_CRS_PCTL_LAST (1 << AXBS_CRS_PCTL_SHIFT) /* Last master in control of slave port */ # define AXBS_CRS_PCTL_NOT (2 << AXBS_CRS_PCTL_SHIFT) /* Not parked on a master */ + #define AXBS_CRS_ARB_SHIFT (8) /* Bits 8-9: Arbitration mode */ #define AXBS_CRS_ARB_MASK (3 << AXBS_CRS_ARB_SHIFT) # define AXBS_CRS_ARB_FIXED (0 << AXBS_CRS_ARB_SHIFT) /* Fixed priority */ # define AXBS_CRS_ARB_MASK (1 << AXBS_CRS_ARB_SHIFT) /* Round-robin (rotating) priority */ + /* Bits 10-29: Reserved */ #define AXBS_CRS_HLP (1 < 30) /* Bit 30: Halt low priority */ #define AXBS_CRS_RO (1 < 31) /* Bit 31: Read only */ @@ -219,18 +231,19 @@ # define AXBS_MGPCR_AULB_4BEATS (2 << AXBS_MGPCR_AULB_SHIFT) /* Arbitration allowed after four beats */ # define AXBS_MGPCR_AULB_8BEATS (3 << AXBS_MGPCR_AULB_SHIFT) /* Arbitration allowed after eight beats */ # define AXBS_MGPCR_AULB_16BEATS (4 << AXBS_MGPCR_AULB_SHIFT) /* Arbitration allowed after 16 beats */ + /* Bits 3-31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_cmp.h b/arch/arm/src/kinetis/hardware/kinetis_cmp.h index 36462f6863..47bebf2caa 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_cmp.h +++ b/arch/arm/src/kinetis/hardware/kinetis_cmp.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_cmp.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINESIS_CMP_OFFSET(n) ((n) << 3) #define KINESIS_CMP0_OFFSET 0x0000 @@ -47,7 +47,7 @@ #define KINETIS_CMP_DACCR_OFFSET 0x0004 /* DAC Control Register */ #define KINETIS_CMP_MUXCR_OFFSET 0x0005 /* MUX Control Register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINESIS_CMP_BASE(n) (KINETIS_CMP_BASE+KINESIS_CMP_OFFSET(n)) #define KINESIS_CMP0_BASE (KINETIS_CMP_BASE+KINESIS_CMP0_OFFSET) @@ -82,7 +82,7 @@ #define KINETIS_CMP2_DACCR (KINETIS_CMP2_BASE+KINETIS_CMP_DACCR_OFFSET) #define KINETIS_CMP2_MUXCR (KINETIS_CMP2_BASE+KINETIS_CMP_MUXCR_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* CMP Control Register 0 (8-bit) */ @@ -103,7 +103,9 @@ # define CMP_CR0_FILTER_CNT5 (5 << CMP_CR0_FILTER_CNT_SHIFT) /* 5 consecutive samples must agree */ # define CMP_CR0_FILTER_CNT6 (6 << CMP_CR0_FILTER_CNT_SHIFT) /* 6 consecutive samples must agree */ # define CMP_CR0_FILTER_CNT7 (7 << CMP_CR0_FILTER_CNT_SHIFT) /* 7 consecutive samples must agree */ + /* Bit 7: Reserved */ + /* CMP Control Register 1 (8-bit) */ #define CMP_CR1_EN (1 << 0) /* Bit 0: Comparator Module Enable */ @@ -117,7 +119,6 @@ /* CMP Filter Period Register (8-bit Filter Sample Period) */ - /* CMP Status and Control Register (8-bit) */ #define CMP_SCR_COUT (1 << 0) /* Bit 0: Analog Comparator Output */ @@ -128,6 +129,7 @@ #define CMP_SCR_SMELB (1 << 5) /* Bit 5: Stop Mode Edge/Level Interrupt Control */ #define CMP_SCR_DMAEN (1 << 6) /* Bit 6: DMA Enable Control */ /* Bit 7: Reserved */ + /* DAC Control Register (8-bit) */ #define CMP_DACCR_VOSEL_SHIFT (0) /* Bits 0-5: DAC Output Voltage Select */ @@ -162,16 +164,16 @@ #endif #define CMP_MUXCR_PEN (1 << 7) /* Bit 7: PMUX Enable */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_cmt.h b/arch/arm/src/kinetis/hardware/kinetis_cmt.h index 8a1f523a34..df34c77abb 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_cmt.h +++ b/arch/arm/src/kinetis/hardware/kinetis_cmt.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_cmt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_CMT_CGH1_OFFSET 0x0000 /* CMT Carrier Generator High Data Register 1 */ #define KINETIS_CMT_CGL1_OFFSET 0x0001 /* CMT Carrier Generator Low Data Register 1 */ @@ -48,7 +48,7 @@ #define KINETIS_CMT_PPS_OFFSET 0x000a /* CMT Primary Prescaler Register */ #define KINETIS_CMT_DMA_OFFSET 0x000b /* CMT Direct Memory Access */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_CMT_CGH1 (KINETIS_CMT_BASE+KINETIS_CMT_CGH1_OFFSET) #define KINETIS_CMT_CGL1 (KINETIS_CMT_BASE+KINETIS_CMT_CGL1_OFFSET) @@ -63,17 +63,18 @@ #define KINETIS_CMT_PPS (KINETIS_CMT_BASE+KINETIS_CMT_PPS_OFFSET) #define KINETIS_CMT_DMA (KINETIS_CMT_BASE+KINETIS_CMT_DMA_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ -/* CMT Carrier Generator High/Low Data Register 1 (8-bit Primary Carrier High Time - * Data Value) +/* CMT Carrier Generator High/Low Data Register 1 + * (8-bit Primary Carrier High Time Data Value) */ -/* CMT Carrier Generator High/Low Data Register 2 (8-bit Secondary Carrier High Time - * Data Value) +/* CMT Carrier Generator High/Low Data Register 2 + * (8-bit Secondary Carrier High Time Data Value) */ /* CMT Output Control Register (8-bit) */ + /* Bits 0-4: Reserved */ #define CMT_OC_IROPEN (1 << 5) /* Bit 5: IRO Pin Enable */ #define CMT_OC_CMTPOL (1 << 6) /* Bit 6: CMT Output Polarity */ @@ -92,32 +93,36 @@ # define CMT_MSC_CMTDIV_DIV2 (1 << CMT_MSC_CMTDIV_SHIFT) /* IF / 2 */ # define CMT_MSC_CMTDIV_DIV4 (2 << CMT_MSC_CMTDIV_SHIFT) /* IF / 4 */ # define CMT_MSC_CMTDIV_DIV8 (3 << CMT_MSC_CMTDIV_SHIFT) /* IF / 8 */ + #define CMT_MSC_EOCF (1 << 7) /* Bit 7: End Of Cycle Status Flag */ /* CMT Modulator Data Register Mark High/Low (8-bit command data) */ -/* CMT Modulator Data Register Space High/Low (8-bit command data)*/ + +/* CMT Modulator Data Register Space High/Low (8-bit command data) */ /* CMT Primary Prescaler Register (8-bit) */ #define CMT_PPS_SHIFT (0) /* Bits 0-3: Primary Prescaler Divider */ #define CMT_PPS_MASK (15 << CMT_PPS_SHIFT) # define CMT_PPS_DIV(n) (((n)-1) << CMT_PPS_SHIFT) /* Bus clock / n, n=1..16 */ + /* Bits 4-7: Reserved */ + /* CMT Direct Memory Access (8-bit) */ -#define CMT_DMA_ENABLE (1 << 0) /* Bit 0: DMA Enable +#define CMT_DMA_ENABLE (1 << 0) /* Bit 0: DMA Enable */ /* Bits 1-7: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_crc.h b/arch/arm/src/kinetis/hardware/kinetis_crc.h index 822d792ff9..270e3ccf20 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_crc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_crc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_crc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,23 +31,23 @@ #if defined(KINETIS_NCRC) && KINETIS_NCRC > 0 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_CRC_DATA_OFFSET 0x0000 /* CRC Data Register */ #define KINETIS_CRC_GPOLY_OFFSET 0x0004 /* CRC Polynomial Register */ #define KINETIS_CRC_CTRL_OFFSET 0x0008 /* CRC Control Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_CRC_DATA (KINETIS_CRC_BASE+KINETIS_CRC_DATA_OFFSET) #define KINETIS_CRC_GPOLY (KINETIS_CRC_BASE+KINETIS_CRC_GPOLY_OFFSET) #define KINETIS_CRC_CTRL (KINETIS_CRC_BASE+KINETIS_CRC_CTRL_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* CRC Data Register (32-bit) */ @@ -68,6 +68,7 @@ #define CRC_GPOLY_HIGH_MASK (0xffff << CRC_GPOLY_HIGH_SHIFT) /* CRC Control Register */ + /* Bits 0-23: Reserved */ #define CRC_CTRL_TCRC (1 << 24) /* Bit 24: Width of CRC protocol */ #define CRC_CTRL_WAS (1 << 25) /* Bit 25: Write CRC data register as seed */ @@ -79,6 +80,7 @@ # define CRC_CTRL_TOTR_BITS (1 << CRC_CTRL_TOTR_SHIFT) /* Bits transposed; bytes are not */ # define CRC_CTRL_TOTR_BOTH (2 << CRC_CTRL_TOTR_SHIFT) /* Both bits bytes and bytes transposed */ # define CRC_CTRL_TOTR_BYTES (3 << CRC_CTRL_TOTR_SHIFT) /* Bytes transposed; bits in byte are not */ + #define CRC_CTRL_TOT_SHIFT (30) /* Bits 30-31: Type of Transpose for Writes */ #define CRC_CTRL_TOT_MASK (3 << CRC_CTRL_TOT_SHIFT) # define CRC_CTRL_TOT_NONE (0 << CRC_CTRL_TOT_SHIFT) /* No transposition */ @@ -86,17 +88,17 @@ # define CRC_CTRL_TOT_BOTH (2 << CRC_CTRL_TOT_SHIFT) /* Both bits bytes and bytes transposed */ # define CRC_CTRL_TOT_BYTES (3 << CRC_CTRL_TOT_SHIFT) /* Bytes transposed; bits in byte are not */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_NCRC && KINETIS_NCRC > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_dac.h b/arch/arm/src/kinetis/hardware/kinetis_dac.h index 3e459f1a64..b694a2144a 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_dac.h +++ b/arch/arm/src/kinetis/hardware/kinetis_dac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_dac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_DAC_DATL_OFFSET(n) (0x0000+((n)<<1)) #define KINETIS_DAC_DATH_OFFSET(n) (0x0001+((n)<<1)) @@ -75,7 +75,7 @@ #define KINETIS_DAC_C1_OFFSET 0x0022 /* DAC Control Register 1 */ #define KINETIS_DAC_C2_OFFSET 0x0023 /* DAC Control Register 2 */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_DAC0_DATL(n) (KINETIS_DAC0_BASE+KINETIS_DAC_DATL_OFFSET(n)) #define KINETIS_DAC0_DATH(n) (KINETIS_DAC0_BASE+KINETIS_DAC_DATH_OFFSET(n)) @@ -157,9 +157,10 @@ #define KINETIS_DAC1_C1 (KINETIS_DAC1_BASE+KINETIS_DAC_C1_OFFSET) #define KINETIS_DAC1_C2 (KINETIS_DAC1_BASE+KINETIS_DAC_C2_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* DAC Data Low Register (8-bits of data DATA[7:0]) */ + /* DAC Data High Register */ #define DAC_DAT0H_MASK (0x0f) /* Bits 0-3: DATA[11:8] */ @@ -168,8 +169,9 @@ #define DAC_SR_DACBFRPBF (1 << 0) /* Bit 0: DAC buffer read pointer bottom position flag */ #define DAC_SR_DACBFRPTF (1 << 1) /* Bit 1: DAC buffer read pointer top position flag */ -#define DAC_SR_DACBFWMF (1 << 2) /* Bit 2: DAC buffer watermark flag +#define DAC_SR_DACBFWMF (1 << 2) /* Bit 2: DAC buffer watermark flag */ /* Bits 3-7: Reserved */ + /* DAC Control Register */ #define DAC_C0_DACBBIEN (1 << 0) /* Bit 0: DAC buffer read pointer bottom flag interrupt enable */ @@ -189,6 +191,7 @@ # define DAC_C1_DACBFMD_NORMAL (0 << DAC_C1_DACBFMD_SHIFT) /* Normal Mode */ # define DAC_C1_DACBFMD_SWING (1 << DAC_C1_DACBFMD_SHIFT) /* Swing Mode */ # define DAC_C1_DACBFMD_OTSCAN (2 << DAC_C1_DACBFMD_SHIFT) /* One-Time Scan Mode */ + #define DAC_C1_DACBFWM_SHIFT (3) /* Bits 3-4: DAC buffer watermark select */ #define DAC_C1_DACBFWM_MASK (3 << DAC_C1_DACBFWM_SHIFT) # define DAC_C1_DACBFWM_1WORD (0 << DAC_C1_DACBFWM_SHIFT) @@ -205,16 +208,16 @@ #define DAC_C2_DACBFUP_SHIFT (0) /* Bits 0-3: DAC buffer upper limit */ #define DAC_C2_DACBFUP_MASK (15 << DAC_C2_DACBFUP_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_dma.h b/arch/arm/src/kinetis/hardware/kinetis_dma.h index aa797c0b6c..bd2b941c72 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_dma.h +++ b/arch/arm/src/kinetis/hardware/kinetis_dma.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_dma.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_DMA_CR_OFFSET 0x0000 /* Control Register */ #define KINETIS_DMA_ES_OFFSET 0x0004 /* Error Status Register */ @@ -68,7 +68,6 @@ #define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */ #define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */ - #define KINETIS_DMA_DCHPRI_OFFSET(n) 0x0100 + (n - (n % 4)) + (3 - (n % 4)) /* Channel n Priority Register */ #define KINETIS_DMA_TCD_OFFSET(n) (0x0000 + ((n) << 5)) @@ -276,7 +275,7 @@ #define KINETIS_DMA_TCD15_CSR_OFFSET 0x01fc /* TCD Control and Status */ #define KINETIS_DMA_TCD15_BITER_OFFSET 0x01fe /* TCD Beginning Minor Loop Link, Major Loop Count */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_DMA_CR (KINETIS_DMAC_BASE + KINETIS_DMA_CR_OFFSET) #define KINETIS_DMA_ES (KINETIS_DMAC_BASE + KINETIS_DMA_ES_OFFSET) @@ -519,9 +518,10 @@ #define KINETIS_DMA_TCD15_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CSR_OFFSET) #define KINETIS_DMA_TCD15_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_BITER_OFFSET) -/* Register Bit Definitions *************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Control Register (32-bit) */ + /* Bit 0: Reserved */ #define DMA_CR_EDBG (1 << 1) /* Bit 1: Enable debug */ #define DMA_CR_ERCA (1 << 2) /* Bit 2: Enable round robin channel arbitration */ @@ -565,8 +565,9 @@ /* Bits 17-30: Reserved */ #define DMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */ -/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI), Interrupt Request Register (INT), - * Error Register (ERR), Hardware Request Status Register (HRS) common bit definitions +/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI), + * Interrupt Request Register (INT), Error Register (ERR), + * Hardware Request Status Register (HRS) common bit definitions */ #define DMA_REQ(n) (1 << (n)) /* Bit n: DMA Request n, n=0.. #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #if KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG == 0 @@ -63,11 +63,12 @@ # define KINETIS_DMAMUX_CHCFG_OFFSET(n) (n) #endif -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_DMAMUX_CHCFG(n) (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG_OFFSET(n)) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ + /* Channel n Configuration Register */ #define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (slot) */ @@ -75,7 +76,7 @@ #define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable */ #define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable */ -/* DMA Request sources*****************************************************************************/ +/* DMA Request sources*******************************************************/ #ifdef KINETIS_K60 @@ -258,16 +259,16 @@ #endif /* KINETIS_K66 */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_dspi.h b/arch/arm/src/kinetis/hardware/kinetis_dspi.h index 40832a534c..041261e4ea 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_dspi.h +++ b/arch/arm/src/kinetis/hardware/kinetis_dspi.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_dspi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_SPI_MCR_OFFSET 0x0000 /* DSPI Module Configuration Register */ #define KINETIS_SPI_TCR_OFFSET 0x0008 /* DSPI Transfer Count Register */ @@ -52,7 +52,7 @@ #define KINETIS_SPI_RXFR2_OFFSET 0x0084 /* DSPI Receive FIFO Registers */ #define KINETIS_SPI_RXFR3_OFFSET 0x0088 /* DSPI Receive FIFO Registers */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_SPI0_MCR (KINETIS_SPI0_BASE+KINETIS_SPI_MCR_OFFSET) #define KINETIS_SPI0_TCR (KINETIS_SPI0_BASE+KINETIS_SPI_TCR_OFFSET) @@ -105,7 +105,7 @@ #define KINETIS_SPI2_RXFR2 (KINETIS_SPI2_BASE+KINETIS_SPI_RXFR2_OFFSET) #define KINETIS_SPI2_RXFR3 (KINETIS_SPI2_BASE+KINETIS_SPI_RXFR3_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* DSPI Module Configuration Register */ @@ -116,6 +116,7 @@ # define SPI_MCR_SMPL_PT_0CLKS (0 << SPI_MCR_SMPL_PT_SHIFT) /* 0 clocks between edge and sample */ # define SPI_MCR_SMPL_PT_1CLKS (1 << SPI_MCR_SMPL_PT_SHIFT) /* 1 clock between edge and sample */ # define SPI_MCR_SMPL_PT_2CLKS (2 << SPI_MCR_SMPL_PT_SHIFT) /* 2 clocks between edge and sample */ + #define SPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO */ #define SPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO */ #define SPI_MCR_DIS_RXF (1 << 12) /* Bit 12: Disable Receive FIFO */ @@ -137,6 +138,7 @@ #define SPI_MCR_MSTR (1 << 31) /* Bit 31: Master/Slave Mode Select */ /* DSPI Transfer Count Register */ + /* Bits 0-15: Reserved */ #define SPI_TCR_SPI_TCNT_SHIFT (16) /* Bits 16-31: SPI Transfer Counter */ #define SPI_TCR_SPI_TCNT_MASK (0xffff << SPI_TCR_SPI_TCNT_SHIFT) @@ -222,8 +224,12 @@ #define SPI_CTARM_DBR (1 << 31) /* Bit 31: Double Baud Rate */ /* DSPI Clock and Transfer Attributes Register (Slave Mode) */ + /* Bits 0-24: Reserved */ - /* Bits 25-26: See common bits above */ + +/* Bits 25-26: + * See common bits above + */ #define SPI_CTARS_FMSZ_SHIFT (27) /* Bits 27-31: Frame Size */ #define SPI_CTARS_FMSZ_MASK (31 << SPI_CTARS_FMSZ_SHIFT) @@ -251,6 +257,7 @@ #define SPI_SR_TCF (1 << 31) /* Bit 31: Transfer Complete Flag */ /* DSPI DMA/Interrupt Request Select and Enable Register */ + /* Bits 0-15: Reserved */ #define SPI_RSER_RFDF_DIRS (1 << 16) /* Bit 16: Receive FIFO Drain DMA or Interrupt Request Select */ #define SPI_RSER_RFDF_RE (1 << 17) /* Bit 17: Receive FIFO Drain Request Enable */ @@ -265,7 +272,7 @@ /* Bits 29-30: Reserved */ #define SPI_RSER_TCF_RE (1 << 31) /* Bit 31: Transmission Complete Request Enable */ -/* DSPI PUSH TX FIFO Register (Master Mode)*/ +/* DSPI PUSH TX FIFO Register (Master Mode) */ #define SPI_PUSHR_TXDATA_SHIFT (0) /* Bits 0-15: Transmit Data */ #define SPI_PUSHR_TXDATA_MASK (0xffff << SPI_PUSHR_TXDATA_SHIFT) @@ -282,7 +289,7 @@ # define SPI_PUSHR_CTAS_CTAR1 (1 << SPI_PUSHR_CTAS_SHIFT) #define SPI_PUSHR_CONT (1 << 31) /* Bit 31: Continuous Peripheral Chip Select Enable */ -/* DSPI PUSH TX FIFO Register (Slave Mode, 32-bits of RXDATA)*/ +/* DSPI PUSH TX FIFO Register (Slave Mode, 32-bits of RXDATA) */ /* DSPI POP RX FIFO Register (32-bits of RXDATA) */ @@ -295,16 +302,16 @@ /* DSPI Receive FIFO Registers (32-bits of RXDATA) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_enet.h b/arch/arm/src/kinetis/hardware/kinetis_enet.h index c5e8592817..fdff9fa392 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_enet.h +++ b/arch/arm/src/kinetis/hardware/kinetis_enet.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,11 @@ #if defined(KINETIS_NENET) && KINETIS_NENET > 0 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ #define KINETIS_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ @@ -88,7 +88,7 @@ #define KINETIS_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ #define KINETIS_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_ENET_EIR (KINETIS_EMAC_BASE+KINETIS_ENET_EIR_OFFSET) #define KINETIS_ENET_EIMR (KINETIS_EMAC_BASE+KINETIS_ENET_EIMR_OFFSET) @@ -141,9 +141,10 @@ #define KINETIS_ENET_TCSR3 (KINETIS_EMAC_BASE+KINETIS_ENET_TCSR3_OFFSET) #define KINETIS_ENET_TCCR3 (KINETIS_EMAC_BASE+KINETIS_ENET_TCCR3_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Interrupt Event Register, Interrupt Mask Register */ + /* Bits 0-14: Reserved */ #define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */ #define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */ @@ -162,14 +163,19 @@ #define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */ #define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */ /* Bit 31: Reserved */ + /* Receive Descriptor Active Register */ + /* Bits 0-23: Reserved */ #define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */ /* Bits 25-31: Reserved */ + /* Transmit Descriptor Active Register */ + /* Bits 0-23: Reserved */ #define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */ /* Bits 25-31: Reserved */ + /* Ethernet Control Register */ #define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */ @@ -184,6 +190,7 @@ #define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes */ #endif /* Bits 9-31: Reserved */ + /* MII Management Frame Register */ #define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */ @@ -200,10 +207,12 @@ # define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */ # define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */ # define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */ + #define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */ #define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT) /* MII Speed Control Register */ + /* Bit 0: Reserved */ #define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */ #define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT) @@ -214,8 +223,11 @@ # define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */ # define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */ # define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */ + /* Bits 11-31: Reserved */ + /* MIB Control Register */ + /* Bits 0-28: Reserved */ #define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */ #define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */ @@ -253,9 +265,12 @@ #define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */ #define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT) # define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */ + #define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */ /* Bits 10-31: Reserved */ + /* Physical Address Lower/Upper Register (32-bits of 48-address) */ + /* Physical Address Upper Register */ #define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */ @@ -270,8 +285,13 @@ #define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ #define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) -/* Descriptor Individual Uupper/Lower Address Register (64-bit address in two 32-bit registers) */ -/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */ +/* Descriptor Individual Uupper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ + +/* Descriptor Group Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ /* Transmit FIFO Watermark Register */ @@ -280,22 +300,28 @@ #define ENET_TFWR_TFWR_MASK (63 << ENET_TFWR_TFWR_SHIFT) #define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */ /* Bits 9-31: Reserved */ + /* Receive Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ #define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ #define ENET_RDSR_MASK (0xfffffff8) /* Transmit Buffer Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ #define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */ #define ENET_TDSR_MASK (0xfffffff8) /* Maximum Receive Buffer Size Register */ + /* Bits 14-31: Reserved */ #define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */ #define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT) /* Bits 0-3: Reserved */ + /* Receive FIFO Section Full Threshold */ + /* Bits 8-31: Reserved */ #define ENET_RSFL_SHIFT (0) /* Bits 0-7: Value of receive FIFO section full threshold */ #define ENET_RSFL_MASK (0xff << ENET_RSFL_SHIFT) @@ -305,41 +331,49 @@ #define ENET_RSEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO section empty threshold */ #define ENET_RSEM_MASK (0xff << ENET_RSEM_SHIFT) /* Bits 8-31: Reserved */ + /* Receive FIFO Almost Empty Threshold */ #define ENET_RAEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost empty threshold */ #define ENET_RAEM_MASK (0xff << ENET_RAEM_SHIFT) /* Bits 8-31: Reserved */ + /* Receive FIFO Almost Full Threshold */ #define ENET_RAFL_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost full threshold */ #define ENET_RAFL_MASK (0xff << ENET_RAFL_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit FIFO Section Empty Threshold */ #define ENET_TSEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ #define ENET_TSEM_MASK (0xff << ENET_TSEM_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit FIFO Almost Empty Threshold */ #define ENET_TAEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ #define ENET_TAEM_MASK (0xff << ENET_TAEM_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit FIFO Almost Full Threshold */ #define ENET_TAFL_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ #define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit Inter-Packet Gap */ #define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */ #define ENET_TIPG_MASK (31 << ENET_TIPG_SHIFT) /* Bits 5-31: Reserved */ + /* Frame Truncation Length */ #define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */ #define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT) /* Bits 14-31: Reserved */ + /* Transmit Accelerator Function Configuration */ #define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */ @@ -347,6 +381,7 @@ #define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */ #define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */ /* Bits 5-31: Reserved */ + /* Receive Accelerator Function Configuration */ #define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */ @@ -356,6 +391,7 @@ #define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */ #define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */ /* Bits 8-31: Reserved */ + /* Timer Control Register */ #define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */ @@ -372,14 +408,19 @@ /* Bit 12: Reserved */ #define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */ /* Bits 14-31: Reserved */ + /* Timer Value Register (32-bit timer value) */ + /* Timer Offset Register (32-bit offset value) */ + /* Timer Period Register (32-bit timer period) */ /* Timer Correction Register */ #define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */ - /* Bit 31: Reserved */ + + /* Bit 31: Reserved */ + /* Time-Stamping Clock Period Register */ #define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */ @@ -388,6 +429,7 @@ #define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */ #define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT) /* Bits 15-31: Reserved */ + /* Timestamp of Last Transmitted Frame (32-bit timestamp) */ /* Timer Global Status Register */ @@ -397,6 +439,7 @@ #define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */ #define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */ /* Bits 14-31: Reserved */ + /* Timer Control Status Register n */ #define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */ @@ -415,12 +458,15 @@ # define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */ # define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */ # define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */ + #define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */ #define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */ /* Bits 8-31: Reserved */ + /* Timer Compare Capture Register (32-bit compare value) */ -/* Buffer Descriptors ***********************************************************************/ +/* Buffer Descriptors *******************************************************/ + /* Endian-independent descriptor offsets */ #define DESC_STATUS1_OFFSET (0) @@ -566,10 +612,12 @@ # define RXDESC_BDU (1 << 7) #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ -/* Buffer Descriptors ***********************************************************************/ + ****************************************************************************/ + +/* Buffer Descriptors *******************************************************/ + /* Legacy Buffer Descriptor */ #ifdef CONFIG_ENET_ENHANCEDBD @@ -625,13 +673,13 @@ struct enet_desc_s #endif #endif -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_NENET && KINETIS_NENET > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_ewm.h b/arch/arm/src/kinetis/hardware/kinetis_ewm.h index 19baf13d63..665b69e8c4 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_ewm.h +++ b/arch/arm/src/kinetis/hardware/kinetis_ewm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_ewm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_EWM_CTRL_OFFSET 0x0000 /* Control Register */ #define KINETIS_EWM_SERV_OFFSET 0x0001 /* Service Register */ #define KINETIS_EWM_CMPL_OFFSET 0x0002 /* Compare Low Register */ #define KINETIS_EWM_CMPH_OFFSET 0x0003 /* Compare High Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_EWM_CTRL (KINETIS_EWM_BASE+KINETIS_EWM_CTRL_OFFSET) #define KINETIS_EWM_SERV (KINETIS_EWM_BASE+KINETIS_EWM_SERV_OFFSET) #define KINETIS_EWM_CMPL (KINETIS_EWM_BASE+KINETIS_EWM_CMPL_OFFSET) #define KINETIS_EWM_CMPH (KINETIS_EWM_BASE+KINETIS_EWM_CMPH_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Control Register (8-bit) */ @@ -57,19 +57,21 @@ /* Bits 7–3: Reserved */ /* Service Register (8-bit values: 0xb4 followed by 0x2c) */ + /* Compare Low Register (8-bit compare low value) */ + /* Compare High Register (8-bit compare high value) */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_flexbus.h b/arch/arm/src/kinetis/hardware/kinetis_flexbus.h index 183f61b871..f926f2995d 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_flexbus.h +++ b/arch/arm/src/kinetis/hardware/kinetis_flexbus.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_flexbus.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_FB_CS_OFFSET(n) (0x0000+(12*(n))) #define KINETIS_FB_CSAR_OFFSET 0x0000 /* Chip select n address register */ @@ -66,7 +66,8 @@ #define KINETIS_FB_CSPMCR_OFFSET 0x0060 /* Chip select port multiplexing control register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ + # define 0x4000c000 /* FlexBus */ #define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n)) @@ -100,7 +101,7 @@ #define KINETIS_FB_CSPMCR (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSPMCR_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Chip select address register (32-bit) */ @@ -112,12 +113,13 @@ #define FB_CSMR_V (1 << 0) /* Bit 0: Valid */ /* Bits 1-7: Reserved */ -#define FB_CSMR_WP (1 << 8) /* Bit 8: Write protect +#define FB_CSMR_WP (1 << 8) /* Bit 8: Write protect */ /* Bits 9-15: Reserved */ #define FB_CSMR_BAM_SHIFT (16) /* Bits 16-31: Base address mask */ #define FB_CSMR_BAM_MASK (0xffff << FB_CSMR_BAM_SHIFT) /* Chip select control register (32-bit) */ + /* Bits 0-1: Reserved */ #define FB_CSCR_BSTW (1 << 3) /* Bit 3: Burst-write enable */ #define FB_CSCR_BSTR (1 << 4) /* Bit 4: Burst-read enable */ @@ -127,6 +129,7 @@ # define FB_CSCR_PS_32BIT (0 << FB_CSCR_PS_SHIFT) /* 32-bit port size */ # define FB_CSCR_PS_8BIT (1 << FB_CSCR_PS_SHIFT) /* 8-bit port size */ # define FB_CSCR_PS_16BIT (2 << FB_CSCR_PS_SHIFT) /* 16-bit port size */ + #define FB_CSCR_AA (1 << 8) /* Bit 8: Auto-acknowledge enable */ #define FB_CSCR_BLS (1 << 9) /* Bit 9: Byte-lane shift */ #define FB_CSCR_WS_SHIFT (10) /* Bits 19-15: Wait states */ @@ -137,18 +140,21 @@ # define FB_CSCR_WRAH_HOLD2 (1 << FB_CSCR_WRAH_SHIFT) /* Hold two cycles after FB_CSn */ # define FB_CSCR_WRAH_HOLD3 (2 << FB_CSCR_WRAH_SHIFT) /* Hold three cycles after FB_CSn */ # define FB_CSCR_WRAH_HOLD4 (3 << FB_CSCR_WRAH_SHIFT) /* Hold four cycles after FB_CSn */ + #define FB_CSCR_RDAH_SHIFT (18) /* Bits 18-19: Read address hold or deselect */ #define FB_CSCR_RDAH_MASK (3 << FB_CSCR_RDAH_SHIFT) # define FB_CSCR_RDAH_10CYCLES (0 << FB_CSCR_RDAH_SHIFT) /* AA=0:1 cycle else 0 cycles */ # define FB_CSCR_RDAH_21CYCLES (1 << FB_CSCR_RDAH_SHIFT) /* AA=0:2 cycles else 1 cycle */ # define FB_CSCR_RDAH_32CYCLES (2 << FB_CSCR_RDAH_SHIFT) /* AA=0:3 cycles else 2 cycles */ # define FB_CSCR_RDAH_43CYCLES (3 << FB_CSCR_RDAH_SHIFT) /* AA=0:4 cycles else 3 cycles */ + #define FB_CSCR_ASET_SHIFT (20) /* Bits 20-21: Address setup */ #define FB_CSCR_ASET_MASK (3 << FB_CSCR_ASET_SHIFT) # define FB_CSCR_ASET_1STRISING (0 << FB_CSCR_ASET_SHIFT) /* Assert CR on first rising clock edge */ # define FB_CSCR_ASET_2NDRISING (1 << FB_CSCR_ASET_SHIFT) /* Assert CR on second rising clock edge */ # define FB_CSCR_ASET_3RDRISING (2 << FB_CSCR_ASET_SHIFT) /* Assert CR on third rising clock edge */ # define FB_CSCR_ASET_4thRISING (3 << FB_CSCR_ASET_SHIFT) /* Assert CR on fourth rising clock edge */ + #define FB_CSCR_EXTS (1 << 22) /* Bit 22: Extended address latch enable */ #define FB_CSCR_SWSEN (1 << 23) /* Bit 23: Secondary wait state enable */ /* Bits 24-25: Reserved */ @@ -156,43 +162,48 @@ #define FB_CSCR_SWS_MASK (0x3f << FB_CSCR_SWS_SHIFT) /* Chip select port multiplexing control register (32-bit) */ + /* Bits 0-11: Reserved */ #define FB_CSPMCR_GROUP5_SHIFT (12) /* Bits 12-15: FlexBus signal group 5 multiplex control */ #define FB_CSPMCR_GROUP5_MASK (15 << FB_CSPMCR_GROUP5_SHIFT) # define FB_CSPMCR_GROUP5_TA (0 << FB_CSPMCR_GROUP5_SHIFT) /* FB_TA */ # define FB_CSPMCR_GROUP5_CS3 (1 << FB_CSPMCR_GROUP5_SHIFT) /* FB_CS3 */ # define FB_CSPMCR_GROUP5_BE70 (2 << FB_CSPMCR_GROUP5_SHIFT) /* FB_BE_7_0 */ + #define FB_CSPMCR_GROUP4_SHIFT (16) /* Bits 16-19: FlexBus signal group 4 multiplex control */ #define FB_CSPMCR_GROUP4_MASK (15 << FB_CSPMCR_GROUP4_SHIFT) # define FB_CSPMCR_GROUP4_TBST (0 << FB_CSPMCR_GROUP4_SHIFT) /* FB_TBST */ # define FB_CSPMCR_GROUP4_CS2 (1 << FB_CSPMCR_GROUP4_SHIFT) /* FB_CS2 */ # define FB_CSPMCR_GROUP4_BE158 (2 << FB_CSPMCR_GROUP4_SHIFT) /* FB_BE_15_8 */ + #define FB_CSPMCR_GROUP3_SHIFT (20) /* Bits 29-23: FlexBus signal group 3 multiplex control */ #define FB_CSPMCR_GROUP3_MASK (15 << FB_CSPMCR_GROUP3_SHIFT) # define FB_CSPMCR_GROUP3_CS5 (0 << FB_CSPMCR_GROUP3_SHIFT) /* FB_CS5 */ # define FB_CSPMCR_GROUP3_TSIZ1 (1 << FB_CSPMCR_GROUP3_SHIFT) /* FB_TSIZ1 */ # define FB_CSPMCR_GROUP3_BE2316 (2 << FB_CSPMCR_GROUP3_SHIFT) /* FB_BE_23_16 */ + #define FB_CSPMCR_GROUP2_SHIFT (24) /* Bits 24-27: FlexBus signal group 2 multiplex control */ #define FB_CSPMCR_GROUP2_MASK (15 << FB_CSPMCR_GROUP2_SHIFT) # define FB_CSPMCR_GROUP2_CS4 (0 << FB_CSPMCR_GROUP2_SHIFT) /* FB_CS4 */ # define FB_CSPMCR_GROUP2_TSIZ0 (1 << FB_CSPMCR_GROUP2_SHIFT) /* FB_TSIZ0 */ # define FB_CSPMCR_GROUP2_BE3124 (2 << FB_CSPMCR_GROUP2_SHIFT) /* FB_BE_31_24 */ + #define FB_CSPMCR_GROUP1_SHIFT (28) /* Bits 28-31: FlexBus signal group 1 multiplex control */ #define FB_CSPMCR_GROUP1_MASK (15 << FB_CSPMCR_GROUP1_MASK) # define FB_CSPMCR_GROUP1_ALE (0 << FB_CSPMCR_GROUP1_MASK) /* FB_ALE */ # define FB_CSPMCR_GROUP1_CS1 (1 << FB_CSPMCR_GROUP1_MASK) /* FB_CS1 */ # define FB_CSPMCR_GROUP1_TS (2 << FB_CSPMCR_GROUP1_MASK) /* FB_TS */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_flexcan.h b/arch/arm/src/kinetis/hardware/kinetis_flexcan.h index 3d1a62024b..4d0011ccf1 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_flexcan.h +++ b/arch/arm/src/kinetis/hardware/kinetis_flexcan.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_flexcan.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_CAN_MCR_OFFSET 0x0000 /* Module Configuration Register */ #define KINETIS_CAN_CTRL1_OFFSET 0x0004 /* Control 1 Register */ @@ -73,7 +73,7 @@ #define KINETIS_CAN_RXIMR14_OFFSET 0x08b8 /* R14 Individual Mask Registers */ #define KINETIS_CAN_RXIMR15_OFFSET 0x08bc /* R15 Individual Mask Registers */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_CAN0_MCR (KINETIS_CAN0_BASE+KINETIS_CAN_MCR_OFFSET) #define KINETIS_CAN0_CTRL1 (KINETIS_CAN0_BASE+KINETIS_CAN_CTRL1_OFFSET) @@ -112,7 +112,7 @@ #define KINETIS_CAN0_RXIMR15 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR15_OFFSET) #define KINETIS_CAN0_RXIMR_COUNT 16 /* Individual Mask Registers Count */ -/* Register Bit Definitions *************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Module Configuration Register */ @@ -320,12 +320,12 @@ /* an incoming Remote Request Frame. */ #define CAN_TXMB_NOTUSED 0xF /* Not used.*/ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_fmc.h b/arch/arm/src/kinetis/hardware/kinetis_fmc.h index 804697ee79..fc92d61b08 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_fmc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_fmc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_fmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/* This file is just a wrapper around FMC header files for the Kinetis family selected by - * the logic in chip.h. +/* This file is just a wrapper around FMC header files for the Kinetis + * family selected by the logic in chip.h. */ #if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60) @@ -43,20 +43,20 @@ # error "No FMC definitions for this Kinetis part" #endif -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_ftfe.h b/arch/arm/src/kinetis/hardware/kinetis_ftfe.h index e8db7bfa00..6d7b1c49c7 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_ftfe.h +++ b/arch/arm/src/kinetis/hardware/kinetis_ftfe.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_ftfe.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_FTFE_FSTAT_OFFSET 0x0000 /* Flash Status Register */ #define KINETIS_FTFE_FCNFG_OFFSET 0x0001 /* Flash Configuration Register */ @@ -59,7 +59,7 @@ #define KINETIS_FTFE_FEPROT_OFFSET 0x0016 /* EEPROM Protection Register */ #define KINETIS_FTFE_FDPROT_OFFSET 0x0017 /* Data Flash Protection Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_FTFE_FSTAT (KINETIS_FTFE_BASE+KINETIS_FTFE_FSTAT_OFFSET) #define KINETIS_FTFE_FCNFG (KINETIS_FTFE_BASE+KINETIS_FTFE_FCNFG_OFFSET) @@ -84,7 +84,7 @@ #define KINETIS_FTFE_FEPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FEPROT_OFFSET) #define KINETIS_FTFE_FDPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FDPROT_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Flash Status Register */ @@ -112,33 +112,40 @@ #define FTFE_FSEC_SEC_MASK (3 << FTFE_FSEC_SEC_SHIFT) # define FTFE_FSEC_SEC_SECURE (0 << FTFE_FSEC_SEC_SHIFT) /* 00,01,11: status is secure */ # define FTFE_FSEC_SEC_UNSECURE (2 << FTFE_FSEC_SEC_SHIFT) /* 10: status is insecure */ + #define FTFE_FSEC_FSLACC_SHIFT (2) /* Bits 2-3: Freescale Failure Analysis Access Code */ #define FTFE_FSEC_FSLACC_MASK (3 << FTFE_FSEC_FSLACC_SHIFT) # define FTFE_FSEC_FSLACC_GRANTED (0 << FTFE_FSEC_FSLACC_SHIFT) /* 00 or 11: Access granted */ # define FTFE_FSEC_FSLACC_DENIED (1 << FTFE_FSEC_FSLACC_SHIFT) /* 01 or 10: Access denied */ + #define FTFE_FSEC_MEEN_SHIFT (4) /* Bits 4-5: Mass Erase Enable Bits */ #define FTFE_FSEC_MEEN_MASK (3 << FTFE_FSEC_MEEN_SHIFT) # define FTFE_FSEC_MEEN_ENABLED (0 << FTFE_FSEC_MEEN_SHIFT) /* All values are enabled */ + #define FTFE_FSEC_KEYEN_SHIFT (6) /* Bits 6-7: Backdoor Key Security Enable */ #define FTFE_FSEC_KEYEN_MASK (3 << FTFE_FSEC_KEYEN_SHIFT) # define FTFE_FSEC_KEYEN_DISABLED (1 << FTFE_FSEC_KEYEN_SHIFT) /* All values are disabled */ /* Flash Option Register (32-bits, see Chip Configuration details) */ + /* Flash Common Command Object Registers (8-bit flash command data) */ + /* Program Flash Protection Registers (8-bit flash protection data) */ + /* EEPROM Protection Register (8-bit eeprom protection data) */ + /* Data Flash Protection Register (8-bit data flash protection data) */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_ftm.h b/arch/arm/src/kinetis/hardware/kinetis_ftm.h index 044e6c9747..6cc27496b0 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_ftm.h +++ b/arch/arm/src/kinetis/hardware/kinetis_ftm.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_ftm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_FTM_SC_OFFSET 0x0000 /* Status and Control */ #define KINETIS_FTM_CNT_OFFSET 0x0004 /* Counter */ @@ -41,6 +41,7 @@ #define KINETIS_FTM_CSC_OFFSET(n) (0x000c+((n)<<3)) /* Channel (n) Status and Control */ #define KINETIS_FTM_CV_OFFSET(n) (0x0010+((n)<<3)) /* Channel (n) Value */ + #define KINETIS_FTM_C0SC_OFFSET 0x000c /* Channel 0 Status and Control */ #define KINETIS_FTM_C0V_OFFSET 0x0010 /* Channel 0 Value */ #define KINETIS_FTM_C1SC_OFFSET 0x0014 /* Channel 1 Status and Control */ @@ -79,7 +80,7 @@ #define KINETIS_FTM_SWOCTRL_OFFSET 0x0094 /* FTM Software Output Control */ #define KINETIS_FTM_PWMLOAD_OFFSET 0x0098 /* FTM PWM Load */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_FTM0_SC (KINETIS_FTM0_BASE+KINETIS_FTM_SC_OFFSET) #define KINETIS_FTM0_CNT (KINETIS_FTM0_BASE+KINETIS_FTM_CNT_OFFSET) @@ -257,7 +258,7 @@ #define KINETIS_FTM3_SWOCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_SWOCTRL_OFFSET) #define KINETIS_FTM3_PWMLOAD (KINETIS_FTM3_BASE+KINETIS_FTM_PWMLOAD_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Status and Control */ @@ -277,10 +278,12 @@ # define FTM_SC_CLKS_SYSCLK (1 << FTM_SC_CLKS_SHIFT) /* System clock */ # define FTM_SC_CLKS_FIXED (2 << FTM_SC_CLKS_SHIFT) /* Fixed frequency clock */ # define FTM_SC_CLKS_EXTCLK (3 << FTM_SC_CLKS_SHIFT) /* External clock */ + #define FTM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */ #define FTM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */ #define FTM_SC_TOF (1 << 7) /* Bit 7: Timer Overflow Flag */ /* Bits 8-31: Reserved */ + /* Counter */ #define FTM_CNT_SHIFT (0) /* Bits 0-15: Counter value */ @@ -304,20 +307,23 @@ #define FTM_CSC_CHIE (1 << 6) /* Bit 6: Channel Interrupt Enable */ #define FTM_CSC_CHF (1 << 7) /* Bit 7: Channel Flag */ /* Bits 8-31: Reserved */ + /* Channel (n) Value */ #define FTM_CV_SHIFT (0) /* Bits 0-15: Channel Value */ #define FTM_CV_MASK (0xffff << FTM_CV_SHIFT) /* Bits 16-31: Reserved */ + /* Counter Initial Value */ #define FTM_CNTIN_SHIFT (0) /* Bits 0-15: Initial Value of the FTM Counter */ #define FTM_CNTIN_MASK (0xffff << FTM_CNTIN_SHIFT) /* Bits 16-31: Reserved */ + /* Capture and Compare Status */ #define FTM_STATUS(n) (1 << (n)) /* Channel (n) Flag, n=0..7 */ - /* Bits 8-31: Reserved */ + /* Bits 8-31: Reserved */ /* Features Mode Selection */ @@ -332,8 +338,10 @@ # define FTM_MODE_FAULTM_EVEN (1 << FTM_MODE_FAULTM_SHIFT) /* Enable even channels, manual fault clearing */ # define FTM_MODE_FAULTM_MANUAL (2 << FTM_MODE_FAULTM_SHIFT) /* Enable all channels, manual fault clearing */ # define FTM_MODE_FAULTM_AUTO (3 << FTM_MODE_FAULTM_SHIFT) /* Enable all channels, automatic fault clearing */ + #define FTM_MODE_FAULTIE (1 << 7) /* Bit 7: Fault Interrupt Enable */ /* Bits 8-31: Reserved */ + /* Synchronization */ #define FTM_SYNC_CNTMIN (1 << 0) /* Bit 0: Minimum loading point enable */ @@ -345,14 +353,17 @@ #define FTM_SYNC_TRIG2 (1 << 6) /* Bit 6: PWM Synchronization Hardware Trigger 2 */ #define FTM_SYNC_SWSYNC (1 << 7) /* Bit 7: PWM Synchronization Software Trigger */ /* Bits 8-31: Reserved */ + /* Initial State for Channels Output */ #define FTM_OUTINIT(n) (1 << (n)) /* Channel (n) Output Initialization Value, n=0..7 */ - /* Bits 8-31: Reserved */ + /* Bits 8-31: Reserved */ + /* Output Mask */ #define FTM_OUTMASK(n) (1 << (n)) /* Channel (n) Output Mask, n=0..7 */ - /* Bits 8-31: Reserved */ + /* Bits 8-31: Reserved */ + /* Function for Linked Channels */ #define FTM_COMBINE_COMBINE0 (1 << 0) /* Bit 0: Combine Channels for n = 0 */ @@ -387,6 +398,7 @@ #define FTM_COMBINE_SYNCEN3 (1 << 29) /* Bit 29: Synchronization Enable for n = 6 */ #define FTM_COMBINE_FAULTEN3 (1 << 30) /* Bit 30: Fault Control Enable for n = 6 */ /* Bit 31: Reserved */ + /* Deadtime Insertion Control */ #define FTM_DEADTIME_DTVAL_SHIFT (0) /* Bits 0-5: Deadtime Value */ @@ -397,6 +409,7 @@ # define FTM_DEADTIME_DTPS_DIV4 (2 << FTM_DEADTIME_DTPS_SHIFT) # define FTM_DEADTIME_DTPS_DIV16 (3 << FTM_DEADTIME_DTPS_SHIFT) /* Bits 8-31: Reserved */ + /* FTM External Trigger */ #define FTM_EXTTRIG_CH2TRIG (1 << 0) /* Bit 0: Channel 2 Trigger Enable */ @@ -408,10 +421,11 @@ #define FTM_EXTTRIG_INITTRIGEN (1 << 6) /* Bit 6: Initialization Trigger Enable */ #define FTM_EXTTRIG_TRIGF (1 << 7) /* Bit 7: Channel Trigger Flag */ /* Bits 8-31: Reserved */ + /* Channels Polarity */ #define FTM_POL(n) (1 << (n)) /* Channel (n) Polarity, n=0..7 */ - /* Bits 8-31: Reserved */ + /* Bits 8-31: Reserved */ /* Fault Mode Status */ @@ -424,6 +438,7 @@ #define FTM_FMS_WPEN (1 << 6) /* Bit 6: Write Protection Enable */ #define FTM_FMS_FAULTF (1 << 7) /* Bit 7: Fault Detection Flag */ /* Bits 8-31: Reserved */ + /* Input Capture Filter Control */ #define FTM_FILTER_CH0FVAL_SHIFT (0) /* Bits 0-3: Channel 0 Input Filter */ @@ -435,6 +450,7 @@ #define FTM_FILTER_CH3FVAL_SHIFT (12) /* Bits 12-15: Channel 3 Input Filter */ #define FTM_FILTER_CH3FVAL_MASK (15 << FTM_FILTER_CH3FVAL_SHIFT) /* Bits 16-31: Reserved */ + /* Fault Control */ #define FTM_FLTCTRL_FAULT0EN (1 << 0) /* Bit 0: Fault Input 0 Enable */ @@ -448,6 +464,7 @@ #define FTM_FLTCTRL_FFVAL_SHIFT (8) /* Bits 8-11: Fault Input Filter */ #define FTM_FLTCTRL_FFVAL_MASK (15 << FTM_FLTCTRL_FFVAL_SHIFT) /* Bits 12-31: Reserved */ + /* Quadrature Decoder Control and Status */ #define FTM_QDCTRL_QUADEN (1 << 0) /* Bit 0: Quadrature Decoder Mode Enable */ @@ -459,6 +476,7 @@ #define FTM_QDCTRL_PHBFLTREN (1 << 6) /* Bit 6: Phase B Input Filter Enable */ #define FTM_QDCTRL_PHAFLTREN (1 << 7) /* Bit 7: Phase A Input Filter Enable */ /* Bits 8-31: Reserved */ + /* Configuration */ #define FTM_CONF_NUMTOF_SHIFT (0) /* Bits 0-4: TOF Frequency */ @@ -470,6 +488,7 @@ #define FTM_CONF_GTBEEN (1 << 9) /* Bit 9: Global time base enable */ #define FTM_CONF_GTBEOUT (1 << 10) /* Bit 10: Global time base output */ /* Bits 11-31: Reserved */ + /* FTM Fault Input Polarity */ #define FTM_FLTPOL_FLT0POL (1 << 0) /* Bit 0: Fault Input 0 Polarity */ @@ -477,6 +496,7 @@ #define FTM_FLTPOL_FLT2POL (1 << 2) /* Bit 2: Fault Input 2 Polarity */ #define FTM_FLTPOL_FLT3POL (1 << 3) /* Bit 3: Fault Input 3 Polarity */ /* Bits 4-31: Reserved */ + /* Synchronization Configuration */ #define FTM_SYNCONF_HWTRIGMODE (1 << 0) /* Bit 0: Hardware Trigger Mode */ @@ -499,6 +519,7 @@ #define FTM_SYNCONF_HWINVC (1 << 19) /* Bit 19: Inverting control synchronization (H/W) */ #define FTM_SYNCONF_HWSOC (1 << 20) /* Bit 20: Software output control synchronization (H/W) */ /* Bits 21-31: Reserved */ + /* FTM Inverting Control */ #define FTM_INVCTRL_INV0EN (1 << 0) /* Bit 0: Pair Channels 0 Inverting Enable */ @@ -506,9 +527,11 @@ #define FTM_INVCTRL_INV2EN (1 << 2) /* Bit 2: Pair Channels 2 Inverting Enable */ #define FTM_INVCTRL_INV3EN (1 << 3) /* Bit 3: Pair Channels 3 Inverting Enable */ /* Bits 4-31: Reserved */ + /* FTM Software Output Control */ #define FTM_SWOCTRL_CHOC(n) (1 << (n)) /* Bits 0-7: Channel (n) Software Output Control Enable */ + #define FTM_SWOCTRL_CH0OC (1 << 0) /* Bit 0: Channel 0 Software Output Control Enable */ #define FTM_SWOCTRL_CH1OC (1 << 1) /* Bit 1: Channel 1 Software Output Control Enable */ #define FTM_SWOCTRL_CH2OC (1 << 2) /* Bit 2: Channel 2 Software Output Control Enable */ @@ -517,7 +540,9 @@ #define FTM_SWOCTRL_CH5OC (1 << 5) /* Bit 5: Channel 5 Software Output Control Enable */ #define FTM_SWOCTRL_CH6OC (1 << 6) /* Bit 6: Channel 6 Software Output Control Enable */ #define FTM_SWOCTRL_CH7OC (1 << 7) /* Bit 7: Channel 7 Software Output Control Enable */ + #define FTM_SWOCTRL_CHOCV(n) (1 << ((n)+8)) /* Bits 8-15: Channel (n) Software Output Control Value */ + #define FTM_SWOCTRL_CH0OCV (1 << 8) /* Bit 8: Channel 0 Software Output Control Value */ #define FTM_SWOCTRL_CH1OCV (1 << 9) /* Bit 9: Channel 1 Software Output Control Value */ #define FTM_SWOCTRL_CH2OCV (1 << 10) /* Bit 10: Channel 2 Software Output Control Value */ @@ -527,6 +552,7 @@ #define FTM_SWOCTRL_CH6OCV (1 << 14) /* Bit 14: Channel 6 Software Output Control Value */ #define FTM_SWOCTRL_CH7OCV (1 << 15) /* Bit 15: Channel 7 Software Output Control Value */ /* Bits 16-31: Reserved */ + /* FTM PWM Load */ #define FTM_PWMLOAD_CHSEL(n) (1 << (n)) /* Bits 0-7: Channel (n) Select */ @@ -542,16 +568,16 @@ #define FTM_PWMLOAD_LDOK (1 << 9) /* Bit 9: Load Enable */ /* Bits 10-31: Reserved */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_gpio.h b/arch/arm/src/kinetis/hardware/kinetis_gpio.h index f3683ccc01..35c3d3ebd7 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_gpio.h +++ b/arch/arm/src/kinetis/hardware/kinetis_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output Register */ #define KINETIS_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output Register */ @@ -42,7 +42,7 @@ #define KINETIS_GPIO_PDIR_OFFSET 0x0010 /* Port Data Input Register */ #define KINETIS_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_GPIO_PDOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PDOR_OFFSET) #define KINETIS_GPIO_PSOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PSOR_OFFSET) @@ -86,7 +86,7 @@ #define KINETIS_GPIOE_PDIR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDIR_OFFSET) #define KINETIS_GPIOE_PDDR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDDR_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Port Data Output Register */ @@ -112,16 +112,16 @@ #define GPIO_PDDR(n) (1 << (n)) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_i2c.h b/arch/arm/src/kinetis/hardware/kinetis_i2c.h index 75a55fd333..6757727069 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_i2c.h +++ b/arch/arm/src/kinetis/hardware/kinetis_i2c.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_I2C_A1_OFFSET 0x0000 /* I2C Address Register 1 */ #define KINETIS_I2C_F_OFFSET 0x0001 /* I2C Frequency Divider register */ @@ -48,7 +48,7 @@ #define KINETIS_I2C_SLTH_OFFSET 0x000a /* I2C SCL Low Timeout Register High */ #define KINETIS_I2C_SLTL_OFFSET 0x000b /* I2C SCL Low Timeout Register Low */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_I2C0_A1 (KINETIS_I2C0_BASE+KINETIS_I2C_A1_OFFSET) #define KINETIS_I2C0_F (KINETIS_I2C0_BASE+KINETIS_I2C_F_OFFSET) @@ -93,9 +93,10 @@ # define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET) #endif -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* I2C Address Register 1 (8-bit) */ + /* Bit 0: Reserved */ #define I2C_A1_SHIFT (1) /* Bits 1-7: Address */ #define I2C_A1_MASK (0x7f << I2C_A1_SHIFT) @@ -111,8 +112,9 @@ # define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT) # define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT) -/* From Table 51-54. I2C divider and hold values. Duplicate divider values differ in hold - * times. Refer to the Table 51-54. in the K64 Sub-Family Reference Manual. +/* From Table 51-54. I2C divider and hold values. + * Duplicate divider values differ in hold times. + * Refer to the Table 51-54. in the K64 Sub-Family Reference Manual. */ #define I2C_F_DIV20 ((uint8_t)0x00) @@ -243,6 +245,7 @@ #endif /* I2C Range Address register (8-bit) */ + /* Bit 0: Reserved */ #define I2C_RA_SHIFT (1) /* Bits 1-7: Range slave address */ #define I2C_RA_MASK (0x7f << I2C_RA_SHIFT) @@ -259,22 +262,25 @@ #define I2C_SMB_FACK (1 << 7) /* Bit 7: Fast NACK/ACK enable */ /* I2C Address Register 2 (8-bit) */ + /* Bit 0: Reserved */ #define I2C_A2_SHIFT (1) /* Bits 1-7: SMBus address */ #define I2C_A2_MASK (0x7f << I2C_A2_SHIFT) -/* I2C SCL Low Timeout Register High/Low (16-bit data in two 8-bit registers) */ +/* I2C SCL Low Timeout Register High/Low + * (16-bit data in two 8-bit registers) + */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_i2s.h b/arch/arm/src/kinetis/hardware/kinetis_i2s.h index 7ebd37ea2b..ebdab3bad5 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_i2s.h +++ b/arch/arm/src/kinetis/hardware/kinetis_i2s.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_i2s.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_I2S_TX0_OFFSET 0x000 /* I2S Transmit Data Registers 0 */ #define KINETIS_I2S_TX1_OFFSET 0x004 /* I2S Transmit Data Registers 1 */ @@ -57,7 +57,7 @@ #define KINETIS_I2S_ACCEN_OFFSET 0x054 /* I2S AC97 Channel Enable Register */ #define KINETIS_I2S_ACCDIS_OFFSET 0x058 /* I2S AC97 Channel Disable Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_I2S0_TX0 (KINETIS_I2S0_BASE+KINETIS_I2S_TX0_OFFSET) #define KINETIS_I2S0_TX1 (KINETIS_I2S0_BASE+KINETIS_I2S_TX1_OFFSET) @@ -81,9 +81,11 @@ #define KINETIS_I2S0_ACCEN (KINETIS_I2S0_BASE+KINETIS_I2S_ACCEN_OFFSET) #define KINETIS_I2S0_ACCDIS (KINETIS_I2S0_BASE+KINETIS_I2S_ACCDIS_OFFSET) -/* Register Bit Definitions *************************************************************************/ +/* Register Bit Definitions *************************************************/ -/* I2S Transmit Data Registers 0/1 and I2S Receive Data Registers 0/1: 32-bit I2S data */ +/* I2S Transmit Data Registers 0/1 and + * I2S Receive Data Registers 0/1: 32-bit I2S data + */ /* I2S Control Register */ @@ -97,6 +99,7 @@ # define I2S_CR_I2SMODE_NORMAL (0 << I2S_CR_I2SMODE_SHIFT) /* Normal mode */ # define I2S_CR_I2SMODE_MASTER (1 << I2S_CR_I2SMODE_SHIFT) /* I2S master mode */ # define I2S_CR_I2SMODE_SLAVE (2 << I2S_CR_I2SMODE_SHIFT) /* I2S slave mode */ + #define I2S_CR_SYSCLKEN (1 << 7) /* Bit 7: System Clock (Oversampling Clock) Enable */ #define I2S_CR_TCHEN (1 << 8) /* Bit 8: Two-Channel Operation Enable */ #define I2S_CR_CLKIST (1 << 9) /* Bit 9: Clock Idle */ @@ -104,7 +107,10 @@ #define I2S_CR_RFRCLKDIS (1 << 11) /* Bit 11: Receive Frame Clock Disable */ #define I2S_CR_SYNCTXFS (1 << 12) /* Bit 12: CR[TE] latched with FS occurrence */ /* Bits 13-31: Reserved */ -/* I2S Interrupt Status Register and I2S Interrupt Enable Register common bit definitions */ + +/* I2S Interrupt Status Register and I2S Interrupt Enable Register + * common bit definitions + */ #define I2S_INT_TFE0 (1 << 0) /* Bit 0: Transmit FIFO Empty 0 */ #define I2S_INT_TFE1 (1 << 1) /* Bit 1: Transmit FIFO Empty 1 */ @@ -129,15 +135,23 @@ #define I2S_INT_TRFC (1 << 23) /* Bit 23: Transmit Frame Complete */ #define I2S_INT_RFRC (1 << 24) /* Bit 24: Receive Frame Complete */ /* Bits 25-31: Reserved */ + /* I2S Interrupt Status Register (see common definitions above) */ -/* I2S Interrupt Enable Register (see common definitions above and unique definitions below)*/ - /* Bits 0-18: See common definitions above */ + +/* I2S Interrupt Enable Register + * (see common definitions above and unique definitions below) + */ + +/* Bits 0-18: + * See common definitions above + */ #define I2S_IER_TIE (1 << 19) /* Bit 19: Transmit Interrupt Enable */ #define I2S_IER_TDMAE (1 << 20) /* Bit 20: Transmit DMA Enable */ #define I2S_IER_RIE (1 << 21) /* Bit 21: Receive Interrupt Enable */ #define I2S_IER_RDMAE (1 << 22) /* Bit 22: Receive DMA Enable */ /* Bits 23-24: See common definitions above */ /* Bits 25-31: Reserved */ + /* I2S Transmit Configuration Register */ #define I2S_TCR_TEFS (1 << 0) /* Bit 0: Transmit Early Frame Sync */ @@ -151,6 +165,7 @@ #define I2S_TCR_TFEN1 (1 << 8) /* Bit 8: Transmit FIFO Enable 1 */ #define I2S_TCR_TXBIT0 (1 << 9) /* Bit 9: Transmit Bit 0 */ /* Bits 10-31: Reserved */ + /* I2S Receive Configuration Register */ #define I2S_RCR_REFS (1 << 0) /* Bit 0: Receive Early Frame Sync */ @@ -165,6 +180,7 @@ #define I2S_RCR_RXBIT0 (1 << 9) /* Bit 9: Receive Bit 0 */ #define I2S_RCR_RXEXT (1 << 10) /* Bit 10: Receive Data Extension */ /* Bits 11-31: Reserved */ + /* I2S Transmit Clock Control Registers */ #define I2S_TCCR_PM_SHIFT (0) /* Bits 0-7: Prescaler Modulus Select */ @@ -184,6 +200,7 @@ #define I2S_TCCR_PSR (1 << 17) /* Bit 17: Prescaler Range */ #define I2S_TCCR_DIV2 (1 << 18) /* Bit 18: Divide By 2 */ /* Bits 19-31: Reserved */ + /* I2S Receive Clock Control Registers */ #define I2S_RCCR_PM_SHIFT (0) /* Bits 0-7: Prescaler Modulus Select */ @@ -203,6 +220,7 @@ #define I2S_RCCR_PSR (1 << 17) /* Bit 17: Prescaler Range */ #define I2S_RCCR_DIV2 (1 << 18) /* Bit 18: Divide By 2 */ /* Bits 19-31: Reserved */ + /* I2S FIFO Control/Status Register */ #define I2S_FCSR_TFWM0_SHIFT (0) /* Bits 0-3: Transmit FIFO Empty WaterMark 0 */ @@ -232,22 +250,27 @@ #define I2S_ACNT_FRDIV_SHIFT (5) /* Bits 5-10: Frame Rate Divider */ #define I2S_ACNT_FRDIV_MASK (63 << I2S_ACNT_FRDIV_SHIFT) /* Bits 11-31: Reserved */ + /* I2S AC97 Command Address Register */ #define I2S_ACADD_ACADD_SHIFT (0) /* Bits 0-18: AC97 Command Address */ #define I2S_ACADD_ACADD_MASK (0x7ffff << I2S_ACADD_ACADD_SHIFT) /* Bits 19-31: Reserved */ + /* I2S AC97 Command Data Register */ #define I2S_ACDAT_ACADD_SHIFT (0) /* Bits 0-18: AC97 Command Data */ #define I2S_ACDAT_ACADD_MASK (0x7ffff << I2S_ACDAT_ACADD_SHIFT) /* Bits 19-31: Reserved */ + /* I2S AC97 Tag Register */ #define I2S_ATAG_ACADD_SHIFT (0) /* Bits 0-15: AC97 Tag Value */ #define I2S_ATAG_ACADD_MASK (0xffff << I2S_ACDAT_ACADD_SHIFT) /* Bits 16-31: Reserved */ + /* I2S Transmit Time Slot Mask Register (32-bit Transmit Mask) */ + /* I2S Receive Time Slot Mask Register (32-bit Receive Mask) */ /* I2S AC97 Channel Status Register */ @@ -255,11 +278,13 @@ #define I2S_ACCST_ACCST_SHIFT (0) /* Bits 0-9: AC97 Channel Status */ #define I2S_ACCST_ACCST_MASK (0x3ff << I2S_ACCST_ACCST_SHIFT) /* Bits 10-31: Reserved */ + /* I2S AC97 Channel Enable Register */ #define I2S_ACCEN_ACCST_SHIFT (0) /* Bits 0-9: AC97 Channel Enable */ #define I2S_ACCEN_ACCST_MASK (0x3ff << I2S_ACCEN_ACCST_SHIFT) /* Bits 10-31: Reserved */ + /* I2S AC97 Channel Disable Register */ #define I2S__ @@ -267,16 +292,16 @@ #define I2S_ACCDIS_ACCST_MASK (0x3ff << I2S_ACCEN_ACCST_SHIFT) /* Bits 10-31: Reserved */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h index 9faad50c54..473dd43a49 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */ #define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */ @@ -152,7 +152,7 @@ #define KINETIS_FMC_DATAW3S7U_OFFSET 0x02f8 /* Cache Data Storage (upper word) */ #define KINETIS_FMC_DATAW3S7L_OFFSET 0x02fc /* Cache Data Storage (lower word) */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET) #define KINETIS_FMC_PFB0CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB0CR_OFFSET) @@ -271,9 +271,10 @@ #define KINETIS_FMC_DATAW3S7U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S7U_OFFSET) #define KINETIS_FMC_DATAW3S7L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S7L_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Flash Access Protection Register */ + /* Access protection bits (all masters) */ #define FMC_PFAPR_NONE 0 /* No access may be performed by this master */ @@ -305,7 +306,9 @@ #define FMC_PFAPR_M5PFD (1 << 21) /* Bit 21: Master 5 Prefetch Disable */ #define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */ #define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */ + /* Bits 24-31: Reserved */ + /* Flash Bank 0 Control Register */ #define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */ @@ -318,11 +321,13 @@ # define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */ # define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */ # define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */ + /* Bits 8-16: Reserved */ #define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */ #define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT) # define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */ # define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */ + #define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */ #define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */ #define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT) @@ -343,6 +348,7 @@ #define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT) # define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */ # define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */ + /* Bits 19-27: Reserved */ #define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */ #define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT) @@ -353,22 +359,23 @@ /* Bits 1-5: Reserved */ #define FMC_TAGVD_TAG_SHIFT (6) /* Bits 6-18: 13-bit tag for cache entry */ #define FMC_TAGVD_TAG_MASK (0x1fff << FMC_TAGVD_TAG_SHIFT) + /* Bits 19-31: Reserved */ /* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7. * 64-bit data in two 32-bit registers. */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h index 2ffc414a9a..2a4a08d547 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */ @@ -137,7 +137,7 @@ #define KINETIS_MPU_RGDAAC14_OFFSET 0x0838 /* Region Descriptor Alternate Access Control 14 */ #define KINETIS_MPU_RGDAAC15_OFFSET 0x083c /* Region Descriptor Alternate Access Control 15 */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET) @@ -241,7 +241,7 @@ #define KINETIS_MPU_RGDAAC14 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC14_OFFSET) #define KINETIS_MPU_RGDAAC15 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC15_OFFSET) -/* Register Bit Definitions *************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Control/Error Status Register */ @@ -252,6 +252,7 @@ # define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */ # define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */ # define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */ + #define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */ #define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT) #define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */ @@ -260,6 +261,7 @@ #define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */ #define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT) # define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */ + # define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */ # define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */ # define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */ @@ -277,6 +279,7 @@ # define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */ # define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */ # define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */ + #define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */ #define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT) /* Bits 8-15: Reserved */ @@ -284,11 +287,13 @@ #define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT) /* Region Descriptor n, Word 0 */ + /* Bits 0-4: Reserved */ #define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */ #define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0) /* Region Descriptor n, Word 1 */ + /* Bits 0-4: Reserved */ #define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */ #define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0) @@ -337,6 +342,7 @@ #define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */ /* Bits 1-31: Reserved */ + /* Region Descriptor Alternate Access Control n */ #define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */ @@ -368,16 +374,16 @@ #define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */ #define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h index a5bff46388..01ff1d0cfb 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,12 @@ #ifdef KINETIS_K20 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Memory Map ***************************************************************/ -/* Memory Map ***********************************************************************/ /* K20 Family * * The memory map for the following parts is defined in Freescale document @@ -49,13 +50,16 @@ # define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */ # define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */ #endif + /* 0x18000000 * –0x1bffffff Reserved */ #define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM * (ICODE/DCODE) */ #define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband * region */ + /* 0x20100000 * –0x21ffffff Reserved */ #define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * –0x3fffffff Reserved */ #define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral * bridge 0 (AIPS-Lite0) */ @@ -63,15 +67,18 @@ * bridge 1 (AIPS-Lite1) */ #define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general * purpose input/output (GPIO) */ + /* 0x40100000 * –0x41ffffff Reserved */ #define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge * (AIPS-Lite) and general purpose * input/output (GPIO) bitband */ + /* 0x44000000 * –0xdfffffff Reserved */ #define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */ + /* 0xe0100000 * –0xffffffff Reserved */ -/* Peripheral Bridge 0 Memory Map ***************************************************/ +/* Peripheral Bridge 0 Memory Map *******************************************/ #define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ #define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ @@ -121,7 +128,7 @@ #define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ #define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ -/* Peripheral Bridge 1 Memory Map ***************************************************/ +/* Peripheral Bridge 1 Memory Map *******************************************/ #define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ #define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ @@ -139,7 +146,7 @@ #define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ #define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ +/* Private Peripheral Bus (PPB) Memory Map **********************************/ #define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ #define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ @@ -149,17 +156,17 @@ #define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ #define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_K20 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h index 78b73e36e4..f44f631f1c 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h @@ -1,4 +1,4 @@ -/****************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ******************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H -/****************************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,11 @@ #ifdef KINETIS_K28 -/****************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************************/ + ****************************************************************************/ -/* Memory Map *****************************************************************************/ +/* Memory Map ***************************************************************/ /* K28 Family * @@ -90,7 +90,7 @@ * External Peripheral - Not executable) */ # define KINETIS_PERIPH_BASE 0xe0000000 /* Private peripherals */ -/* Peripheral Bridge 0 Memory Map *********************************************************/ +/* Peripheral Bridge 0 Memory Map *******************************************/ # define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ @@ -147,7 +147,7 @@ # define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ # define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ -/* Peripheral Bridge 1 Memory Map *********************************************************/ +/* Peripheral Bridge 1 Memory Map *******************************************/ # define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ # define KINETIS_RNGA_BASE 0x400a0000 /* True Random Number Generator (TRNG) */ @@ -185,7 +185,7 @@ # define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ # define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ -/* Private Peripheral Bus (PPB) Memory Map ************************************************/ +/* Private Peripheral Bus (PPB) Memory Map **********************************/ # define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ # define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ @@ -202,10 +202,10 @@ * of debug components */ #else - /* The memory map for other parts is defined in other documents and may or may not - * be the same as above (the family members are all very similar) This error just - * means that you have to look at the document and determine for yourself if the - * memory map is the same. + /* The memory map for other parts is defined in other documents and may or + * may not be the same as above (the family members are all very similar) + * This error just means that you have to look at the document and + * determine for yourself if the memory map is the same. */ # error "No memory map for this K28 part" diff --git a/arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h index 75ef6d8343..b3382310de 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -31,19 +31,20 @@ #ifdef KINETIS_K28 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin * configuration (with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in the initial version of this file. + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in the initial version of this file. */ /* ADC */ @@ -802,17 +803,17 @@ #define PIN_USB1_ID (PIN_ALT7 | PIN_PORTA | PIN11) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_K28 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h index c6e17b463f..ea1181bf43 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,12 @@ #ifdef KINETIS_K40 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Memory Map ***************************************************************/ -/* Memory Map ***********************************************************************/ /* K40 Family * * The memory map for the following parts is defined in Freescale document @@ -53,8 +54,10 @@ * (ICODE/DCODE) */ #define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband * region */ + /* 0x20100000 * -0x21ffffff Reserved */ #define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x3fffffff Reserved */ #define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral * bridge 0 (AIPS-Lite0) */ @@ -62,10 +65,12 @@ * bridge 1 (AIPS-Lite1) */ #define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ #define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge * (AIPS-Lite) and general purpose * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ #define KINETIS_FLEXBUS_WBBASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - * Write-back) */ @@ -74,9 +79,10 @@ #define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* -0xdfffffff FlexBus (External Memory - * Non-executable) */ #define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ -/* Peripheral Bridge 0 Memory Map ***************************************************/ +/* Peripheral Bridge 0 Memory Map *******************************************/ #define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ #define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ @@ -131,7 +137,7 @@ #define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ #define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ -/* Peripheral Bridge 1 Memory Map ***************************************************/ +/* Peripheral Bridge 1 Memory Map *******************************************/ #define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ #define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ @@ -155,7 +161,7 @@ #define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ #define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ +/* Private Peripheral Bus (PPB) Memory Map **********************************/ #define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ #define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ @@ -168,17 +174,17 @@ #define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ #define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_K40 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h index 019af34ca8..ab2299156a 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,12 @@ #ifdef KINETIS_K60 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Memory Map ***************************************************************/ -/* Memory Map ***********************************************************************/ /* K60 Family * * The memory map for the following parts is defined in Freescale document @@ -53,25 +54,30 @@ * (ICODE/DCODE) */ #define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband * region */ + /* 0x20100000 * -0x21ffffff Reserved */ #define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x3fffffff Reserved */ #define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral * bridge 0 (AIPS-Lite0) */ -#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral +#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral * bridge 1 (AIPS-Lite1) */ #define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ #define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge * (AIPS-Lite) and general purpose * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ #define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */ #define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ -/* Peripheral Bridge 0 Memory Map ***************************************************/ +/* Peripheral Bridge 0 Memory Map *******************************************/ #define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ #define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ @@ -126,7 +132,7 @@ #define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ #define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ -/* Peripheral Bridge 1 Memory Map ***************************************************/ +/* Peripheral Bridge 1 Memory Map *******************************************/ #define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ #define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ @@ -151,7 +157,7 @@ #define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ #define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ +/* Private Peripheral Bus (PPB) Memory Map **********************************/ #define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ #define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ @@ -165,17 +171,17 @@ #define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ #define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_K60 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k64fmc.h b/arch/arm/src/kinetis/hardware/kinetis_k64fmc.h index 012962a552..82039effcf 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k64fmc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k64fmc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k64fmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */ #define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */ @@ -104,7 +104,7 @@ #define KINETIS_FMC_DATAW3S3U_OFFSET 0x0278 /* Cache Data Storage (upper word) */ #define KINETIS_FMC_DATAW3S3L_OFFSET 0x027c /* Cache Data Storage (lower word) */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET) #define KINETIS_FMC_PFB0CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB0CR_OFFSET) @@ -175,9 +175,10 @@ #define KINETIS_FMC_DATAW3S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3U_OFFSET) #define KINETIS_FMC_DATAW3S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3L_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Flash Access Protection Register */ + /* Access protection bits (all masters) */ #define FMC_PFAPR_NONE 0 /* No access may be performed by this master */ @@ -210,6 +211,7 @@ #define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */ #define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */ /* Bits 24-31: Reserved */ + /* Flash Bank 0 Control Register */ #define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */ @@ -222,11 +224,13 @@ # define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */ # define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */ # define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */ + /* Bits 8-16: Reserved */ #define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */ #define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT) # define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */ # define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */ + #define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */ #define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */ #define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT) @@ -247,6 +251,7 @@ #define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT) # define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */ # define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */ + /* Bits 19-27: Reserved */ #define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */ #define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT) @@ -263,16 +268,16 @@ * 64-bit data in two 32-bit registers. */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h index ce77839ec4..b6d6ff3a91 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,12 @@ #ifdef KINETIS_K64 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Memory Map ***************************************************************/ -/* Memory Map ***********************************************************************/ /* K64 Family * * The memory map for the following parts is defined in NXP document @@ -58,8 +59,10 @@ * (ICODE/DCODE) */ # define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband * region */ + /* 0x20100000 * -0x21ffffff Reserved */ # define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x3fffffff Reserved */ # define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral * bridge 0 (AIPS-Lite0) */ @@ -67,16 +70,19 @@ * bridge 1 (AIPS-Lite1) */ # define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ # define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge * (AIPS-Lite) and general purpose * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ # define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */ # define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ -/* Peripheral Bridge 0 Memory Map ***************************************************/ +/* Peripheral Bridge 0 Memory Map *******************************************/ # define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ @@ -132,7 +138,7 @@ # define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ # define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ -/* Peripheral Bridge 1 Memory Map ***************************************************/ +/* Peripheral Bridge 1 Memory Map *******************************************/ # define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ # define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ @@ -158,7 +164,7 @@ # define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ # define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ +/* Private Peripheral Bus (PPB) Memory Map **********************************/ # define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ # define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ @@ -173,26 +179,26 @@ # define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ #else - /* The memory map for other parts is defined in other documents and may or may not - * be the same as above (the family members are all very similar) This error just - * means that you have to look at the document and determine for yourself if the - * memory map is the same. + /* The memory map for other parts is defined in other documents and may or + * may not be the same as above (the family members are all very similar) + * This error just means that you have to look at the document and + * determine for yourself if the memory map is the same. */ # error "No memory map for this K64 part" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_K64 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_llwu.h b/arch/arm/src/kinetis/hardware/kinetis_llwu.h index 45c78f7942..e9634a6cce 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_llwu.h +++ b/arch/arm/src/kinetis/hardware/kinetis_llwu.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_llwu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_LLWU_PE1_OFFSET 0x0000 /* LLWU Pin Enable 1 Register */ #define KINETIS_LLWU_PE2_OFFSET 0x0001 /* LLWU Pin Enable 2 Register */ @@ -45,7 +45,7 @@ #define KINETIS_LLWU_F3_OFFSET 0x0007 /* LLWU Flag 3 Register */ #define KINETIS_LLWU_CS_OFFSET 0x0008 /* LLWU Control and Status Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_LLWU_PE1 (KINETIS_LLWU_BASE+KINETIS_LLWU_PE1_OFFSET) #define KINETIS_LLWU_PE2 (KINETIS_LLWU_BASE+KINETIS_LLWU_PE2_OFFSET) @@ -57,7 +57,7 @@ #define KINETIS_LLWU_F3 (KINETIS_LLWU_BASE+KINETIS_LLWU_F3_OFFSET) #define KINETIS_LLWU_CS (KINETIS_LLWU_BASE+KINETIS_LLWU_CS_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* LLWU Pin Enable 1 Register */ @@ -67,18 +67,21 @@ # define LLWU_PE1_WUPE0_RISING (1 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE1_WUPE0_FALLING (2 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE1_WUPE0_BOTH (3 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE1_WUPE1_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P1 */ #define LLWU_PE1_WUPE1_MASK (3 << LLWU_PE1_WUPE1_SHIFT) # define LLWU_PE1_WUPE1_DISABLED (0 << LLWU_PE1_WUPE1_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE1_WUPE1_RISING (1 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE1_WUPE1_FALLING (2 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE1_WUPE1_BOTH (3 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE1_WUPE2_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P2 */ #define LLWU_PE1_WUPE2_MASK (3 << LLWU_PE1_WUPE2_SHIFT) # define LLWU_PE1_WUPE2_DISABLED (0 << LLWU_PE1_WUPE2_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE1_WUPE2_RISING (1 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE1_WUPE2_FALLING (2 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE1_WUPE2_BOTH (3 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE1_WUPE3_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P3 */ #define LLWU_PE1_WUPE3_MASK (3 << LLWU_PE1_WUPE3_SHIFT) # define LLWU_PE1_WUPE3_DISABLED (0 << LLWU_PE1_WUPE3_SHIFT) /* Ext input disabled as wakeup input */ @@ -94,18 +97,21 @@ # define LLWU_PE2_WUPE4_RISING (1 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE2_WUPE4_FALLING (2 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE2_WUPE4_BOTH (3 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE2_WUPE5_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P5 */ #define LLWU_PE2_WUPE5_MASK (3 << LLWU_PE2_WUPE5_SHIFT) # define LLWU_PE2_WUPE5_DISABLED (0 << LLWU_PE2_WUPE5_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE2_WUPE5_RISING (1 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE2_WUPE5_FALLING (2 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE2_WUPE5_BOTH (3 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE2_WUPE6_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P6 */ #define LLWU_PE2_WUPE6_MASK (3 << LLWU_PE2_WUPE6_SHIFT) # define LLWU_PE2_WUPE6_DISABLED (0 << LLWU_PE2_WUPE6_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE2_WUPE6_RISING (1 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE2_WUPE6_FALLING (2 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE2_WUPE6_BOTH (3 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE2_WUPE7_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P7 */ #define LLWU_PE2_WUPE7_MASK (3 << LLWU_PE2_WUPE7_SHIFT) # define LLWU_PE2_WUPE7_DISABLED (0 << LLWU_PE2_WUPE7_SHIFT) /* Ext input disabled as wakeup input */ @@ -121,18 +127,21 @@ # define LLWU_PE3_WUPE8_RISING (1 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE3_WUPE8_FALLING (2 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE3_WUPE8_BOTH (3 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE3_WUPE9_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P9 */ #define LLWU_PE3_WUPE9_MASK (3 << LLWU_PE3_WUPE9_SHIFT) # define LLWU_PE3_WUPE9_DISABLED (0 << LLWU_PE3_WUPE9_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE3_WUPE9_RISING (1 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE3_WUPE9_FALLING (2 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE3_WUPE9_BOTH (3 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE3_WUPE10_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P10 */ #define LLWU_PE3_WUPE10_MASK (3 << LLWU_PE3_WUPE10_SHIFT) # define LLWU_PE3_WUPE10_DISABLED (0 << LLWU_PE3_WUPE10_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE3_WUPE10_RISING (1 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE3_WUPE10_FALLING (2 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE3_WUPE10_BOTH (3 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE3_WUPE11_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P11 */ #define LLWU_PE3_WUPE11_MASK (3 << LLWU_PE3_WUPE11_SHIFT) # define LLWU_PE3_WUPE11_DISABLED (0 << LLWU_PE3_WUPE11_SHIFT) /* Ext input disabled as wakeup input */ @@ -148,18 +157,21 @@ # define LLWU_PE4_WUPE12_RISING (1 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE4_WUPE12_FALLING (2 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE4_WUPE12_BOTH (3 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE4_WUPE13_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P13 */ #define LLWU_PE4_WUPE13_MASK (3 << LLWU_PE4_WUPE13_SHIFT) # define LLWU_PE4_WUPE13_DISABLED (0 << LLWU_PE4_WUPE13_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE4_WUPE13_RISING (1 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE4_WUPE13_FALLING (2 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE4_WUPE13_BOTH (3 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE4_WUPE14_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P14 */ #define LLWU_PE4_WUPE14_MASK (3 << LLWU_PE4_WUPE14_SHIFT) # define LLWU_PE4_WUPE14_DISABLED (0 << LLWU_PE4_WUPE14_SHIFT) /* Ext input disabled as wakeup input */ # define LLWU_PE4_WUPE14_RISING (1 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for rising edge */ # define LLWU_PE4_WUPE14_FALLING (2 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for falling edge */ # define LLWU_PE4_WUPE14_BOTH (3 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for any change */ + #define LLWU_PE4_WUPE15_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P15 */ #define LLWU_PE4_WUPE15_MASK (3 << LLWU_PE4_WUPE15_SHIFT) # define LLWU_PE4_WUPE15_DISABLED (0 << LLWU_PE4_WUPE15_SHIFT) /* Ext input disabled as wakeup input */ @@ -224,16 +236,16 @@ #define LLWU_CS_FLTEP (1 << 1) /* Bit 1: Digital Filter on External Pin */ #define LLWU_CS_FLTR (1 << 0) /* Bit 0: Digital Filter on RESET Pin */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_lptmr.h b/arch/arm/src/kinetis/hardware/kinetis_lptmr.h index 3bb5d19adf..581bf8e698 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_lptmr.h +++ b/arch/arm/src/kinetis/hardware/kinetis_lptmr.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_lptmr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_LPTMR_CSR_OFFSET 0x0000 /* Low Power Timer Control Status Register */ #define KINETIS_LPTMR_PSR_OFFSET 0x0004 /* Low Power Timer Prescale Register */ #define KINETIS_LPTMR_CMR_OFFSET 0x0008 /* Low Power Timer Compare Register */ #define KINETIS_LPTMR_CNR_OFFSET 0x000c /* Low Power Timer Counter Register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_LPTMR0_CSR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_CSR_OFFSET) #define KINETIS_LPTMR0_PSR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_PSR_OFFSET) @@ -52,7 +52,7 @@ #define KINETIS_LPTMR1_CMR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CMR_OFFSET) #define KINETIS_LPTMR1_CNR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CNR_OFFSET) -/* Register Bit Definitions *************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Low Power Timer Control Status Register (32-bit) */ @@ -66,6 +66,7 @@ # define LPTMR_CSR_TPS_INPUT1 (1 << LPTMR_CSR_TPS_SHIFT) /* Pulse counter input 1 selected */ # define LPTMR_CSR_TPS_INPUT2 (2 << LPTMR_CSR_TPS_SHIFT) /* Pulse counter input 2 selected */ # define LPTMR_CSR_TPS_INPUT3 (3 << LPTMR_CSR_TPS_SHIFT) /* Pulse counter input 3 selected */ + #define LPTMR_CSR_TIE (1 << 6) /* Bit 6: Timer Interrupt Enable */ #define LPTMR_CSR_TCF (1 << 7) /* Bit 7: Timer Compare Flag */ @@ -77,8 +78,10 @@ # define LPTMR_PSR_PCS_CLOCK (1 << LPTMR_PSR_PCS_SHIFT) /* Prescaler/glitch filter clock 1 */ # define LPTMR_PSR_PCS_CLOCK (2 << LPTMR_PSR_PCS_SHIFT) /* Prescaler/glitch filter clock 2 */ # define LPTMR_PSR_PCS_CLOCK (3 << LPTMR_PSR_PCS_SHIFT) /* Prescaler/glitch filter clock 3 */ + #define LPTMR_PSR_PBYP (1 << 2) /* Bit 2: Prescaler Bypass */ #define LPTMR_PSR_PRESCALE_SHIFT (6) /* Bits 3-6: Prescale Value */ + #define LPTMR_PSR_PRESCALE_MASK (15 << LPTMR_PSR_PRESCALE_SHIFT) /* Prescale divider: Glitch filter after: */ # define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=2 N/S */ # define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=4 2 edges */ @@ -96,28 +99,31 @@ # define LPTMR_PSR_PRESCALE_DIV16K (13 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=16384 8192 edges */ # define LPTMR_PSR_PRESCALE_DIV32K (14 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=32768 16384 edges */ # define LPTMR_PSR_PRESCALE_DIV64K (15 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=65536 32768 edges */ + /* Bits 7-31: Reserved */ + /* Low Power Timer Compare Register */ #define LPTMR_CMR_SHIFT (0) /* Bits 0-15: Compare Value */ #define LPTMR_CMR_MASK (0xffff << LPTMR_CMR_COMPARE_SHIFT) /* Bits 16-31: Reserved */ + /* Low Power Timer Counter Register */ #define LPTMR_CNR_SHIFT (0) /* Bits 0-15: Counter Value */ #define LPTMR_CNR_MASK (0xffff << LPTMR_CNR_COMPARE_SHIFT) /* Bits 16-31: Reserved */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_mcm.h b/arch/arm/src/kinetis/hardware/kinetis_mcm.h index 9722f6af7c..f564e4cb0e 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_mcm.h +++ b/arch/arm/src/kinetis/hardware/kinetis_mcm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_mcm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_MCM_PLASC_OFFSET 0x0008 /* Crossbar switch (AXBS) slave configuration */ #define KINETIS_MCM_PLAMC_OFFSET 0x000a /* Crossbar switch (AXBS) master configuration */ @@ -46,7 +46,7 @@ # define KINETIS_MCM_PID_OFFSET 0x0030 /* Process ID register */ #endif -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_MCM_PLASC (KINETIS_MCM_BASE+KINETIS_MCM_PLASC_OFFSET) #define KINETIS_MCM_PLAMC (KINETIS_MCM_BASE+KINETIS_MCM_PLAMC_OFFSET) @@ -59,7 +59,7 @@ # define KINETIS_MCM_PID (KINETIS_MCM_BASE+KINETIS_MCM_PID_OFFSET) #endif -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Crossbar switch (AXBS) slave configuration */ @@ -81,6 +81,7 @@ /* Bits 8-15: Reserved */ /* SRAM arbitration and protection */ + /* Bits 0-23: Reserved */ #define MCM_SRAMAP_SRAMUAP_SHIFT (24) /* Bits 24-25: SRAM_U arbitration priority */ #define MCM_SRAMAP_SRAMUAP_MASK (3 << MCM_SRAMAP_SRAMUAP_SHIFT) @@ -88,6 +89,7 @@ # define MCM_SRAMAP_SRAMUAP_SRR (1 << MCM_SRAMAP_SRAMUAP_SHIFT) /* Special round robin */ # define MCM_SRAMAP_SRAMUAP_FIXED1 (2 << MCM_SRAMAP_SRAMUAP_SHIFT) /* Fixed pri. Proc highest/backdoor lowest */ # define MCM_SRAMAP_SRAMUAP_FIXED2 (3 << MCM_SRAMAP_SRAMUAP_SHIFT) /* Fixed pri. Backdoor highest/proc lowest */ + #define MCM_SRAMAP_SRAMUWP (1 << 26) /* Bit 26: SRAM_U write protect */ /* Bit 27: Reserved */ #define MCM_SRAMAP_SRAMLAP_SHIFT (28) /* Bits 28-29: SRAM_L arbitration priority */ @@ -96,13 +98,17 @@ # define MCM_SRAMAP_SRAMLAP_SRR (1 << MCM_SRAMAP_SRAMLAP_SHIFT) /* Special round robin */ # define MCM_SRAMAP_SRAMLAP_FIXED1 (2 << MCM_SRAMAP_SRAMLAP_SHIFT) /* Fixed pri. Proc highest/backdoor lowest */ # define MCM_SRAMAP_SRAMLAP_FIXED2 (3 << MCM_SRAMAP_SRAMLAP_SHIFT) /* Fixed pri. Backdoor highest/proc lowest */ + #define MCM_SRAMAP_SRAMLWP (1 << 30) /* Bit 30: SRAM_L write protect */ /* Bit 31: Reserved */ + /* Interrupt status register */ + /* Bit 0: Reserved */ #define MCM_ISR_IRQ (1 << 1) /* Bit 1: Normal interrupt pending */ #define MCM_ISR_NMI (1 << 2) /* Bit 2: Non-maskable interrupt pending */ /* Bits 3-31: Reserved */ + /* ETB counter control register */ #define MCM_ETBCC_CNTEN (1 << 0) /* Bit 0: Counter enable */ @@ -112,31 +118,34 @@ # define MCM_ETBCC_RSPT_INT (1 << MCM_ETBCC_RSPT_SHIFT) /* Normal interrupt when ETB count expires */ # define MCM_ETBCC_RSPT_NMI (2 << MCM_ETBCC_RSPT_SHIFT) /* NMI when ETB count expires */ # define MCM_ETBCC_RSPT_HALT (3 << MCM_ETBCC_RSPT_SHIFT) /* Debug halt when ETB count expires */ + #define MCM_ETBCC_RLRQ (1 << 3) /* Bit 3: Reload request */ #define MCM_ETBCC_ETDIS (1 << 4) /* Bit 4: ETM-to-TPIU disable */ #define MCM_ETBCC_ITDIS (1 << 5) /* Bit 5: ITM-to-TPIU disable */ /* Bits 6-31: Reserved */ + /* ETB reload register */ #define MCM_ETBRL_RELOAD_SHIFT (0) /* Bits 0-10: Byte count reload value */ #define MCM_ETBRL_RELOAD_MASK (0x7ff << MCM_ETBRL_RELOAD_SHIFT) /* Bits 11-31: Reserved */ + /* ETB counter value register */ #define MCM_ETBCNT_COUNTER_SHIFT (0) /* Bits 0-10: Byte count counter value */ #define MCM_ETBCNT_COUNTER_MASK (0x7ff << MCM_ETBCNT_COUNTER_SHIFT) /* Bits 11-31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_memorymap.h index c21ebc0747..7c5d009251 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_memorymap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/* This file is just a wrapper around pin muxing header files for the Kinetis family selected - * by the logic in chip.h. +/* This file is just a wrapper around pin muxing header files for the Kinetis + * family selected by the logic in chip.h. */ #if defined(KINETIS_K20) @@ -49,20 +49,20 @@ # error "No memory map for this Kinetis part" #endif -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_mmcau.h b/arch/arm/src/kinetis/hardware/kinetis_mmcau.h index e36f1bf744..4a5f26c222 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_mmcau.h +++ b/arch/arm/src/kinetis/hardware/kinetis_mmcau.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_mmcau.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,11 @@ #if defined(KINETIS_NMMCAU) && KINETIS_NMMCAU > 0 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_CAU_CASR_OFFSET 0x0000 /* Status Register */ #define KINETIS_CAU_CAA_OFFSET 0x0001 /* Accumulator */ @@ -53,7 +53,7 @@ # define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */ #endif -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_CAU_CASR (KINETIS_MMCAU_BASE+KINETIS_CAU_CASR_OFFSET) #define KINETIS_CAU_CAA (KINETIS_MMCAU_BASE+KINETIS_CAU_CAA_OFFSET) @@ -71,7 +71,7 @@ # define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET) #endif -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Status Register */ @@ -81,10 +81,11 @@ #define CAU_CASR_VER_SHIFT (28) /* Bits 28-31: CAU version */ #define CAU_CASR_VER_MASK (15 << CAU_CASR_VER_SHIFT) -/* Accumulator (32-bit accumulated value)*/ +/* Accumulator (32-bit accumulated value) */ + /* General Purpose Register n (32-bit value used by CAU commands) */ -/* CAU Commands *********************************************************************/ +/* CAU Commands *************************************************************/ /* Bits 4-8 of 9-bit commands (bits 0-3 may be arguments of the command) */ @@ -112,17 +113,17 @@ #define CAU_CMD_SHS2 0x150 /* Secure Hash Shift 2 */ #define CAU_CMD_ILL 0x1f0 /* Illegal Command */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_mpu.h b/arch/arm/src/kinetis/hardware/kinetis_mpu.h index c3639a311e..77f2354c65 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_mpu.h +++ b/arch/arm/src/kinetis/hardware/kinetis_mpu.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_mpu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/* This file is just a wrapper around MPU header files for the Kinetis family selected by the - * in chip.h. +/* This file is just a wrapper around MPU header files for the Kinetis family + * selected by the in chip.h. */ #if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60) @@ -41,20 +41,20 @@ # error "No MPU definitions for this Kinetis part" #endif -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_osc.h b/arch/arm/src/kinetis/hardware/kinetis_osc.h index ecdd21ab31..5575925f1c 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_osc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_osc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_osc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,34 +16,34 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_OSC_CR_OFFSET 0x0000 /* OSC Control Register */ #define KINETIS_OSC_DIV_OFFSET 0x0002 /* OSC CLock divider register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_OSC_CR (KINETIS_OSC_BASE+KINETIS_OSC_CR_OFFSET) #define KINETIS_OSC_DIV (KINETIS_OSC_BASE+KINETIS_OSC_DIV_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* OSC Control Register (8-bit) */ @@ -57,6 +57,7 @@ #define OSC_CR_SC16P (1 << 0) /* Bit 0: Oscillator 16 pF Capacitor Load Configure */ /* OSC Control Register (8-bit) */ + /* Bits 0-5: Reserved */ #define OSC_DIV_ERPS_SHIFT 6 /* Bits 6-7: ERCLK prescaler */ #define OSC_DIV_ERPS_MASK (3 << OSC_DIV_ERPS_SHIFT) @@ -65,16 +66,16 @@ # define OSC_DIV_ERPS_DIV3 (2 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 4 */ # define OSC_DIV_ERPS_DIV8 (3 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 8 */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_pdb.h b/arch/arm/src/kinetis/hardware/kinetis_pdb.h index 36a97622e0..ee4484d4bc 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_pdb.h +++ b/arch/arm/src/kinetis/hardware/kinetis_pdb.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_pdb.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_PDB_SC_OFFSET 0x0000 /* Status and Control Register */ #define KINETIS_PDB_MOD_OFFSET 0x0004 /* Modulus Register */ @@ -41,6 +41,7 @@ #define KINETIS_PDB_IDLY_OFFSET 0x000c /* Interrupt Delay Register */ #define KINETIS_PDB_CH_OFFSET(n) (0x0010+(0x28*(n)) /* Channel n */ + #define KINETIS_PDB_CHC1_OFFSET 0x0000 /* Channel n Control Register 1 */ #define KINETIS_PDB_CHS_OFFSET 0x0004 /* Channel n Status Register */ #define KINETIS_PDB_CHDLY0_OFFSET 0x0008 /* Channel n Delay 0 Register */ @@ -57,6 +58,7 @@ #define KINETIS_PDB_CH1DLY1_OFFSET 0x0044 /* Channel 1 Delay 1 Register */ #define KINETIS_PDB_INT_OFFSET(n) (0x0150+((n)<<3) /* DAC Interval n offset */ + #define KINETIS_PDB_DACINTC_OFFSET 0x0000 /* DAC Interval Trigger n Control Register */ #define KINETIS_PDB_DACINT_OFFSET 0x0004 /* DAC Interval n Register */ @@ -73,7 +75,7 @@ # define KINETIS_PDB_PO2DLY_OFFSET 0x019c /* Pulse-Out 2 Delay Register */ #endif -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_PDB0_SC (KINETIS_PDB0_BASE+KINETIS_PDB_SC_OFFSET) #define KINETIS_PDB0_MOD (KINETIS_PDB0_BASE+KINETIS_PDB_MOD_OFFSET) @@ -113,7 +115,7 @@ # define KINETIS_PDB0_PO2DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO2DLY_OFFSET) #endif -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Status and Control Register */ @@ -147,6 +149,7 @@ # define PDB_SC_TRGSEL_TRGIN13 (13 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 3 */ # define PDB_SC_TRGSEL_TRGIN14 (14 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 4 */ # define PDB_SC_TRGSEL_TRGSW (15 << PDB_SC_TRGSEL_SHIFT) /* Software trigger */ + #define PDB_SC_PRESCALER_SHIFT (12) /* Bits 12-14: Prescaler Divider Select */ #define PDB_SC_PRESCALER_MASK (7 << PDB_SC_PRESCALER_SHIFT) # define PDB_SC_PRESCALER_DIVM (0 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / MULT */ @@ -157,6 +160,7 @@ # define PDB_SC_PRESCALER_DIV32M (5 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 32*MULT */ # define PDB_SC_PRESCALER_DIV64M (6 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 64*MULT */ # define PDB_SC_PRESCALER_DIV128M (7 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 128*MULT */ + #define PDB_SC_DMAEN (1 << 15) /* Bit 15: DMA Enable */ #define PDB_SC_SWTRIG (1 << 16) /* Bit 16: Software Trigger */ #define PDB_SC_PDBEIE (1 << 17) /* Bit 17: PDB Sequence Error Interrupt Enable */ @@ -166,7 +170,9 @@ # define PDB_SC_LDMOD_PDBCNT (1 << PDB_SC_LDMOD_SHIFT) /* Load when the PDB counter = MOD */ # define PDB_SC_LDMOD_TRIGGER (2 << PDB_SC_LDMOD_SHIFT) /* Load when trigger input event */ # define PDB_SC_LDMOD_EITHER (3 << PDB_SC_LDMOD_SHIFT) /* Load when either occurs */ + /* Bits 20-31: Reserved */ + /* Modulus Register */ /* Bits 16-31: Reserved */ @@ -194,6 +200,7 @@ #define PDB_CHC1_BB_MASK (0xff << PDB_CHC1_BB_SHIFT) # define PDB_CHC1_BB_CHAN(n) ((1 << (n)) << PDB_CHC1_BB_SHIFT) /* Bits 24-31: Reserved */ + /* Channel n Status Register */ #define PDB_CHS_ERR_SHIFT (0) /* Bits 0-7: PDB Channel Sequence Error Flags */ @@ -204,11 +211,14 @@ #define PDB_CHS_CF_MASK (0xff << PDB_CHS_CF_SHIFT) # define PDB_CHS_CF_CHAN(n) ((1 << (n)) << PDB_CHS_CF_SHIFT) /* Bits 24-31: Reserved */ + /* Channel n Delay 0 Register */ + /* Bits 16-31: Reserved */ #define PDB_CHDLY0_MASK (0xffff) /* Bits 0-15: PDB Channel Delay */ /* Channel n Delay 1 Register */ + /* Bits 16-31: Reserved */ #define PDB_CHDLY1_MASK (0xffff) /* Bits 0-15: PDB Channel Delay */ @@ -217,7 +227,9 @@ #define PDB_DACINTC_TOE (1 << 0) /* Bit 0: DAC Interval Trigger Enable */ #define PDB_DACINTC_EXT (1 << 1) /* Bit 1: DAC External Trigger Input Enable */ /* Bits 2-31: Reserved */ + /* DAC Interval n Register */ + /* Bits 16-31: Reserved */ #define PDB_DACINT_MASK (0xffff) /* Bits 0-15: DAC Interval */ @@ -233,16 +245,16 @@ #define PDB_PO0DLY_DLY2_SHIFT (0) /* Bits 0-15: PDB Pulse-Out Delay 2 */ #define PDB_PO0DLY_DLY2_MASK (0xffff << PDB_PO0DLY_DLY2_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_pinmux.h index 6059170517..ececbbb2ad 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_pinmux.h +++ b/arch/arm/src/kinetis/hardware/kinetis_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/* This file is just a wrapper around pin muxing header files for the Kinetis family selected - * by the logic in chip.h. +/* This file is just a wrapper around pin muxing header files for the Kinetis + * family selected by the logic in chip.h. */ #if defined(KINETIS_K20) @@ -49,20 +49,20 @@ # error "No pin multiplexing for this Kinetis part" #endif -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_pit.h b/arch/arm/src/kinetis/hardware/kinetis_pit.h index a6a97b0cf8..11b3cee5fe 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_pit.h +++ b/arch/arm/src/kinetis/hardware/kinetis_pit.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_pit.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,29 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #if defined(KINETIS_K66) # define KINETIS_PIT_HAS_CHAIN # define KINETIS_PIT_HAS_LIFETIME #endif -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */ #if defined(KINETIS_PIT_HAS_LIFETIME) @@ -62,7 +62,7 @@ #define KINETIS_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */ #define KINETIS_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_PIT_MCR (KINETIS_PIT_BASE+KINETIS_PIT_MCR_OFFSET) #if defined(KINETIS_PIT_HAS_LIFETIME) @@ -86,7 +86,7 @@ #define KINETIS_PIT_TCTRL3 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL3_OFFSET) #define KINETIS_PIT_TFLG3 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG3_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* PIT Module Control Register */ @@ -95,6 +95,7 @@ /* Bits 2-31: Reserved */ /* Timer Load Value Register (32-bit Timer Start Value Bits) */ + /* Current Timer Value Register (32-bit Current Timer Value) */ /* Timer Control Register */ @@ -111,16 +112,16 @@ #define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */ /* Bits 1-31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_pmc.h b/arch/arm/src/kinetis/hardware/kinetis_pmc.h index ce3109693f..c74fd36f83 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_pmc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_pmc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_pmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_PMC_LVDSC1_OFFSET 0x0000 /* Low Voltage Detect Status and Control 1 Register */ #define KINETIS_PMC_LVDSC2_OFFSET 0x0001 /* Low Voltage Detect Status and Control 2 Register */ @@ -45,7 +45,7 @@ # define KINETIS_PMC_SRAMCTL_OFFSET 0x000c /* SRAM VLLS2 Control register */ #endif -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_PMC_LVDSC1 (KINETIS_PMC_BASE + KINETIS_PMC_LVDSC1_OFFSET) #define KINETIS_PMC_LVDSC2 (KINETIS_PMC_BASE + KINETIS_PMC_LVDSC2_OFFSET) @@ -57,7 +57,7 @@ # define KINETIS_PMC_SRAMCTL (KINETIS_PMC_BASE + KINETIS_PMC_SRAMCTL_OFFSET) #endif -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Low Voltage Detect Status and Control 1 Register */ @@ -65,6 +65,7 @@ #define PMC_LVDSC1_LVDV_MASK (3 << PMC_LVDSC1_LVDV_SHIFT) # define PMC_LVDSC1_LVDV_LOW (0 << PMC_LVDSC1_LVDV_SHIFT) /* Low trip point selected (VLVD = VLVDL) */ # define PMC_LVDSC1_LVDV_HIGH (1 << PMC_LVDSC1_LVDV_SHIFT) /* High trip point selected (VLVD = VLVDH) */ + /* Bits 2-3: Reserved */ #define PMC_LVDSC1_LVDRE (1 << 4) /* Bit 4: Low-Voltage Detect Reset Enable */ #define PMC_LVDSC1_LVDIE (1 << 5) /* Bit 5: Low-Voltage Detect Interrupt Enable */ @@ -79,7 +80,8 @@ # define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */ # define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */ # define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */ - /* Bits 2-4: Reserved */ + + /* Bits 2-4: Reserved */ #define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */ #define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */ #define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */ @@ -123,16 +125,16 @@ # define PMC_SRAMCTL_VLLS2PD (1 << (n)) /* Bits 0-7: SRAM VLLS2 Powerdown */ #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_port.h b/arch/arm/src/kinetis/hardware/kinetis_port.h index 84af23cf6d..b193c9fff3 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_port.h +++ b/arch/arm/src/kinetis/hardware/kinetis_port.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_port.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* General Definitions **************************************************************/ + ****************************************************************************/ + +/* General Definitions ******************************************************/ #define KINETIS_PORTA (0) #define KINETIS_PORTB (1) @@ -41,9 +42,10 @@ #define KINETIS_PORTE (4) #define KINETIS_NPORTS (5) -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_PORT_PCR_OFFSET(n) ((n) << 2) /* Pin Control Register n, n=0..31 */ + #define KINETIS_PORT_PCR0_OFFSET 0x0000 /* Pin Control Register 0 */ #define KINETIS_PORT_PCR1_OFFSET 0x0004 /* Pin Control Register 1 */ #define KINETIS_PORT_PCR2_OFFSET 0x0008 /* Pin Control Register 2 */ @@ -83,7 +85,7 @@ #define KINETIS_PORT_DFCR_OFFSET 0x00c4 /* Digital Filter Clock Register */ #define KINETIS_PORT_DFWR_OFFSET 0x00c8 /* Digital Filter Width Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_PORT_PCR(p,n) (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR_OFFSET(n) #define KINETIS_PORT_PCR0(p) (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR0_OFFSET) @@ -325,7 +327,8 @@ #define KINETIS_PORTE_DFCR (KINETIS_PORTE_BASE+KINETIS_PORT_DFCR_OFFSET) #define KINETIS_PORTE_DFWR (KINETIS_PORTE_BASE+KINETIS_PORT_DFWR_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ + /* Pin Control Register n, n=0..31 */ #define PORT_PCR_PS (1 << 0) /* Bit 0: Pull Select */ @@ -347,6 +350,7 @@ # define PORT_PCR_MUX_ALT5 (5 << PORT_PCR_MUX_SHIFT) /* Alternative 5 (chip specific) */ # define PORT_PCR_MUX_ALT6 (6 << PORT_PCR_MUX_SHIFT) /* Alternative 6 (chip specific) */ # define PORT_PCR_MUX_ALT7 (7 << PORT_PCR_MUX_SHIFT) /* Alternative 7 (chip specific / JTAG / NMI) */ + /* Bits 11-14: Reserved */ #define PORT_PCR_LK (1 << 15) /* Bit 15: Lock Register */ #define PORT_PCR_IRQC_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ @@ -360,6 +364,7 @@ # define PORT_PCR_IRQC_FALLING (10 << PORT_PCR_IRQC_SHIFT) /* Interrupt on falling edge */ # define PORT_PCR_IRQC_BOTH (11 << PORT_PCR_IRQC_SHIFT) /* Interrupt on either edge */ # define PORT_PCR_IRQC_ONE (12 << PORT_PCR_IRQC_SHIFT) /* Interrupt when logic one */ + /* Bits 20-23: Reserved */ #define PORT_PCR_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */ /* Bits 25-31: Reserved */ @@ -399,16 +404,16 @@ #define PORT_DFWR_FILT_SHIFT (0) /* Bits 0-4: Filter Length */ #define PORT_DFWR_FILT_MASK (31 << PORT_DFWR_FILT_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_rngb.h b/arch/arm/src/kinetis/hardware/kinetis_rngb.h index f756a2a239..00003bf1be 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_rngb.h +++ b/arch/arm/src/kinetis/hardware/kinetis_rngb.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_rngb.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,11 @@ #if defined(KINETIS_NRNG) && KINETIS_NRNG > 0 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_RNG_VER_OFFSET 0x0000 /* RNGB Version ID Register */ #define KINETIS_RNG_CMD_OFFSET 0x0004 /* RNGB Command Register */ @@ -44,7 +44,7 @@ #define KINETIS_RNG_ESR_OFFSET 0x0010 /* RNGB Error Status Register */ #define KINETIS_RNG_OUT_OFFSET 0x0014 /* RNGB Output FIFO */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_RNG_VER (KINETIS_RNGB_BASE+KINETIS_RNG_VER_OFFSET) #define KINETIS_RNG_CMD (KINETIS_RNGB_BASE+KINETIS_RNG_CMD_OFFSET) @@ -53,7 +53,7 @@ #define KINETIS_RNG_ESR (KINETIS_RNGB_BASE+KINETIS_RNG_ESR_OFFSET) #define KINETIS_RNG_OUT (KINETIS_RNGB_BASE+KINETIS_RNG_OUT_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* RNGB Version ID Register */ @@ -77,6 +77,7 @@ #define RNG_CMD_CE (1 << 5) /* Bit 5: Clear error */ #define RNG_CMD_SR (1 << 6) /* Bit 6: Software reset */ /* Bits 7-31: Reserved */ + /* RNGB Control Register */ #define RNG_CR_FUFMOD_SHIFT (0) /* Bits 0-1: FIFO underflow response mode */ @@ -84,12 +85,15 @@ # define RNG_CR_FUFMOD_ZEROS (0 << RNG_CR_FUFMOD_SHIFT) /* Return zeros, set RNG_ESR[FUFE] */ # define RNG_CR_FUFMOD_ERROR (2 << RNG_CR_FUFMOD_SHIFT) /* Generate bus transfer error */ # define RNG_CR_FUFMOD_INT (3 << RNG_CR_FUFMOD_SHIFT) /* Generate interrupt, return zeros */ + /* Bits 2-3: Reserved */ #define RNG_CR_AR (1 << 4) /* Bit 4: Auto-reseed */ #define RNG_CR_MASKDONE (1 << 5) /* Bit 5: Mask done interrupt */ #define RNG_CR_MASKERR (1 << 6) /* Bit 6: Mask error interrupt */ /* Bits 7-31: Reserved */ + /* RNGB Status Register */ + /* Bit 0: Reserved */ #define RNG_SR_BUSY (1 << 1) /* Bit 1: Busy */ #define RNG_SR_SLP (1 << 2) /* Bit 2: Sleep */ @@ -109,6 +113,7 @@ # define RNG_SR_ST_PF_TRNG (4 << RNG_SR_ST_PF_SHIFT) /* TRNG self test pass/fail */ # define RNG_SR_ST_PF_PRNG (2 << RNG_SR_ST_PF_SHIFT) /* PRNG self test pass/fail */ # define RNG_SR_ST_PF_RESEED (1 << RNG_SR_ST_PF_SHIFT) /* RESEED self test pass/fail */ + #define RNG_SR_STATPF_SHIFT (24) /* Bits 24-31: Statistics test pass fail */ #define RNG_SR_STATPF_MASK (0xff << RNG_SR_STATPF_SHIFT) # define RNG_SR_STATPF_LONG (0x80 << RNG_SR_STATPF_SHIFT) /* Long run test (>34) */ @@ -128,19 +133,20 @@ #define RNG_ESR_SATE (1 << 3) /* Bit 3: Statistical test error */ #define RNG_ESR_FUFE (1 << 4) /* Bit 4: FIFO underflow error */ /* Bits 5-31: Reserved */ + /* RNGB Output FIFO (32-bit random output) */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_NRNG && KINETIS_NRNG > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_rtc.h b/arch/arm/src/kinetis/hardware/kinetis_rtc.h index ef03ed3850..b728b20978 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_rtc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_rtc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,16 +31,17 @@ #if defined(KINETIS_NRTC) && KINETIS_NRTC > 0 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ -/* NXP/Freescale has families and technology generations (sometimes seen as processor - * speed). These are organized into feature families, and faster speeds sometimes - * have extended features. Families are K02 K10 K20 K22 K24 K30 K40 K50 K60 K64 K65 - * K66 K70 K80 +/* NXP/Freescale has families and technology generations + * (sometimes seen as processor speed). + * These are organized into feature families, and faster speeds sometimes + * have extended features. + * Families are K02 K10 K20 K22 K24 K30 K40 K50 K60 K64 K65 K66 K70 K80 * * So far only two variations/generations on the RTC have been discovered. * GEN1 RTC_TSR TPR TAR TCR CR SR LR IER WAR RAR @@ -68,9 +69,10 @@ #define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */ #ifdef KINETIS_K60 - /* Haven't found a processor or nuttx file where KINETIS_RTC_CCR is in it - * from K60P100M100SF2V2RM this would be called KINETIS_RTC_IER_OFFSET. - */ + +/* Haven't found a processor or nuttx file where KINETIS_RTC_CCR is in it + * from K60P100M100SF2V2RM this would be called KINETIS_RTC_IER_OFFSET. + */ # define KINETIS_RTC_CCR_OFFSET 0x001c /* RTC Chip Configuration Register (K60) */ #endif @@ -85,7 +87,7 @@ #define KINETIS_RTC_WAR_OFFSET 0x0800 /* RTC Write Access Register */ #define KINETIS_RTC_RAR_OFFSET 0x0804 /* RTC Read Access Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_RTC_TSR (KINETIS_RTC_BASE+KINETIS_RTC_TSR_OFFSET) #define KINETIS_RTC_TPR (KINETIS_RTC_BASE+KINETIS_RTC_TPR_OFFSET) @@ -112,7 +114,7 @@ #define KINETIS_RTC_WAR (KINETIS_RTC_BASE+KINETIS_RTC_WAR_OFFSET) #define KINETIS_RTC_RAR (KINETIS_RTC_BASE+KINETIS_RTC_RAR_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* RTC Time Seconds Register (32-bits of time in seconds) */ @@ -121,6 +123,7 @@ #define RTC_TPR_SHIFT (0) /* Bits 0-15: Time Prescaler Register */ #define RTC_TPR_MASK (0xffff << RTC_TPR_SHIFT) /* Bits 16-31: Reserved */ + /* RTC Time Alarm Register (32-bits of time alarm) */ /* RTC Time Compensation Register (32-bits) */ @@ -148,6 +151,7 @@ #define RTC_CR_SC4P (1 << 12) /* Bit 12: Oscillator 4pF load configure */ #define RTC_CR_SC2P (1 << 13) /* Bit 13: Oscillator 2pF load configure */ /* Bits 14-31: Reserved */ + /* RTC Status Register (32-bits) */ #define RTC_SR_TIF (1 << 0) /* Bit 0: Time Invalid Flag */ @@ -160,7 +164,9 @@ /* Bit 3: Reserved RTC_GEN1 */ #define RTC_SR_TCE (1 << 4) /* Bit 4: Time Counter Enable */ /* Bits 5-31: Reserved */ + /* RTC Lock Register (32-bits) */ + /* Bits 0-2: Reserved */ #define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */ #define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */ @@ -174,6 +180,7 @@ # define RTC_LR_MCHL (1 << 11) /* Bit 10: Monotoic Counter High Lock */ #endif /* Bits 12-31: Reserved */ + /* RTC Interrupt Enable Register (32-bits, K40) */ # define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */ @@ -189,7 +196,9 @@ # define RTC_IER_WPON (1 << 7) /* Bit 7: Wakeup Pin On */ #ifdef KINETIS_K60 + /* RTC Chip Configuration Register (32-bits,K60) */ + /* Haven't found this in K60P100M100SF2V2RM */ # define RTC_CCR_CONFIG_SHIFT (0) /* Bits 0-7: Chip Configuration */ @@ -209,11 +218,14 @@ #define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */ #ifdef KINETIS_K60 -/* This looks like old name, from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERW */ +/* This looks like old name, + * from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERW + */ # define RTC_WAR_CCRW (1 << 7) /* Bit 7: Chip Config Register Write */ #endif /* Bits 8-31: Reserved */ + /* RTC Read Access Register */ #define RTC_RAR_TSRR (1 << 0) /* Bit 0: Time Seconds Register Read */ @@ -226,8 +238,8 @@ #define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */ #ifdef KINETIS_K60 -/* This is possibly an old name, from K60P100M100SF2V2RM bit 7 would be called - * RTC_RAR_IERR. +/* This is possibly an old name, + * from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERR. */ # define RTC_RAR_CCRR (1 << 7) /* Bit 7: Chip Config Register Read */ @@ -246,17 +258,17 @@ # define CONFIG_RTC_MAGICH 0xef32a141 #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* KINETIS_NRTC && KINETIS_NRTC > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_sdhc.h b/arch/arm/src/kinetis/hardware/kinetis_sdhc.h index 76d03d1667..b8c2621167 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_sdhc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_sdhc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_sdhc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_SDHC_DSADDR_OFFSET 0x0000 /* DMA System Address Register */ #define KINETIS_SDHC_BLKATTR_OFFSET 0x0004 /* Block Attributes Register */ @@ -60,7 +60,7 @@ #define KINETIS_SDHC_MMCBOOT_OFFSET 0x00c4 /* MMC Boot Register */ #define KINETIS_SDHC_HOSTVER_OFFSET 0x00fc /* Host Controller Version */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_SDHC_DSADDR (KINETIS_SDHC_BASE+KINETIS_SDHC_DSADDR_OFFSET) #define KINETIS_SDHC_BLKATTR (KINETIS_SDHC_BASE+KINETIS_SDHC_BLKATTR_OFFSET) @@ -87,13 +87,14 @@ #define KINETIS_SDHC_MMCBOOT (KINETIS_SDHC_BASE+KINETIS_SDHC_MMCBOOT_OFFSET) #define KINETIS_SDHC_HOSTVER (KINETIS_SDHC_BASE+KINETIS_SDHC_HOSTVER_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* DMA System Address Register */ #define SDHC_DSADDR_SHIFT (1) /* Bits 1-31: DMA System Address */ #define SDHC_DSADDR_MASK (0xfffffffe) /* Bits 0-1: Reserved */ + /* Block Attributes Register */ #define SDHC_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */ @@ -119,6 +120,7 @@ # define SDHC_XFERTYP_RSPTYP_LEN136 (1 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */ # define SDHC_XFERTYP_RSPTYP_LEN48 (2 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */ # define SDHC_XFERTYP_RSPTYP_LEN48BSY (3 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */ + /* Bit 18: Reserved */ #define SDHC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */ #define SDHC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */ @@ -129,9 +131,11 @@ # define SDHC_XFERTYP_CMDTYP_SUSPEND (1 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */ # define SDHC_XFERTYP_CMDTYP_RESUME (2 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */ # define SDHC_XFERTYP_CMDTYP_ABORT (3 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */ + #define SDHC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */ #define SDHC_XFERTYP_CMDINX_MASK (63 << SDHC_XFERTYP_CMDINX_SHIFT) /* Bits 30-31: Reserved */ + /* Command Response 0-3 (32-bit response data) */ /* Buffer Data Port Register (32-bit data content) */ @@ -173,12 +177,14 @@ # define SDHC_PROCTL_DTW_1BIT (0 << SDHC_PROCTL_DTW_SHIFT) /* 1-bit mode */ # define SDHC_PROCTL_DTW_4BIT (1 << SDHC_PROCTL_DTW_SHIFT) /* 4-bit mode */ # define SDHC_PROCTL_DTW_8BIT (2 << SDHC_PROCTL_DTW_SHIFT) /* 8-bit mode */ + #define SDHC_PROCTL_D3CD (1 << 3) /* Bit nn: DAT3 as Card Detection Pin */ #define SDHC_PROCTL_EMODE_SHIFT (4) /* Bits 4-5: Endian mode */ #define SDHC_PROCTL_EMODE_MASK (3 << SDHC_PROCTL_EMODE_SHIFT) # define SDHC_PROCTL_EMODE_BE (0 << SDHC_PROCTL_EMODE_SHIFT) /* Big endian mode */ # define SDHC_PROCTL_EMODE_HWBE (1 << SDHC_PROCTL_EMODE_SHIFT) /* Half word big endian mode */ # define SDHC_PROCTL_EMODE_LE (2 << SDHC_PROCTL_EMODE_SHIFT) /* Little endian mode */ + #define SDHC_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */ #define SDHC_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */ #define SDHC_PROCTL_DMAS_SHIFT (8) /* Bits 8-9: DMA Select */ @@ -186,6 +192,7 @@ # define SDHC_PROCTL_DMAS_NODMA (0 << SDHC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */ # define SDHC_PROCTL_DMAS_ADMA1 (1 << SDHC_PROCTL_DMAS_SHIFT) /* ADMA1 is selected */ # define SDHC_PROCTL_DMAS_ADMA2 (2 << SDHC_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */ + /* Bits 10-15: Reserved */ #define SDHC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */ #define SDHC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */ @@ -196,6 +203,7 @@ #define SDHC_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */ #define SDHC_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */ /* Bits 27-31: Reserved */ + /* System Control Register */ #define SDHC_SYSCTL_IPGEN (1 << 0) /* Bit 0: IPG Clock Enable */ @@ -205,6 +213,7 @@ #define SDHC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */ #define SDHC_SYSCTL_DVS_MASK (15 << SDHC_SYSCTL_DVS_SHIFT) # define SDHC_SYSCTL_DVS_DIV(n) (((n)-1) << SDHC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */ + #define SDHC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */ #define SDHC_SYSCTL_SDCLKFS_MASK (0xff << SDHC_SYSCTL_SDCLKFS_SHIFT) # define SDHC_SYSCTL_SDCLKFS_BYPASS (0x00 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */ @@ -216,16 +225,20 @@ # define SDHC_SYSCTL_SDCLKFS_DIV64 (0x20 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */ # define SDHC_SYSCTL_SDCLKFS_DIV128 (0x40 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */ # define SDHC_SYSCTL_SDCLKFS_DIV256 (0x80 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */ + #define SDHC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */ #define SDHC_SYSCTL_DTOCV_MASK (15 << SDHC_SYSCTL_DTOCV_SHIFT) # define SDHC_SYSCTL_DTOCV_MUL(n) (((n)-213) << SDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */ + /* Bits 20-23: Reserved */ #define SDHC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */ #define SDHC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */ #define SDHC_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */ #define SDHC_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */ /* Bits 28-31: Reserved */ -/* Interrupt Status Register, Interrupt Status Enable Register, and Interrupt Signal Enable Register + +/* Interrupt Status Register, Interrupt Status Enable Register, + * and Interrupt Signal Enable Register * Common interrupt bit definitions */ @@ -263,7 +276,9 @@ /* Bits 5-6: Reserved */ #define SDHC_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */ /* Bits 8-31: Reserved */ + /* Host Controller Capabilities */ + /* Bits 0-15: Reserved */ #define SDHC_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */ #define SDHC_HTCAPBLT_MBL_MASK (7 << SDHC_HTCAPBLT_MBL_SHIFT) @@ -280,6 +295,7 @@ #define SDHC_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */ #define SDHC_HTCAPBLT_VS18 (1 << 26) /* Bit 26: Voltage Support 1.8 */ /* Bits 27-31: Reserved */ + /* Watermark Level Register */ #define SDHC_WML_RD_SHIFT (0) /* Bits 0-7: Read Watermark Level */ @@ -288,6 +304,7 @@ #define SDHC_WML_WR_SHIFT (16) /* Bits 16-23: Write Watermark Level */ #define SDHC_WML_WR_MASK (0xff << SDHC_WML_WRWML_SHIFT) /* Bits 24-31: Reserved */ + /* Force Event Register */ #define SDHC_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */ @@ -320,9 +337,11 @@ # define SDHC_ADMAES_FDS (1 << SDHC_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */ # define SDHC_ADMAES_CADR (2 << SDHC_ADMAES_ADMAES_SHIFT) /* Change address */ # define SDHC_ADMAES_TFR (3 << SDHC_ADMAES_ADMAES_SHIFT) /* Transfer data */ + #define SDHC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */ #define SDHC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */ /* Bits 4-31: Reserved */ + /* ADMA System Address Register */ #define SDHC_ADSADDR_SHIFT (1) /* Bits 1-31: ADMA System Address */ @@ -337,11 +356,13 @@ #define SDHC_VENDOR_INTSTVAL_SHIFT (16) /* Bits 16-23: Internal State Value */ #define SDHC_VENDOR_INTSTVAL_MASK (0xff << SDHC_VENDOR_INTSTVAL_SHIFT) /* Bits 24-31: Reserved */ + /* MMC Boot Register */ #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0) /* Bits 0-3: Boot ACK time out counter value */ #define SDHC_MMCBOOT_DTOCVACK_MASK (15 << SDHC_MMCBOOT_DTOCVACK_SHIFT) # define SDHC_MMCBOOT_DTOCVACK_MUL(n) ((n-8) << SDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^n, n=8..22 */ + #define SDHC_MMCBOOT_BOOTACK (1 << 4) /* Bit 4: Boot ack mode select */ #define SDHC_MMCBOOT_BOOTMODE (1 << 5) /* Bit 5: Boot mode select */ #define SDHC_MMCBOOT_BOOTEN (1 << 6) /* Bit 6: Boot mode enable */ @@ -358,16 +379,16 @@ #define SDHC_HOSTVER_VVN_MASK (0xff << SDHC_HOSTVER_VVN_SHIFT) /* Bits 16-31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_slcd.h b/arch/arm/src/kinetis/hardware/kinetis_slcd.h index e7fb8d48db..d846ec221a 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_slcd.h +++ b/arch/arm/src/kinetis/hardware/kinetis_slcd.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_slcd.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_LCD_GCR_OFFSET 0x0000 /* LCD general control register */ #define KINETIS_LCD_AR_OFFSET 0x0004 /* LCD auxiliary register */ @@ -60,7 +60,7 @@ #define KINETIS_LCD_WF59TO56_OFFSET 0x0058 /* LCD waveform register */ #define KINETIS_LCD_WF63TO60_OFFSET 0x005C /* LCD waveform register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_LCD_GCR (KINETIS_SLCD_BASE+KINETIS_LCD_GCR_OFFSET) #define KINETIS_LCD_AR (KINETIS_SLCD_BASE+KINETIS_LCD_AR_OFFSET) @@ -87,13 +87,14 @@ #define KINETIS_LCD_WF59TO56 (KINETIS_SLCD_BASE+KINETIS_LCD_WF59TO56_OFFSET) #define KINETIS_LCD_WF63TO60 (KINETIS_SLCD_BASE+KINETIS_LCD_WF63TO60_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* LCD general control register */ #define LCD_GCR_DUTYSHIFT (0) /* Bits 0-2: LCD duty select */ #define LCD_GCR_DUTY_MASK (7 << LCD_GCR_DUTYSHIFT) # define LCD_GCR_DUTY_BP(n) (((n)-1) << LCD_GCR_DUTYSHIFT) /* Use n BP (1/n duty cycle) */ + #define LCD_GCR_LCLK_SHIFT (3) /* Bits 3-5: LCD clock prescaler */ #define LCD_GCR_LCLK_MASK (7 << LCD_GCR_LCLK_SHIFT) #define LCD_GCR_SOURCE (1 << 6) /* Bit 6: LCD clock source select */ @@ -107,6 +108,7 @@ # define LCD_GCR_ALTDIV_DIV (1 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 8 */ # define LCD_GCR_ALTDIV_DIV (2 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 64 */ # define LCD_GCR_ALTDIV_DIV (3 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 512 */ + #define LCD_GCR_FDCIEN (1 << 14) /* Bit 14: LCD fault detection complete interrupt enable */ #define LCD_GCR_LCDIEN (1 << 15) /* Bit 15: LCD frame frequency interrupt enable */ #define LCD_GCR_VSUPPLY_SHIFT (16) /* Bits 16-17: Voltage supply control */ @@ -115,6 +117,7 @@ #define LCD_GCR_VSUPPLY_INTVLL3 (1 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL3 internally from VDD */ #define LCD_GCR_VSUPPLY_EXTVLL3 (3 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL3 externally from VDD */ #define LCD_GCR_VSUPPLY_INTVLL1 (3 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL1 internally from VIREG */ + /* Bits 18-19: Reserved */ #define LCD_GCR_LADJ_SHIFT (20) /* Bits 20-21: Load adjust */ #define LCD_GCR_LADJ_MASK (3 << LCD_GCR_LADJ_SHIFT) @@ -126,6 +129,7 @@ # define LCD_GCR_LADJ_MIDFAST (1 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=6000pF */ # define LCD_GCR_LADJ_MIDSLOW (2 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=4000pF */ # define LCD_GCR_LADJ_SLOW (3 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=2000pF */ + #define LCD_GCR_HREFSEL (1 << 22) /* Bit 22: High reference select */ #define LCD_GCR_CPSEL (1 << 23) /* Bit 23: Charge pump or resistor bias select */ #define LCD_GCR_RVTRIM_SHIFT (24) /* Bits 24-27: Regulated voltage trim */ @@ -139,12 +143,13 @@ #define LCD_AR_BRATE_MASK (7 << LCD_AR_BRATE_SHIFT) #define LCD_AR_BMODE (1 << 3) /* Bit 3: Blink mode */ /* Bit 4: Reserved */ -#define LCD_AR_BLANK (1 << 5) /* Bit 5: Blank display mode +#define LCD_AR_BLANK (1 << 5) /* Bit 5: Blank display mode */ #define LCD_AR_ALT (1 << 6) /* Bit 6: Alternate display mode */ #define LCD_AR_BLINK (1 << 7) /* Bit 7: Blink command */ /* Bits 8-14: Reserved */ #define LCD_AR_LCDIF (1 << 15) /* Bit 15: LCD frame frequency interrupt flag */ /* Bits 16-31: Reserved */ + /* LCD fault detect control register */ #define LCD_FDCR_FDPINID_SHIFT (0) /* Bits 0-5: Fault detect pin ID */ @@ -164,7 +169,9 @@ # define LCD_FDCR_FDPRS_DIV32 (5 << LCD_FDCR_FDPRS_SHIFT) /* 1/32 bus clock */ # define LCD_FDCR_FDPRS_DIV64 (6 << LCD_FDCR_FDPRS_SHIFT) /* 1/64 bus clock */ # define LCD_FDCR_FDPRS_DIV128 (7 << LCD_FDCR_FDPRS_SHIFT) /* 1/128 bus clock */ + /* Bits 15-31: Reserved */ + /* LCD fault detect status register */ #define LCD_FDSR_FDCNT_SHIFT (0) /* Bits 0-7: Fault detect counter */ @@ -172,12 +179,13 @@ /* Bits 8-14: Reserved */ #define LCD_FDSR_FDCF (1 << 15) /* Bit 15: Fault detection complete flag */ /* Bits 16-31: Reserved */ -/* LCD pin enable register low/high (64 pin bits in two 32-bit registers) */ +/* LCD pin enable register low/high (64 pin bits in two 32-bit registers) */ /* LCD backplane enable register (64 pin bits in two 32-bit registers) */ #define LCD_BPENL(n) (1 << (n)) /* Bit n: Enable backplane operation pin n, n=0-31 */ + #define LCD_BPENH(n) (1 << ((n)-32)) /* Bit n-32: Enable backplane operation pin n, n=32-63 */ /* LCD waveform registers */ @@ -185,12 +193,15 @@ #define LCD_WF3TO0_WF0_SHIFT (0) /* Bits 0-7: Waveform control field 0 segment bits */ #define LCD_WF3TO0_WF0_MASK (0xff << LCD_WF3TO0_WF0_SHIFT) # define LCD_WF3TO0_WF0_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF0_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF3TO0_WF1_SHIFT (8) /* Bits 8-15: Waveform control field 1 segment bits */ #define LCD_WF3TO0_WF1_MASK (0xff << LCD_WF3TO0_WF1_SHIFT) # define LCD_WF3TO0_WF1_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF1_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF3TO0_WF2_SHIFT (16) /* Bits 16-23: Waveform control field 2 segment bits */ #define LCD_WF3TO0_WF2_MASK (0xff << LCD_WF3TO0_WF2_SHIFT) # define LCD_WF3TO0_WF2_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF2_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF3TO0_WF3_SHIFT (24) /* Bits 24-31: Waveform control field 3 segment bits */ #define LCD_WF3TO0_WF3_MASK (0xff << LCD_WF3TO0_WF3_SHIFT) # define LCD_WF3TO0_WF3_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF3_SHIFT) /* Segment n, n=0..7 */ @@ -198,12 +209,15 @@ #define LCD_WF7TO4_WF4_SHIFT (0) /* Bits 0-7: Waveform control field 4 segment bits */ #define LCD_WF7TO4_WF4_MASK (0xff << LCD_WF7TO4_WF4_SHIFT) # define LCD_WF7TO4_WF4_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF4_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF7TO4_WF5_SHIFT (8) /* Bits 8-15: Waveform control field 5 segment bits */ #define LCD_WF7TO4_WF5_MASK (0xff << LCD_WF7TO4_WF5_SHIFT) # define LCD_WF7TO4_WF5_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF5_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF7TO4_WF6_SHIFT (16) /* Bits 16-23: Waveform control field 6 segment bits */ #define LCD_WF7TO4_WF6_MASK (0xff << LCD_WF7TO4_WF6_SHIFT) # define LCD_WF7TO4_WF6_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF6_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF7TO4_WF7_SHIFT (24) /* Bits 24-31: Waveform control field 7 segment bits */ #define LCD_WF7TO4_WF7_MASK (0xff << LCD_WF7TO4_WF7_SHIFT) # define LCD_WF7TO4_WF7_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF7_SHIFT) /* Segment n, n=0..7 */ @@ -211,12 +225,15 @@ #define LCD_WF11TO8_WF8_SHIFT (0) /* Bits 0-7: Waveform control field 8 segment bits */ #define LCD_WF11TO8_WF8_MASK (0xff << LCD_WF11TO8_WF8_SHIFT) # define LCD_WF11TO8_WF8_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF8_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF11TO8_WF9_SHIFT (8) /* Bits 8-15: Waveform control field 9 segment bits */ #define LCD_WF11TO8_WF9_MASK (0xff << LCD_WF11TO8_WF9_SHIFT) # define LCD_WF11TO8_WF9_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF9_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF11TO8_WF10_SHIFT (16) /* Bits 16-23: Waveform control field 10 segment bits */ #define LCD_WF11TO8_WF10_MASK (0xff << LCD_WF11TO8_WF10_SHIFT) # define LCD_WF11TO8_WF10_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF10_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF11TO8_WF11_SHIFT (24) /* Bits 24-31: Waveform control field 11 segment bits */ #define LCD_WF11TO8_WF11_MASK (0xff << LCD_WF11TO8_WF11_SHIFT) # define LCD_WF11TO8_WF11_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF11_SHIFT) /* Segment n, n=0..7 */ @@ -224,12 +241,15 @@ #define LCD_WF15TO12_WF12_SHIFT (0) /* Bits 0-7: Waveform control field 12 segment bits */ #define LCD_WF15TO12_WF12_MASK (0xff << LCD_WF15TO12_WF12_SHIFT) # define LCD_WF15TO12_WF12_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF12_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF15TO12_WF13_SHIFT (8) /* Bits 8-15: Waveform control field 13 segment bits */ #define LCD_WF15TO12_WF13_MASK (0xff << LCD_WF15TO12_WF13_SHIFT) # define LCD_WF15TO12_WF13_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF13_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF15TO12_WF14_SHIFT (16) /* Bits 16-23: Waveform control field 14 segment bits */ #define LCD_WF15TO12_WF14_MASK (0xff << LCD_WF15TO12_WF14_SHIFT) # define LCD_WF15TO12_WF14_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF14_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF15TO12_WF15_SHIFT (24) /* Bits 24-31: Waveform control field 15 segment bits */ #define LCD_WF15TO12_WF15_MASK (0xff << LCD_WF15TO12_WF15_SHIFT) # define LCD_WF15TO12_WF15_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF15_SHIFT) /* Segment n, n=0..7 */ @@ -237,12 +257,15 @@ #define LCD_WF19TO16_WF16_SHIFT (0) /* Bits 0-7: Waveform control field 16 segment bits */ #define LCD_WF19TO16_WF16_MASK (0xff << LCD_WF19TO16_WF16_SHIFT) # define LCD_WF19TO16_WF16_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF16_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF19TO16_WF17_SHIFT (8) /* Bits 8-15: Waveform control field 17 segment bits */ #define LCD_WF19TO16_WF17_MASK (0xff << LCD_WF19TO16_WF17_SHIFT) # define LCD_WF19TO16_WF17_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF17_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF19TO16_WF18_SHIFT (16) /* Bits 16-23: Waveform control field 18 segment bits */ #define LCD_WF19TO16_WF18_MASK (0xff << LCD_WF19TO16_WF18_SHIFT) # define LCD_WF19TO16_WF18_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF18_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF19TO16_WF19_SHIFT (24) /* Bits 24-31: Waveform control field 19 segment bits */ #define LCD_WF19TO16_WF19_MASK (0xff << LCD_WF19TO16_WF19_SHIFT) # define LCD_WF19TO16_WF19_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF19_SHIFT) /* Segment n, n=0..7 */ @@ -250,12 +273,15 @@ #define LCD_WF23TO20_WF20_SHIFT (0) /* Bits 0-7: Waveform control field 20 segment bits */ #define LCD_WF23TO20_WF20_MASK (0xff << LCD_WF23TO20_WF20_SHIFT) # define LCD_WF23TO20_WF20_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF20_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF23TO20_WF21_SHIFT (8) /* Bits 8-15: Waveform control field 21 segment bits */ #define LCD_WF23TO20_WF21_MASK (0xff << LCD_WF23TO20_WF21_SHIFT) # define LCD_WF23TO20_WF21_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF21_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF23TO20_WF22_SHIFT (16) /* Bits 16-23: Waveform control field 22 segment bits */ #define LCD_WF23TO20_WF22_MASK (0xff << LCD_WF23TO20_WF22_SHIFT) # define LCD_WF23TO20_WF22_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF22_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF23TO20_WF23_SHIFT (24) /* Bits 24-31: Waveform control field 23 segment bits */ #define LCD_WF23TO20_WF23_MASK (0xff << LCD_WF23TO20_WF23_SHIFT) # define LCD_WF23TO20_WF23_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF23_SHIFT) /* Segment n, n=0..7 */ @@ -263,12 +289,15 @@ #define LCD_WF27TO24_WF24_SHIFT (0) /* Bits 0-7: Waveform control field 24 segment bits */ #define LCD_WF27TO24_WF24_MASK (0xff << LCD_WF27TO24_WF24_SHIFT) # define LCD_WF27TO24_WF24_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF24_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF27TO24_WF25_SHIFT (8) /* Bits 8-15: Waveform control field 25 segment bits */ #define LCD_WF27TO24_WF25_MASK (0xff << LCD_WF27TO24_WF25_SHIFT) # define LCD_WF27TO24_WF25_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF25_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF27TO24_WF26_SHIFT (16) /* Bits 16-23: Waveform control field 26 segment bits */ #define LCD_WF27TO24_WF26_MASK (0xff << LCD_WF27TO24_WF26_SHIFT) # define LCD_WF27TO24_WF26_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF26_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF27TO24_WF27_SHIFT (24) /* Bits 24-31: Waveform control field 27 segment bits */ #define LCD_WF27TO24_WF27_MASK (0xff << LCD_WF27TO24_WF27_SHIFT) # define LCD_WF27TO24_WF27_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF27_SHIFT) /* Segment n, n=0..7 */ @@ -276,12 +305,15 @@ #define LCD_WF31TO28_WF28_SHIFT (0) /* Bits 0-7: Waveform control field 28 segment bits */ #define LCD_WF31TO28_WF28_MASK (0xff << LCD_WF31TO28_WF28_SHIFT) # define LCD_WF31TO28_WF28_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF28_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF31TO28_WF29_SHIFT (8) /* Bits 8-15: Waveform control field 29 segment bits */ #define LCD_WF31TO28_WF29_MASK (0xff << LCD_WF31TO28_WF29_SHIFT) # define LCD_WF31TO28_WF29_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF29_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF31TO28_WF30_SHIFT (16) /* Bits 16-23: Waveform control field 30 segment bits */ #define LCD_WF31TO28_WF30_MASK (0xff << LCD_WF31TO28_WF30_SHIFT) # define LCD_WF31TO28_WF30_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF30_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF31TO28_WF31_SHIFT (24) /* Bits 24-31: Waveform control field 31 segment bits */ #define LCD_WF31TO28_WF31_MASK (0xff << LCD_WF31TO28_WF31_SHIFT) # define LCD_WF31TO28_WF31_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF31_SHIFT) /* Segment n, n=0..7 */ @@ -289,12 +321,15 @@ #define LCD_WF35TO32_WF32_SHIFT (0) /* Bits 0-7: Waveform control field 32 segment bits */ #define LCD_WF35TO32_WF32_MASK (0xff << LCD_WF35TO32_WF32_SHIFT) # define LCD_WF35TO32_WF32_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF32_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF35TO32_WF33_SHIFT (8) /* Bits 8-15: Waveform control field 33 segment bits */ #define LCD_WF35TO32_WF33_MASK (0xff << LCD_WF35TO32_WF33_SHIFT) # define LCD_WF35TO32_WF33_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF33_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF35TO32_WF34_SHIFT (16) /* Bits 16-23: Waveform control field 34 segment bits */ #define LCD_WF35TO32_WF34_MASK (0xff << LCD_WF35TO32_WF34_SHIFT) # define LCD_WF35TO32_WF34_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF34_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF35TO32_WF35_SHIFT (24) /* Bits 24-31: Waveform control field 35 segment bits */ #define LCD_WF35TO32_WF35_MASK (0xff << LCD_WF35TO32_WF35_SHIFT) # define LCD_WF35TO32_WF35_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF35_SHIFT) /* Segment n, n=0..7 */ @@ -302,12 +337,15 @@ #define LCD_WF39TO36_WF36_SHIFT (0) /* Bits 0-7: Waveform control field 36 segment bits */ #define LCD_WF39TO36_WF36_MASK (0xff << LCD_WF39TO36_WF36_SHIFT) # define LCD_WF39TO36_WF36_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF36_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF39TO36_WF37_SHIFT (8) /* Bits 8-15: Waveform control field 37 segment bits */ #define LCD_WF39TO36_WF37_MASK (0xff << LCD_WF39TO36_WF37_SHIFT) # define LCD_WF39TO36_WF37_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF37_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF39TO36_WF38_SHIFT (16) /* Bits 16-23: Waveform control field 38 segment bits */ #define LCD_WF39TO36_WF38_MASK (0xff << LCD_WF39TO36_WF38_SHIFT) # define LCD_WF39TO36_WF38_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF38_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF39TO36_WF39_SHIFT (24) /* Bits 24-31: Waveform control field 39 segment bits */ #define LCD_WF39TO36_WF39_MASK (0xff << LCD_WF39TO36_WF39_SHIFT) # define LCD_WF39TO36_WF39_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF39_SHIFT) /* Segment n, n=0..7 */ @@ -315,12 +353,15 @@ #define LCD_WF43TO40_WF40_SHIFT (0) /* Bits 0-7: Waveform control field 40 segment bits */ #define LCD_WF43TO40_WF40_MASK (0xff << LCD_WF43TO40_WF40_SHIFT) # define LCD_WF43TO40_WF40_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF40_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF43TO40_WF41_SHIFT (8) /* Bits 8-15: Waveform control field 41 segment bits */ #define LCD_WF43TO40_WF41_MASK (0xff << LCD_WF43TO40_WF41_SHIFT) # define LCD_WF43TO40_WF41_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF41_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF43TO40_WF42_SHIFT (16) /* Bits 16-23: Waveform control field 42 segment bits */ #define LCD_WF43TO40_WF42_MASK (0xff << LCD_WF43TO40_WF42_SHIFT) # define LCD_WF43TO40_WF42_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF42_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF43TO40_WF43_SHIFT (24) /* Bits 24-31: Waveform control field 43 segment bits */ #define LCD_WF43TO40_WF43_MASK (0xff << LCD_WF43TO40_WF43_SHIFT) # define LCD_WF43TO40_WF43_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF43_SHIFT) /* Segment n, n=0..7 */ @@ -328,12 +369,15 @@ #define LCD_WF47TO44_WF44_SHIFT (0) /* Bits 0-7: Waveform control field 44 segment bits */ #define LCD_WF47TO44_WF44_MASK (0xff << LCD_WF47TO44_WF44_SHIFT) # define LCD_WF47TO44_WF44_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF44_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF47TO44_WF45_SHIFT (8) /* Bits 8-15: Waveform control field 45 segment bits */ #define LCD_WF47TO44_WF45_MASK (0xff << LCD_WF47TO44_WF45_SHIFT) # define LCD_WF47TO44_WF45_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF45_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF47TO44_WF46_SHIFT (16) /* Bits 16-23: Waveform control field 46 segment bits */ #define LCD_WF47TO44_WF46_MASK (0xff << LCD_WF47TO44_WF46_SHIFT) # define LCD_WF47TO44_WF46_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF46_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF47TO44_WF47_SHIFT (24) /* Bits 24-31: Waveform control field 47 segment bits */ #define LCD_WF47TO44_WF47_MASK (0xff << LCD_WF47TO44_WF47_SHIFT) # define LCD_WF47TO44_WF47_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF47_SHIFT) /* Segment n, n=0..7 */ @@ -341,12 +385,15 @@ #define LCD_WF51TO48_WF48_SHIFT (0) /* Bits 0-7: Waveform control field 48 segment bits */ #define LCD_WF51TO48_WF48_MASK (0xff << LCD_WF51TO48_WF48_SHIFT) # define LCD_WF51TO48_WF48_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF48_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF51TO48_WF49_SHIFT (8) /* Bits 8-15: Waveform control field 49 segment bits */ #define LCD_WF51TO48_WF49_MASK (0xff << LCD_WF51TO48_WF49_SHIFT) # define LCD_WF51TO48_WF49_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF49_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF51TO48_WF50_SHIFT (16) /* Bits 16-23: Waveform control field 50 segment bits */ #define LCD_WF51TO48_WF50_MASK (0xff << LCD_WF51TO48_WF50_SHIFT) # define LCD_WF51TO48_WF50_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF50_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF51TO48_WF51_SHIFT (24) /* Bits 24-31: Waveform control field 51 segment bits */ #define LCD_WF51TO48_WF51_MASK (0xff << LCD_WF51TO48_WF51_SHIFT) # define LCD_WF51TO48_WF51_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF51_SHIFT) /* Segment n, n=0..7 */ @@ -354,12 +401,15 @@ #define LCD_WF55TO52_WF52_SHIFT (0) /* Bits 0-7: Waveform control field 52 segment bits */ #define LCD_WF55TO52_WF52_MASK (0xff << LCD_WF55TO52_WF52_SHIFT) # define LCD_WF55TO52_WF52_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF52_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF55TO52_WF53_SHIFT (8) /* Bits 8-15: Waveform control field 53 segment bits */ #define LCD_WF55TO52_WF53_MASK (0xff << LCD_WF55TO52_WF53_SHIFT) # define LCD_WF55TO52_WF53_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF53_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF55TO52_WF54_SHIFT (16) /* Bits 16-23: Waveform control field 54 segment bits */ #define LCD_WF55TO52_WF54_MASK (0xff << LCD_WF55TO52_WF54_SHIFT) # define LCD_WF55TO52_WF54_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF54_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF55TO52_WF55_SHIFT (24) /* Bits 24-31: Waveform control field 55 segment bits */ #define LCD_WF55TO52_WF55_MASK (0xff << LCD_WF55TO52_WF55_SHIFT) # define LCD_WF55TO52_WF55_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF55_SHIFT) /* Segment n, n=0..7 */ @@ -367,12 +417,15 @@ #define LCD_WF59TO56_WF56_SHIFT (0) /* Bits 0-7: Waveform control field 56 segment bits */ #define LCD_WF59TO56_WF56_MASK (0xff << LCD_WF59TO56_WF56_SHIFT) # define LCD_WF59TO56_WF56_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF56_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF59TO56_WF57_SHIFT (8) /* Bits 8-15: Waveform control field 57 segment bits */ #define LCD_WF59TO56_WF57_MASK (0xff << LCD_WF59TO56_WF57_SHIFT) # define LCD_WF59TO56_WF57_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF57_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF59TO56_WF58_SHIFT (16) /* Bits 16-23: Waveform control field 58 segment bits */ #define LCD_WF59TO56_WF58_MASK (0xff << LCD_WF59TO56_WF58_SHIFT) # define LCD_WF59TO56_WF58_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF58_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF59TO56_WF59_SHIFT (24) /* Bits 24-31: Waveform control field 59 segment bits */ #define LCD_WF59TO56_WF59_MASK (0xff << LCD_WF59TO56_WF59_SHIFT) # define LCD_WF59TO56_WF59_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF59_SHIFT) /* Segment n, n=0..7 */ @@ -380,26 +433,29 @@ #define LCD_WF63TO60_WF60_SHIFT (0) /* Bits 0-7: Waveform control field 60 segment bits */ #define LCD_WF63TO60_WF60_MASK (0xff << LCD_WF63TO60_WF60_SHIFT) # define LCD_WF63TO60_WF60_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF60_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF63TO60_WF61_SHIFT (8) /* Bits 8-15: Waveform control field 61 segment bits */ #define LCD_WF63TO60_WF61_MASK (0xff << LCD_WF63TO60_WF61_SHIFT) # define LCD_WF63TO60_WF61_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF61_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF63TO60_WF62_SHIFT (16) /* Bits 16-23: Waveform control field 62 segment bits */ #define LCD_WF63TO60_WF62_MASK (0xff << LCD_WF63TO60_WF62_SHIFT) # define LCD_WF63TO60_WF62_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF62_SHIFT) /* Segment n, n=0..7 */ + #define LCD_WF63TO60_WF63_SHIFT (24) /* Bits 24-31: Waveform control field 63 segment bits */ #define LCD_WF63TO60_WF63_MASK (0xff << LCD_WF63TO60_WF63_SHIFT) # define LCD_WF63TO60_WF63_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF63_SHIFT) /* Segment n, n=0..7 */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_smc.h b/arch/arm/src/kinetis/hardware/kinetis_smc.h index a1890dbb68..a1992f4a10 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_smc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_smc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_smc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_SMC_SRSH_OFFSET 0x0000 /* System Reset Status Register High */ #define KINETIS_SMC_SRSL_OFFSET 0x0001 /* System Reset Status Register Low */ #define KINETIS_SMC_PMPROT_OFFSET 0x0002 /* Power Mode Protection Register */ #define KINETIS_SMC_PMCTRL_OFFSET 0x0003 /* Power Mode Control Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_SMC_SRSH (KINETIS_SMC_BASE+KINETIS_SMC_SRSH_OFFSET) #define KINETIS_SMC_SRSL (KINETIS_SMC_BASE+KINETIS_SMC_SRSL_OFFSET) #define KINETIS_SMC_PMPROT (KINETIS_SMC_BASE+KINETIS_SMC_PMPROT_OFFSET) #define KINETIS_SMC_PMCTRL (KINETIS_SMC_BASE+KINETIS_SMC_PMCTRL_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* System Reset Status Register High */ @@ -75,6 +75,7 @@ #define SMC_PMPROT_ALLS (1 << 4) /* Bit 4: Allow low leakage stop mode */ #define SMC_PMPROT_AVLP (1 << 5) /* Bit 5: Allow very low power modes */ /* Bits 6-7: Reserved */ + /* Power Mode Control Register */ #define SMC_PMCTRL_LPLLSM_SHIFT (0) /* Bits 0-2: Low Power, Low Leakage Stop Mode */ @@ -85,23 +86,25 @@ # define SMC_PMCTRL_LPLLSM_VLLS3 (5 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 3 */ # define SMC_PMCTRL_LPLLSM_VLLS2 (6 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 2 */ # define SMC_PMCTRL_LPLLSM_VLLS1 (7 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 1 */ + /* Bits 3-4: Reserved */ #define SMC_PMCTRL_RUNM_SHIFT (5) /* Bits 5-6: Run Mode Enable */ #define SMC_PMCTRL_RUNM_MASK (3 << SMC_PMCTRL_RUNM_SHIFT) # define SMC_PMCTRL_RUNM_NORMAL (0 << SMC_PMCTRL_RUNM_SHIFT) /* Normal run mode */ # define SMC_PMCTRL_RUNM_VLP (2 << SMC_PMCTRL_RUNM_SHIFT) /* Very low power run mode */ + #define SMC_PMCTRL_LPWUI (1 << 7) /* Bit 7: Low Power Wake Up on Interrupt */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_tsi.h b/arch/arm/src/kinetis/hardware/kinetis_tsi.h index 88798c65ef..a2de3b0a01 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_tsi.h +++ b/arch/arm/src/kinetis/hardware/kinetis_tsi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_tsi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_TSI_GENCS_OFFSET 0x0000 /* General Control and Status Register */ #define KINETIS_TSI_SCANC_OFFSET 0x0004 /* SCAN control register */ @@ -41,6 +41,7 @@ #define KINETIS_TSI_STATUS_OFFSET 0x000c /* Status Register */ #define KINETIS_TSI_CNTR_OFFSET(n) (0x0100+(((n)-1)<<1) /* Counter Register n */ + #define KINETIS_TSI_CNTR1_OFFSET 0x0100 /* Counter Register 1 */ #define KINETIS_TSI_CNTR3_OFFSET 0x0104 /* Counter Register 3 */ #define KINETIS_TSI_CNTR5_OFFSET 0x0108 /* Counter Register 5 */ @@ -51,6 +52,7 @@ #define KINETIS_TSI_CNTR15_OFFSET 0x011c /* Counter Register 15 */ #define KINETIS_TSI_THRESHLD_OFFSET(n) (0x0120+((n)<<2)) /* Channel n threshold register */ + #define KINETIS_TSI_THRESHLD0_OFFSET 0x0120 /* Channel 0 threshold register */ #define KINETIS_TSI_THRESHLD1_OFFSET 0x0124 /* Channel 1 threshold register */ #define KINETIS_TSI_THRESHLD2_OFFSET 0x0128 /* Channel 2 threshold register */ @@ -68,7 +70,7 @@ #define KINETIS_TSI_THRESHLD14_OFFSET 0x0158 /* Channel 14 threshold register */ #define KINETIS_TSI_THRESHLD15_OFFSET 0x015c /* Channel 15 threshold register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_TSI0_GENCS (KINETIS_TSI0_BASE+KINETIS_TSI_GENCS_OFFSET) #define KINETIS_TSI0_SCANC (KINETIS_TSI0_BASE+KINETIS_TSI_SCANC_OFFSET) @@ -103,7 +105,7 @@ #define KINETIS_TSI0_THRESHLD14 (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD14_OFFSET) #define KINETIS_TSI0_THRESHLD15 (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD15_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* General Control and Status Register */ @@ -117,7 +119,7 @@ #define TSI_GENCS_SWTS (1 << 8) /* Bit 8: Software trigger start */ #define TSI_GENCS_SCNIP (1 << 9) /* Bit 9: Scan-in-progress status */ /* Bits 10-11: Reserved */ -#define TSI_GENCS_OVRF (1 << 12) /* Bit 12: Overrun error flag +#define TSI_GENCS_OVRF (1 << 12) /* Bit 12: Overrun error flag */ #define TSI_GENCS_EXTERF (1 << 13) /* Bit 13: External electrode error occurred */ #define TSI_GENCS_OUTRGF (1 << 14) /* Bit 14: Out of Range Flag */ #define TSI_GENCS_EOSF (1 << 15) /* Bit 15: End of scan flag */ @@ -131,9 +133,11 @@ # define TSI_GENCS_PS_DIV32 (5 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 32 */ # define TSI_GENCS_PS_DIV64 (6 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 64 */ # define TSI_GENCS_PS_DIV128 (7 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 128 */ + #define TSI_GENCS_NSCN_SHIFT (19) /* Bits 19-23: Number of Consecutive Scans per Electrode */ #define TSI_GENCS_NSCN_MASK (31 << TSI_GENCS_NSCN_SHIFT) # define TSI_GENCS_NSCN_TIMES(n) (((n)-1) << TSI_GENCS_NSCN_SHIFT) /* n times per electrode, n=1..32 */ + #define TSI_GENCS_LPSCNITV_SHIFT (24) /* Bits 24-27: TSI Low Power Mode Scan Interval */ #define TSI_GENCS_LPSCNITV_MASK (15 << TSI_GENCS_LPSCNITV_SHIFT) # define TSI_GENCS_LPSCNITV_1MS (0 << TSI_GENCS_LPSCNITV_SHIFT) /* 1 ms scan interval */ @@ -152,8 +156,10 @@ # define TSI_GENCS_LPSCNITV_300MS (13 << TSI_GENCS_LPSCNITV_SHIFT) /* 300 ms scan interval */ # define TSI_GENCS_LPSCNITV_400MS (14 << TSI_GENCS_LPSCNITV_SHIFT) /* 400 ms scan interval */ # define TSI_GENCS_LPSCNITV_500MS (15 << TSI_GENCS_LPSCNITV_SHIFT) /* 500 ms scan interval */ + #define TSI_GENCS_LPCLKS (1 << 28) /* Bit 28: Low Power Mode Clock Source Selection */ /* Bits 29-31: Reserved */ + /* SCAN control register */ #define TSI_SCANC_AMPSC_SHIFT (0) /* Bits 0-2: Active mode prescaler */ @@ -166,17 +172,20 @@ # define TSI_SCANC_AMPSC_DIV32 (5 << TSI_SCANC_AMPSC_SHIFT) /* Input clock source / 32 */ # define TSI_SCANC_AMPSC_DIV64 (6 << TSI_SCANC_AMPSC_SHIFT) /* Input clock source / 64 */ # define TSI_SCANC_AMPSC_DIV128 (7 << TSI_SCANC_AMPSC_SHIFT) /* Input clock source / 128 */ + #define TSI_SCANC_AMCLKS_SHIFT (3) /* Bits 3-4: Active mode clock source */ #define TSI_SCANC_AMCLKS_MASK (3 << TSI_SCANC_AMCLKS_SHIFT) # define TSI_SCANC_AMCLKS_BUSCLK (0 << TSI_SCANC_AMCLKS_SHIFT) /* Bus Clock */ # define TSI_SCANC_AMCLKS_MCGIRCLK (1 << TSI_SCANC_AMCLKS_SHIFT) /* MCGIRCLK */ # define TSI_SCANC_AMCLKS_OSCERCLK (2 << TSI_SCANC_AMCLKS_SHIFT) /* OSCERCLK */ + #define TSI_SCANC_AMCLKDIV (1 << 5) /* Bit 5: Active mode clock divider */ /* Bits 6-7: Reserved */ #define TSI_SCANC_SMOD_SHIFT (8) /* Bits 8-15: Scan modulo */ #define TSI_SCANC_SMOD_MASK (0xff << TSI_SCANC_SMOD_SHIFT) # define TSI_SCANC_SMOD_CONTINUOUS (0 << TSI_SCANC_SMOD_SHIFT) # define TSI_SCANC_SMOD(n) ((n) << TSI_SCANC_SMOD_SHIFT) + #define TSI_SCANC_DELVOL_SHIFT (16) /* Bits 16-18: Delta voltage select applied to analog oscillators */ #define TSI_SCANC_DELVOL_MASK (7 << TSI_SCANC_DELVOL_SHIFT) # define TSI_SCANC_DELVOL_100MV (0 << TSI_SCANC_DELVOL_SHIFT) /* 100 mV delta voltage */ @@ -187,9 +196,11 @@ # define TSI_SCANC_DELVOL_400MV (5 << TSI_SCANC_DELVOL_SHIFT) /* 400 mV delta voltage */ # define TSI_SCANC_DELVOL_500MV (6 << TSI_SCANC_DELVOL_SHIFT) /* 500 mV delta voltage */ # define TSI_SCANC_DELVOL_600MV (7 << TSI_SCANC_DELVOL_SHIFT) /* 600 mV delta voltage */ + #define TSI_SCANC_EXTCHRG_SHIFT (19) /* Bits 19-23: External oscillator charge current select */ #define TSI_SCANC_EXTCHRG_MASK (31 << TSI_SCANC_EXTCHRG_SHIFT) # define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */ + #define TSI_SCANC_CAPTRM_SHIFT (24) /* Bits 24-26: Internal capacitance trim value */ #define TSI_SCANC_CAPTRM_MASK (7 << TSI_SCANC_CAPTRM_SHIFT) #define TSI_SCANC_CAPTRM_0p5PF (0 << TSI_SCANC_CAPTRM_SHIFT) /* 0.5 pF internal reference capacitance */ @@ -200,6 +211,7 @@ #define TSI_SCANC_CAPTRM_1p0PF (5 << TSI_SCANC_CAPTRM_SHIFT) /* 1.0 pF internal reference capacitance */ #define TSI_SCANC_CAPTRM_1p1PF (6 << TSI_SCANC_CAPTRM_SHIFT) /* 1.1 pF internal reference capacitance */ #define TSI_SCANC_CAPTRM_1p2PF (7 << TSI_SCANC_CAPTRM_SHIFT) /* 1.2 pF internal reference capacitance */ + #define TSI_SCANC_REFCHRG_SHIFT (27) /* Bits 27-31: Reference oscillator charge current select */ #define TSI_SCANC_REFCHRG_MASK (31 << TSI_SCANC_REFCHRG_SHIFT) # define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */ @@ -222,11 +234,15 @@ #define TSI_PEN13 (1 << 13) /* Bit 13: TSI pin 13 enable */ #define TSI_PEN14 (1 << 14) /* Bit 14: TSI pin 14 enable */ #define TSI_PEN15 (1 << 15) /* Bit 15: TSI pin 15 enable */ + #define TSI_PEN(n) (1 << (n)) /* Bit n: TSI pin n enable, n=0..15 */ + #define TSI_PEN_LPSP_SHIFT (16) /* Bits 16-19: Low-power scan pin */ #define TSI_PEN_LPSP_MASK (15 << TSI_PEN_LPSP_SHIFT) # define TSI_PEN_LPSP(n) ((n) << TSI_PEN_LPSP_SHIFT) /* TSI_IN[n] active in low power mode */ + /* Bits 20-31: Reserved */ + /* Status Register */ #define TSI_STATUS_ORNGF0 (1 << 0) /* Bit 0: Touch Sensing Electrode Out-of-Range Flag 0 */ @@ -245,8 +261,11 @@ #define TSI_STATUS_ORNGF13 (1 << 13) /* Bit 13: Touch Sensing Electrode Out-of-Range Flag 13 */ #define TSI_STATUS_ORNGF14 (1 << 14) /* Bit 14: Touch Sensing Electrode Out-of-Range Flag 14 */ #define TSI_STATUS_ORNGF15 (1 << 15) /* Bit 15: Touch Sensing Electrode Out-of-Range Flag 15 */ + #define TSI_STATUS_ORNGF(n) (1 << (n)) /* Bits 0-15: Touch Sensing Electrode Out-of-Range Flag n, n=0..15 */ + #define TSI_STATUS_ERROF(n) (1 << ((n)+16)) /* Bits 16-31: TouchSensing Error Flag n, n=0..15 */ + #define TSI_STATUS_ERROF0 (1 << 16) /* Bit 16: TouchSensing Error Flag 0 */ #define TSI_STATUS_ERROF1 (1 << 17) /* Bit 17: TouchSensing Error Flag 1 */ #define TSI_STATUS_ERROF2 (1 << 18) /* Bit 18: TouchSensing Error Flag 2 */ @@ -281,16 +300,16 @@ #define TSI_THRESHLD_LTHH_SHIFT (16) /* Bits 16-31: Low threshold value */ #define TSI_THRESHLD_LTHH_MASK (0xffff << TSI_THRESHLD_LTHH_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_usbdcd.h b/arch/arm/src/kinetis/hardware/kinetis_usbdcd.h index 0e73fc7098..a4e0ecec9e 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_usbdcd.h +++ b/arch/arm/src/kinetis/hardware/kinetis_usbdcd.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_usbdcd.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */ #define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */ @@ -47,7 +47,7 @@ # define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */ #endif -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_USBDCD_CONTROL (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CONTROL_OFFSET) #define KINETIS_USBDCD_CLOCK (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CLOCK_OFFSET) @@ -61,7 +61,7 @@ # define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET) #endif -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Control Register */ #define USBDCD_CONTROL_IACK (1 << 0) /* Bit 0: Interrupt Acknowledge */ @@ -73,13 +73,16 @@ #define USBDCD_CONTROL_START (1 << 24) /* Bit 24: Start Change Detection Sequence */ #define USBDCD_CONTROL_SR (1 << 25) /* Bit 25: Software Reset */ /* Bits 26-31: Reserved */ + /* Clock Register */ #define USBDCD_CLOCK_UNIT (1 << 0) /* Bit 0: Unit of measurement encoding for Clock Speed */ /* Bit 1: Reserved */ #define USBDCD_CLOCK_SPEED_SHIFT (2) /* Bits 2-11: Value of Clock Speed */ #define USBDCD_CLOCK_SPEED_MASK (0x3ff << USBDCD_CLOCK_SPEED_SHIFT) /* Bits 12-31: Reserved */ + /* Status Register */ + /* Bits 0-15: Reserved */ #define USBDCD_STATUS_SEQ_RES_SHIFT (16) /* Bits 16-17: Charger Detection Sequence Results */ #define USBDCD_STATUS_SEQ_RES_MASK (3 << USBDCD_STATUS_SEQ_RES_SHIFT) @@ -87,16 +90,19 @@ # define USBDCD_STATUS_SEQ_RES_STD (1 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Standard host */ # define USBDCD_STATUS_SEQ_RES_CHGPORT (2 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Charging port */ # define USBDCD_STATUS_SEQ_RES_DEDCTD (3 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Dedicated charge */ + #define USBDCD_STATUS_SEQ_STAT_SHIFT (18) /* Bits 18-19: Charger Detection Sequence Stat */ #define USBDCD_STATUS_SEQ_STAT_MASK (3 << USBDCD_STATUS_SEQ_STAT_SHIFT) # define USBDCD_STATUS_SEQ_STAT_DISAB (0 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Not enabled or data pins not detected */ # define USBDCD_STATUS_SEQ_STAT_DATPIN (1 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Data pin contact detection complete */ # define USBDCD_STATUS_SEQ_STAT_CHGDET (2 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger detection is complete */ # define USBDCD_STATUS_SEQ_STAT_CHGTYPE (3 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger type detection complete */ + #define USBDCD_STATUS_ERR (1 << 20) /* Bit 20: Error Flag */ #define USBDCD_STATUS_TO (1 << 21) /* Bit 21: Timeout Flag */ #define USBDCD_STATUS_ACTIVE (1 << 22) /* Bit 22: Active Status Indicator */ /* Bits 23-31: Reserved */ + /* TIMER0 Register */ #define USBDCD_TIMER0_TUNITCON_SHIFT (0) /* Bits 0-11: Unit Connection Timer Elapse (in ms) */ @@ -105,6 +111,7 @@ #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16) /* Bits 16-25: Sequence Initiation Time */ #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3ff << USBDCD_TIMER0_TSEQ_INIT_SHIFT) /* Bits 26-31: Reserved */ + /* TIMER1 Register */ #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0) /* Bits 0-9: Time Period Comparator Enabled */ @@ -113,7 +120,9 @@ #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16) /* Bits 16-25: Time Period to Debounce D+ Signal */ #define USBDCD_TIMER1_TDCD_DBNC__MASK (0x3ff << USBDCD_TIMER1_TDCD_DBNC_SHIFT) /* Bits 26-31: Reserved */ + /* TIMER2 Register */ + /* Bits 26-31: Reserved */ #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16) /* Bits 16-25: Time Period Before Enabling D+ Pullup */ #define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3ff << USBDCD_TIMER2_TVDPSRC_CON_SHIFT) @@ -121,16 +130,16 @@ #define USBDCD_TIMER2_CHECK_DM_SHIFT (0) /* Bits 0-3: Time Before Check of D- Line */ #define USBDCD_TIMER2_CHECK_DM_MASK (15 << USBDCD_TIMER2_CHECK_DM_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_usbhs.h b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h index 7e3470a264..11ad28a5ae 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_usbhs.h +++ b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h @@ -1,4 +1,4 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_usbhs.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,28 +32,28 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBHS_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBHS_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ #define KINETIS_EHCI_NRHPORT 1 /* There is only a single root hub port */ #define KINETIS_USBHS_HCCR_OFFSET 0x100 /* Offset to EHCI Host Controller Capabiliy registers */ #define KINETIS_USBHS_HCOR_OFFSET 0x140 /* Offset to EHCI Host Controller Operational Registers */ -/* Register Offsets *************************************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_USBHS_ID_OFFSET 0x0000 /* Identification Register */ #define KINETIS_USBHS_HWGENERAL_OFFSET 0x0004 /* General Hardware Parameters */ @@ -163,7 +163,7 @@ #define KINETIS_USBHSDCD_TIMER2_BC11_OFFSET 0x0018 /* TIMER2_BC11 register */ #define KINETIS_USBHSDCD_TIMER2_BC12_OFFSET 0x001c /* TIMER2_BC12 register */ -/* Register Addresses ***********************************************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_USBHS_HCCR_BASE (KINETIS_USBHS_BASE + KINETIS_USBHS_HCCR_OFFSET) #define KINETIS_USBHS_HCOR_BASE (KINETIS_USBHS_BASE + KINETIS_USBHS_HCOR_OFFSET) @@ -276,557 +276,559 @@ #define KINETIS_USBHSDCD_TIMER2_BC11 (KINETIS_USBHSDCD_BASE + KINETIS_USBHSDCD_TIMER2_BC11_OFFSET) #define KINETIS_USBHSDCD_TIMER2_BC12 (KINETIS_USBHSDCD_BASE + KINETIS_USBHSDCD_TIMER2_BC12_OFFSET) -/* Register Bit-Field Definitions ***********************************************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Identification Register */ -#define USBHS_ID_VERSIONID_SHIFT (29) /* Bits 29-31: Version ID */ -#define USBHS_ID_VERSIONID_MASK (0x7 << USBHS_ID_VERSIONID_SHIFT) -#define USBHS_ID_VERSION_SHIFT (25) /* Bits 25-28: Version */ -#define USBHS_ID_VERSION_MASK (0xf << USBHS_ID_VERSION_SHIFT) -#define USBHS_ID_REVISION_SHIFT (21) /* Bits 21-24: Revision */ -#define USBHS_ID_REVISION_MASK (0xf << USBHS_ID_REVISION_SHIFT) -#define USBHS_ID_TAG_SHIFT (16) /* Bits 16-20: Tag */ -#define USBHS_ID_TAG_MASK (0x1f << USBHS_ID_TAG_SHIFT) - /* Bits 14-15: Reserved */ -#define USBHS_ID_NID_SHIFT (8) /* Bits 8-13: Ones complement version of ID */ -#define USBHS_ID_NID_MASK (0x3f << USBHS_ID_NID_SHIFT) - /* Bits 6-7: Reserved */ -#define USBHS_ID_ID_SHIFT (0) /* Bits 0-5: ID Configuration number */ -#define USBHS_ID_ID_MASK (0x3f << USBHS_ID_ID_SHIFT) +#define USBHS_ID_VERSIONID_SHIFT (29) /* Bits 29-31: Version ID */ +#define USBHS_ID_VERSIONID_MASK (0x7 << USBHS_ID_VERSIONID_SHIFT) +#define USBHS_ID_VERSION_SHIFT (25) /* Bits 25-28: Version */ +#define USBHS_ID_VERSION_MASK (0xf << USBHS_ID_VERSION_SHIFT) +#define USBHS_ID_REVISION_SHIFT (21) /* Bits 21-24: Revision */ +#define USBHS_ID_REVISION_MASK (0xf << USBHS_ID_REVISION_SHIFT) +#define USBHS_ID_TAG_SHIFT (16) /* Bits 16-20: Tag */ +#define USBHS_ID_TAG_MASK (0x1f << USBHS_ID_TAG_SHIFT) + /* Bits 14-15: Reserved */ +#define USBHS_ID_NID_SHIFT (8) /* Bits 8-13: Ones complement version of ID */ +#define USBHS_ID_NID_MASK (0x3f << USBHS_ID_NID_SHIFT) + /* Bits 6-7: Reserved */ +#define USBHS_ID_ID_SHIFT (0) /* Bits 0-5: ID Configuration number */ +#define USBHS_ID_ID_MASK (0x3f << USBHS_ID_ID_SHIFT) /* General Hardware Parameters Register */ - /* Bits 11-31: Reserved */ -#define USBHS_HWGENERAL_SM_SHIFT (9) /* Bits 9-10: Serial mode */ -#define USBHS_HWGENERAL_SM_MASK (0x3 << USBHS_HWGENERAL_SM_SHIFT) -#define USBHS_HWGENERAL_PHYM_SHIFT (6) /* Bits 6-8: PHY Mode */ -#define USBHS_HWGENERAL_PHYM_MASK (0x7 << USBHS_HWGENERAL_PHYM_SHIFT) -#define USBHS_HWGENERAL_PHYW_SHIFT (4) /* Bits 4-5: PHY Width */ -#define USBHS_HWGENERAL_PHYW_MASK (0x3 << USBHS_HWGENERAL_PHYW_SHIFT) - /* Bits 0-3: Reserved */ + /* Bits 11-31: Reserved */ +#define USBHS_HWGENERAL_SM_SHIFT (9) /* Bits 9-10: Serial mode */ +#define USBHS_HWGENERAL_SM_MASK (0x3 << USBHS_HWGENERAL_SM_SHIFT) +#define USBHS_HWGENERAL_PHYM_SHIFT (6) /* Bits 6-8: PHY Mode */ +#define USBHS_HWGENERAL_PHYM_MASK (0x7 << USBHS_HWGENERAL_PHYM_SHIFT) +#define USBHS_HWGENERAL_PHYW_SHIFT (4) /* Bits 4-5: PHY Width */ +#define USBHS_HWGENERAL_PHYW_MASK (0x3 << USBHS_HWGENERAL_PHYW_SHIFT) + /* Bits 0-3: Reserved */ /* Host Hardware Parameters Register */ -#define USBHS_HWHOST_TTPER_SHIFT (24) /* Bits 24-31: Transaction translator periodic contexts */ -#define USBHS_HWHOST_TTPER_MASK (0xff << USBHS_HWHOST_TTPER_SHIFT) -#define USBHS_HWHOST_TTASY_SHIFT (16) /* Bits 16-23: Transaction translator contexts */ -#define USBHS_HWHOST_TTASY_MASK (0xff << USBHS_HWHOST_TTASY_SHIFT) - /* Bits 5-14: Reserved */ -#define USBHS_HWHOST_NPORT_SHIFT (1) /* Bits 1-3: Number of Ports */ -#define USBHS_HWHOST_NPORT_MASK (0x7 << USBHS_HWHOST_NPORT_SHIFT) -#define USBHS_HWHOST_HC (1 << 0) /* Bit 0: Host Capable */ +#define USBHS_HWHOST_TTPER_SHIFT (24) /* Bits 24-31: Transaction translator periodic contexts */ +#define USBHS_HWHOST_TTPER_MASK (0xff << USBHS_HWHOST_TTPER_SHIFT) +#define USBHS_HWHOST_TTASY_SHIFT (16) /* Bits 16-23: Transaction translator contexts */ +#define USBHS_HWHOST_TTASY_MASK (0xff << USBHS_HWHOST_TTASY_SHIFT) + /* Bits 5-14: Reserved */ +#define USBHS_HWHOST_NPORT_SHIFT (1) /* Bits 1-3: Number of Ports */ +#define USBHS_HWHOST_NPORT_MASK (0x7 << USBHS_HWHOST_NPORT_SHIFT) +#define USBHS_HWHOST_HC (1 << 0) /* Bit 0: Host Capable */ /* Device Hardware Parameters Register */ - /* Bits 6-31: Reserved */ -#define USBHS_HWDEVICE_DEVEP_SHIFT (1) /* Bits 1-5: Device endpoints */ -#define USBHS_HWDEVICE_DEVEP_MASK (0x1f << USBHS_HWDEVICE_DEVEP_SHIFT) -#define USBHS_HWDEVICE_DC (1 << 0) /* Bit 0: Device Capable */ + /* Bits 6-31: Reserved */ +#define USBHS_HWDEVICE_DEVEP_SHIFT (1) /* Bits 1-5: Device endpoints */ +#define USBHS_HWDEVICE_DEVEP_MASK (0x1f << USBHS_HWDEVICE_DEVEP_SHIFT) +#define USBHS_HWDEVICE_DC (1 << 0) /* Bit 0: Device Capable */ /* Transmit Buffer Hardware Parameters Register */ -#define USBHS_HWTXBUF_TXLC (1 << 31) /* Bit 31: Transmit local Context Registers */ - /* Bits 24-30: Reserved */ -#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16) /* Bits 16-23: Transmit Channel Address */ -#define USBHS_HWTXBUF_TXCHANADD_MASK (0xff << USBHS_HWTXBUF_TXCHANADD_SHIFT) -#define USBHS_HWTXBUF_TXADD_SHIFT (8) /* Bits 8-15: Transmit Address */ -#define USBHS_HWTXBUF_TXADD_MASK (0xff << USBHS_HWTXBUF_TXADD_SHIFT) -#define USBHS_HWTXBUF_TXBURST_SHIFT (0) /* Bits 0-7: Transmit Burst */ -#define USBHS_HWTXBUF_TXBURST_MASK (0xff << USBHS_HWTXBUF_TXBURST_SHIFT) +#define USBHS_HWTXBUF_TXLC (1 << 31) /* Bit 31: Transmit local Context Registers */ + /* Bits 24-30: Reserved */ +#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16) /* Bits 16-23: Transmit Channel Address */ +#define USBHS_HWTXBUF_TXCHANADD_MASK (0xff << USBHS_HWTXBUF_TXCHANADD_SHIFT) +#define USBHS_HWTXBUF_TXADD_SHIFT (8) /* Bits 8-15: Transmit Address */ +#define USBHS_HWTXBUF_TXADD_MASK (0xff << USBHS_HWTXBUF_TXADD_SHIFT) +#define USBHS_HWTXBUF_TXBURST_SHIFT (0) /* Bits 0-7: Transmit Burst */ +#define USBHS_HWTXBUF_TXBURST_MASK (0xff << USBHS_HWTXBUF_TXBURST_SHIFT) /* Receive Buffer Hardware Parameters Register */ - /* Bits 16-31: Reserved */ -#define USBHS_HWRXBUF_RXADD_SHIFT (8) /* Bits 8-15: Receive Address */ -#define USBHS_HWRXBUF_RXADD_MASK (0xff << USBHS_HWRXBUF_RXADD_SHIFT) -#define USBHS_HWRXBUF_RXBURST_SHIFT (0) /* Bits 0-7: Receive Burst */ -#define USBHS_HWRXBUF_RXBURST_MASK (0xff << USBHS_HWRXBUF_RXBURST_SHIFT) + /* Bits 16-31: Reserved */ +#define USBHS_HWRXBUF_RXADD_SHIFT (8) /* Bits 8-15: Receive Address */ +#define USBHS_HWRXBUF_RXADD_MASK (0xff << USBHS_HWRXBUF_RXADD_SHIFT) +#define USBHS_HWRXBUF_RXBURST_SHIFT (0) /* Bits 0-7: Receive Burst */ +#define USBHS_HWRXBUF_RXBURST_MASK (0xff << USBHS_HWRXBUF_RXBURST_SHIFT) /* General Purpose Timer n Load Register */ - /* Bits 24-31: Reserved */ -#define USBHS_GPTIMERnLD_GPTLD_SHIFT (0) /* Bits 0-23: Value to be loaded into the countdown timer on reset */ -#define USBHS_GPTIMERnLD_GPTLD_MASK (0xffffff << USBHS_GPTIMERnLD_GPTLD_SHIFT) + /* Bits 24-31: Reserved */ +#define USBHS_GPTIMERnLD_GPTLD_SHIFT (0) /* Bits 0-23: Value to be loaded into the countdown timer on reset */ +#define USBHS_GPTIMERnLD_GPTLD_MASK (0xffffff << USBHS_GPTIMERnLD_GPTLD_SHIFT) /* General Purpose Timer n Control Register */ -#define USBHS_GPTIMERnCTL_RUN (1 << 31) /* Bit 31: Timer Run */ -#define USBHS_GPTIMERnCTL_RST (1 << 30) /* Bit 30: Timer Reset */ - /* Bits 25-29: Reserved */ -#define USBHS_GPTIMERnCTL_MODE (1 << 24) /* Bit 24: Timer Mode */ -#define USBHS_GPTIMERnCTL_GPTCNT_SHIFT (0) /* Bits 0-23: Timer Count */ -#define USBHS_GPTIMERnCTL_GPTCNT_MASK (0xffffff << USBHS_GPTIMERnCTL_GPTCNT_SHIFT) +#define USBHS_GPTIMERnCTL_RUN (1 << 31) /* Bit 31: Timer Run */ +#define USBHS_GPTIMERnCTL_RST (1 << 30) /* Bit 30: Timer Reset */ + /* Bits 25-29: Reserved */ +#define USBHS_GPTIMERnCTL_MODE (1 << 24) /* Bit 24: Timer Mode */ +#define USBHS_GPTIMERnCTL_GPTCNT_SHIFT (0) /* Bits 0-23: Timer Count */ +#define USBHS_GPTIMERnCTL_GPTCNT_MASK (0xffffff << USBHS_GPTIMERnCTL_GPTCNT_SHIFT) /* System Bus Interface Configuration Register */ - /* Bits 3-31: Reserved */ -#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0) /* Bits 0-2: Burst mode */ -#define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7 << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT) + /* Bits 3-31: Reserved */ +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0) /* Bits 0-2: Burst mode */ +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7 << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT) -/* Host Controller Interface Version and Capability Registers Length Register */ +/* Host Controller Interface Version and + * Capability Registers Length Register + */ -#define USBHS_HCIVERSION_HCIVERSION_SHIFT (16) /* Bits 16-31: EHCI revision number */ -#define USBHS_HCIVERSION_HCIVERSION_MASK (0xffff << USBHS_HCIVERSION_HCIVERSION_SHIFT) - /* Bits 8-15: Reserved */ -#define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0) /* Bits 0-7: Capability registers length */ -#define USBHS_HCIVERSION_CAPLENGTH_MASK (0xff << USBHS_HCIVERSION_CAPLENGTH_SHIFT) +#define USBHS_HCIVERSION_HCIVERSION_SHIFT (16) /* Bits 16-31: EHCI revision number */ +#define USBHS_HCIVERSION_HCIVERSION_MASK (0xffff << USBHS_HCIVERSION_HCIVERSION_SHIFT) + /* Bits 8-15: Reserved */ +#define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0) /* Bits 0-7: Capability registers length */ +#define USBHS_HCIVERSION_CAPLENGTH_MASK (0xff << USBHS_HCIVERSION_CAPLENGTH_SHIFT) /* Host Controller Structural Parameters Register */ - /* Bits 28-31: Reserved */ -#define USBHS_HCSPARAMS_N_TT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */ -#define USBHS_HCSPARAMS_N_TT_MASK (0xf << USBHS_HCSPARAMS_N_TT_SHIFT) -#define USBHS_HCSPARAMS_N_PTT_SHIFT (20) /* Bits 20-23: Ports per Transaction Translator */ -#define USBHS_HCSPARAMS_N_PTT_MASK (0xf << USBHS_HCSPARAMS_N_PTT_SHIFT) - /* Bits 17-19: Reserved */ -#define USBHS_HCSPARAMS_PI (1 << 16) /* Bit 16: Port Indicators */ -#define USBHS_HCSPARAMS_N_CC_SHIFT (12) /* Bits 12-15: Number of Companion Controllers */ -#define USBHS_HCSPARAMS_N_CC_MASK (0xf << USBHS_HCSPARAMS_N_CC_SHIFT) -#define USBHS_HCSPARAMS_N_PCC_SHIFT (8) /* Bits 8-11: Number Ports per CC */ -#define USBHS_HCSPARAMS_N_PCC_MASK (0xf << USBHS_HCSPARAMS_N_PCC_SHIFT) - /* Bits 5-7: Reserved */ -#define USBHS_HCSPARAMS_PPC (1 << 4) /* Bit 4: Power Port Control */ -#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0) /* Bits 0-3: Number of Ports */ -#define USBHS_HCSPARAMS_N_PORTS_MASK (0xf << USBHS_HCSPARAMS_N_PORTS_SHIFT) + /* Bits 28-31: Reserved */ +#define USBHS_HCSPARAMS_N_TT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */ +#define USBHS_HCSPARAMS_N_TT_MASK (0xf << USBHS_HCSPARAMS_N_TT_SHIFT) +#define USBHS_HCSPARAMS_N_PTT_SHIFT (20) /* Bits 20-23: Ports per Transaction Translator */ +#define USBHS_HCSPARAMS_N_PTT_MASK (0xf << USBHS_HCSPARAMS_N_PTT_SHIFT) + /* Bits 17-19: Reserved */ +#define USBHS_HCSPARAMS_PI (1 << 16) /* Bit 16: Port Indicators */ +#define USBHS_HCSPARAMS_N_CC_SHIFT (12) /* Bits 12-15: Number of Companion Controllers */ +#define USBHS_HCSPARAMS_N_CC_MASK (0xf << USBHS_HCSPARAMS_N_CC_SHIFT) +#define USBHS_HCSPARAMS_N_PCC_SHIFT (8) /* Bits 8-11: Number Ports per CC */ +#define USBHS_HCSPARAMS_N_PCC_MASK (0xf << USBHS_HCSPARAMS_N_PCC_SHIFT) + /* Bits 5-7: Reserved */ +#define USBHS_HCSPARAMS_PPC (1 << 4) /* Bit 4: Power Port Control */ +#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0) /* Bits 0-3: Number of Ports */ +#define USBHS_HCSPARAMS_N_PORTS_MASK (0xf << USBHS_HCSPARAMS_N_PORTS_SHIFT) /* Host Controller Capability Parameters Register */ - /* Bits 16-31: Reserved */ -#define USBHS_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ -#define USBHS_HCCPARAMS_EECP_MASK (0xff << USBHS_HCCPARAMS_EECP_SHIFT) -#define USBHS_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ -#define USBHS_HCCPARAMS_IST_MASK (0xf << USBHS_HCCPARAMS_IST_SHIFT) - /* Bit 3: Reserved */ -#define USBHS_HCCPARAMS_ASP (1 << 2) /* Bit 2: Asynchronous Schedule Park capability */ -#define USBHS_HCCPARAMS_PFL (1 << 1) /* Bit 1: Programmable Frame List flag */ -#define USBHS_HCCPARAMS_ADC (1 << 0) /* Bit 0: 64-bit addressing capability */ + /* Bits 16-31: Reserved */ +#define USBHS_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ +#define USBHS_HCCPARAMS_EECP_MASK (0xff << USBHS_HCCPARAMS_EECP_SHIFT) +#define USBHS_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ +#define USBHS_HCCPARAMS_IST_MASK (0xf << USBHS_HCCPARAMS_IST_SHIFT) + /* Bit 3: Reserved */ +#define USBHS_HCCPARAMS_ASP (1 << 2) /* Bit 2: Asynchronous Schedule Park capability */ +#define USBHS_HCCPARAMS_PFL (1 << 1) /* Bit 1: Programmable Frame List flag */ +#define USBHS_HCCPARAMS_ADC (1 << 0) /* Bit 0: 64-bit addressing capability */ /* Device Controller Capability Parameters */ - /* Bits 9-31: Reserved */ -#define USBHS_DCCPARAMS_HC (1 << 8) /* Bit 8: Host Capable */ -#define USBHS_DCCPARAMS_DC (1 << 7) /* Bit 7: Device Capable */ - /* Bits 5-6: Reserved */ -#define USBHS_DCCPARAMS_DEN_SHIFT (0) /* Bits 0-4: Device Endpoint Number */ -#define USBHS_DCCPARAMS_DEN_MASK (0x1f << USBHS_DCCPARAMS_DEN_SHIFT) + /* Bits 9-31: Reserved */ +#define USBHS_DCCPARAMS_HC (1 << 8) /* Bit 8: Host Capable */ +#define USBHS_DCCPARAMS_DC (1 << 7) /* Bit 7: Device Capable */ + /* Bits 5-6: Reserved */ +#define USBHS_DCCPARAMS_DEN_SHIFT (0) /* Bits 0-4: Device Endpoint Number */ +#define USBHS_DCCPARAMS_DEN_MASK (0x1f << USBHS_DCCPARAMS_DEN_SHIFT) /* USB Command Register */ - /* Bits 24-31: Reserved */ -#define USBHS_USBCMD_ITC_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ -#define USBHS_USBCMD_ITC_MASK (0xff << USBHS_USBCMD_ITC_SHIFT) -#define USBHS_USBCMD_FS2 (1 << 15) /* Bit 15: Frame list Size 2 */ -#define USBHS_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD TripWire */ -#define USBHS_USBCMD_SUTW (1 << 13) /* Bit 13: Setup TripWire */ - /* Bit 12: Reserved */ -#define USBHS_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park mode Enable */ - /* Bit 10: Reserved */ -#define USBHS_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park mode count */ -#define USBHS_USBCMD_ASP_MASK (0x3 << USBHS_USBCMD_ASP_SHIFT) - /* Bit 7: Reserved */ -#define USBHS_USBCMD_IAA (1 << 6) /* Bit 6: Interrupt on Async Advance doorbell */ -#define USBHS_USBCMD_ASE (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ -#define USBHS_USBCMD_PSE (1 << 4) /* Bit 4: Periodic Schedule Enable */ -#define USBHS_USBCMD_FS_SHIFT (2) /* Bits 2-3: Frame list Size */ -#define USBHS_USBCMD_FS_MASK (0x3 << USBHS_USBCMD_FS_SHIFT) -#define USBHS_USBCMD_RST (1 << 1) /* Bit 1: Controller Reset */ -#define USBHS_USBCMD_RS (1 << 0) /* Bit 0: Run/Stop */ + /* Bits 24-31: Reserved */ +#define USBHS_USBCMD_ITC_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ +#define USBHS_USBCMD_ITC_MASK (0xff << USBHS_USBCMD_ITC_SHIFT) +#define USBHS_USBCMD_FS2 (1 << 15) /* Bit 15: Frame list Size 2 */ +#define USBHS_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD TripWire */ +#define USBHS_USBCMD_SUTW (1 << 13) /* Bit 13: Setup TripWire */ + /* Bit 12: Reserved */ +#define USBHS_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park mode Enable */ + /* Bit 10: Reserved */ +#define USBHS_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park mode count */ +#define USBHS_USBCMD_ASP_MASK (0x3 << USBHS_USBCMD_ASP_SHIFT) + /* Bit 7: Reserved */ +#define USBHS_USBCMD_IAA (1 << 6) /* Bit 6: Interrupt on Async Advance doorbell */ +#define USBHS_USBCMD_ASE (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ +#define USBHS_USBCMD_PSE (1 << 4) /* Bit 4: Periodic Schedule Enable */ +#define USBHS_USBCMD_FS_SHIFT (2) /* Bits 2-3: Frame list Size */ +#define USBHS_USBCMD_FS_MASK (0x3 << USBHS_USBCMD_FS_SHIFT) +#define USBHS_USBCMD_RST (1 << 1) /* Bit 1: Controller Reset */ +#define USBHS_USBCMD_RS (1 << 0) /* Bit 0: Run/Stop */ /* USB Status Register */ - /* Bits 26-31: Reserved */ -#define USBHS_USBSTS_TI1 (1 << 25) /* Bit 25: General purpose Timer 1 Interrupt */ -#define USBHS_USBSTS_TI0 (1 << 24) /* Bit 24: General purpose Timer 0 Interrupt */ - /* Bits 22-30: Reserved */ -#define USBHS_USBSTS_UPIUSB (1 << 19) /* Bit 19: host Periodic Interrupt */ -#define USBHS_USBSTS_UAI (1 << 18) /* Bit 18: USB host Asynchronous Interrupt */ - /* Bit 17: Reserved */ -#define USBHS_USBSTS_NAKI (1 << 16) /* Bit 16: NAK Interrupt */ -#define USBHS_USBSTS_AS (1 << 15) /* Bit 15: Asynchronous schedule Status */ -#define USBHS_USBSTS_PS (1 << 14) /* Bit 14: Periodic schedule Status */ -#define USBHS_USBSTS_RCL (1 << 13) /* Bit 13: Reclamation */ -#define USBHS_USBSTS_HCH (1 << 12) /* Bit 12: Host Controller Halted */ - /* Bits 9-11: Reserved */ -#define USBHS_USBSTS_SLI (1 << 8) /* Bit 8: Device-controller suspend */ -#define USBHS_USBSTS_SRI (1 << 7) /* Bit 7: SOF Received */ -#define USBHS_USBSTS_URI (1 << 6) /* Bit 6: USB Reset received */ -#define USBHS_USBSTS_AAI (1 << 5) /* Bit 5: Interrupt on Async Advance */ -#define USBHS_USBSTS_SEI (1 << 4) /* Bit 4: System Error */ -#define USBHS_USBSTS_FRI (1 << 3) /* Bit 3: Port Change detect */ -#define USBHS_USBSTS_PCI (1 << 2) /* Bit 2: Port Change detect */ -#define USBHS_USBSTS_UEI (1 << 1) /* Bit 1: USB Error Interrupt */ -#define USBHS_USBSTS_UI (1 << 0) /* Bit 0: USB Interrupt (USBINT) */ + /* Bits 26-31: Reserved */ +#define USBHS_USBSTS_TI1 (1 << 25) /* Bit 25: General purpose Timer 1 Interrupt */ +#define USBHS_USBSTS_TI0 (1 << 24) /* Bit 24: General purpose Timer 0 Interrupt */ + /* Bits 22-30: Reserved */ +#define USBHS_USBSTS_UPIUSB (1 << 19) /* Bit 19: host Periodic Interrupt */ +#define USBHS_USBSTS_UAI (1 << 18) /* Bit 18: USB host Asynchronous Interrupt */ + /* Bit 17: Reserved */ +#define USBHS_USBSTS_NAKI (1 << 16) /* Bit 16: NAK Interrupt */ +#define USBHS_USBSTS_AS (1 << 15) /* Bit 15: Asynchronous schedule Status */ +#define USBHS_USBSTS_PS (1 << 14) /* Bit 14: Periodic schedule Status */ +#define USBHS_USBSTS_RCL (1 << 13) /* Bit 13: Reclamation */ +#define USBHS_USBSTS_HCH (1 << 12) /* Bit 12: Host Controller Halted */ + /* Bits 9-11: Reserved */ +#define USBHS_USBSTS_SLI (1 << 8) /* Bit 8: Device-controller suspend */ +#define USBHS_USBSTS_SRI (1 << 7) /* Bit 7: SOF Received */ +#define USBHS_USBSTS_URI (1 << 6) /* Bit 6: USB Reset received */ +#define USBHS_USBSTS_AAI (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define USBHS_USBSTS_SEI (1 << 4) /* Bit 4: System Error */ +#define USBHS_USBSTS_FRI (1 << 3) /* Bit 3: Port Change detect */ +#define USBHS_USBSTS_PCI (1 << 2) /* Bit 2: Port Change detect */ +#define USBHS_USBSTS_UEI (1 << 1) /* Bit 1: USB Error Interrupt */ +#define USBHS_USBSTS_UI (1 << 0) /* Bit 0: USB Interrupt (USBINT) */ /* USB Interrupt Enable Register */ - /* Bits 26-31: Reserved */ -#define USBHS_USBINTR_TIE1 (1 << 25) /* Bit 25: General purpose Timer 1 Interrupt Enable */ -#define USBHS_USBINTR_TIE0 (1 << 24) /* Bit 24: General purpose Timer 0 Interrupt Enable */ - /* Bits 22-30: Reserved */ -#define USBHS_USBINTR_UPIE (1 << 19) /* Bit 19: USB host Periodic Interrupt Enable */ -#define USBHS_USBINTR_UAIE (1 << 18) /* Bit 18: USB host Asynchronous Interrupt Enable */ - /* Bit 17: Reserved */ -#define USBHS_USBINTR_NAKE (1 << 16) /* Bit 16: NAK Interrupt Enable */ - /* Bits 9-15: Reserved */ -#define USBHS_USBINTR_SLE (1 << 8) /* Bit 8: Sleep (DC suspend) Enable */ -#define USBHS_USBINTR_SRE (1 << 7) /* Bit 7: SOF-Received Enable */ -#define USBHS_USBINTR_URE (1 << 6) /* Bit 6: USB-Reset Enable */ -#define USBHS_USBINTR_AAE (1 << 5) /* Bit 5: Interrupt on Async advance Enable */ -#define USBHS_USBINTR_SEE (1 << 4) /* Bit 4: System Error Enable */ -#define USBHS_USBINTR_FRE (1 << 3) /* Bit 3: Frame list Rollover Enable */ -#define USBHS_USBINTR_PCE (1 << 2) /* Bit 2: Port Change detect Enable */ -#define USBHS_USBINTR_UEE (1 << 1) /* Bit 1: USB Error interrupt Enable */ -#define USBHS_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt Enable */ + /* Bits 26-31: Reserved */ +#define USBHS_USBINTR_TIE1 (1 << 25) /* Bit 25: General purpose Timer 1 Interrupt Enable */ +#define USBHS_USBINTR_TIE0 (1 << 24) /* Bit 24: General purpose Timer 0 Interrupt Enable */ + /* Bits 22-30: Reserved */ +#define USBHS_USBINTR_UPIE (1 << 19) /* Bit 19: USB host Periodic Interrupt Enable */ +#define USBHS_USBINTR_UAIE (1 << 18) /* Bit 18: USB host Asynchronous Interrupt Enable */ + /* Bit 17: Reserved */ +#define USBHS_USBINTR_NAKE (1 << 16) /* Bit 16: NAK Interrupt Enable */ + /* Bits 9-15: Reserved */ +#define USBHS_USBINTR_SLE (1 << 8) /* Bit 8: Sleep (DC suspend) Enable */ +#define USBHS_USBINTR_SRE (1 << 7) /* Bit 7: SOF-Received Enable */ +#define USBHS_USBINTR_URE (1 << 6) /* Bit 6: USB-Reset Enable */ +#define USBHS_USBINTR_AAE (1 << 5) /* Bit 5: Interrupt on Async advance Enable */ +#define USBHS_USBINTR_SEE (1 << 4) /* Bit 4: System Error Enable */ +#define USBHS_USBINTR_FRE (1 << 3) /* Bit 3: Frame list Rollover Enable */ +#define USBHS_USBINTR_PCE (1 << 2) /* Bit 2: Port Change detect Enable */ +#define USBHS_USBINTR_UEE (1 << 1) /* Bit 1: USB Error interrupt Enable */ +#define USBHS_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt Enable */ /* Frame Index Register */ - /* Bits 14_31: Reserved */ -#define USBHS_FRINDEX_FRINDEX_SHIFT (0) /* Bits 0-13: Frame Index */ -#define USBHS_FRINDEX_FRINDEX_MASK (0x3fff << USBHS_FRINDEX_FRINDEX_SHIFT) + /* Bits 14_31: Reserved */ +#define USBHS_FRINDEX_FRINDEX_SHIFT (0) /* Bits 0-13: Frame Index */ +#define USBHS_FRINDEX_FRINDEX_MASK (0x3fff << USBHS_FRINDEX_FRINDEX_SHIFT) /* Periodic Frame List Base Address Register */ -#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12) /* Bits 12-31: Base address */ -#define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xfffff << USBHS_PERIODICLISTBASE_PERBASE_SHIFT) - /* Bits 0-12: Reserved */ +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12) /* Bits 12-31: Base address */ +#define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xfffff << USBHS_PERIODICLISTBASE_PERBASE_SHIFT) + /* Bits 0-12: Reserved */ /* Device Address Register */ -#define USBHS_DEVICEADDR_USBADR_SHIFT (25) /* Bits 25-31: Device Address */ -#define USBHS_DEVICEADDR_USBADR_MASK (0x7f << USBHS_DEVICEADDR_USBADR_SHIFT) -#define USBHS_DEVICEADDR_USBADRA (1 << 24) /* Bit 24: Device Address Advance */ - /* Bits 0-23: Reserved */ +#define USBHS_DEVICEADDR_USBADR_SHIFT (25) /* Bits 25-31: Device Address */ +#define USBHS_DEVICEADDR_USBADR_MASK (0x7f << USBHS_DEVICEADDR_USBADR_SHIFT) +#define USBHS_DEVICEADDR_USBADRA (1 << 24) /* Bit 24: Device Address Advance */ + /* Bits 0-23: Reserved */ /* Current Asynchronous List Address Register */ -#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5) /* Bits 5-31: Link pointer low (LPL) */ -#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0x7ffffff << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT) - /* Bits 0-4: Reserved */ +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5) /* Bits 5-31: Link pointer low (LPL) */ +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0x7ffffff << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT) + /* Bits 0-4: Reserved */ /* Endpoint List Address Register */ -#define USBHS_EPLISTADDR_EPBASE_SHIFT (11) /* Bits 11-31: Endpoint list address */ -#define USBHS_EPLISTADDR_EPBASE_MASK (0x1fffff << USBHS_EPLISTADDR_EPBASE_SHIFT) - /* Bits 0-10: Reserved */ +#define USBHS_EPLISTADDR_EPBASE_SHIFT (11) /* Bits 11-31: Endpoint list address */ +#define USBHS_EPLISTADDR_EPBASE_MASK (0x1fffff << USBHS_EPLISTADDR_EPBASE_SHIFT) + /* Bits 0-10: Reserved */ /* Host TT Asynchronous Buffer Control */ - /* Bit 31: Reserved */ -#define USBHS_TTCTRL_TTHA_SHIFT (24) /* Bits 24-30: TT Hub Address */ -#define USBHS_TTCTRL_TTHA_MASK (0x7f << USBHS_TTCTRL_TTHA_SHIFT) - /* Bits 0-23: Reserved */ + /* Bit 31: Reserved */ +#define USBHS_TTCTRL_TTHA_SHIFT (24) /* Bits 24-30: TT Hub Address */ +#define USBHS_TTCTRL_TTHA_MASK (0x7f << USBHS_TTCTRL_TTHA_SHIFT) + /* Bits 0-23: Reserved */ /* Master Interface Data Burst Size Register */ - /* Bits 16-31: Reserved */ -#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX Burst length */ -#define USBHS_BURSTSIZE_TXPBURST_MASK (0xff << USBHS_BURSTSIZE_TXPBURST_SHIFT) -#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: Programmable RX Burst length */ -#define USBHS_BURSTSIZE_RXPBURST_MASK (0xff << USBHS_BURSTSIZE_RXPBURST_SHIFT) + /* Bits 16-31: Reserved */ +#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX Burst length */ +#define USBHS_BURSTSIZE_TXPBURST_MASK (0xff << USBHS_BURSTSIZE_TXPBURST_SHIFT) +#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: Programmable RX Burst length */ +#define USBHS_BURSTSIZE_RXPBURST_MASK (0xff << USBHS_BURSTSIZE_RXPBURST_SHIFT) /* Transmit FIFO Tuning Control Register */ - /* Bits 31-22: Reserved */ -#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) /* Bits 16-21: FIFO burst Threshold */ -#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3f << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT) - /* Bits 15-13: Reserved */ -#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8) /* Bits 8-12: Scheduler Health counter */ -#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1f << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT) - /* Bit 7: Reserved */ -#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0) /* Bits 0-6: Scheduler Overhead */ -#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7f << USBHS_TXFILLTUNING_TXSCHOH_SHIFT) + /* Bits 31-22: Reserved */ +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) /* Bits 16-21: FIFO burst Threshold */ +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3f << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT) + /* Bits 15-13: Reserved */ +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8) /* Bits 8-12: Scheduler Health counter */ +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1f << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT) + /* Bit 7: Reserved */ +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0) /* Bits 0-6: Scheduler Overhead */ +#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7f << USBHS_TXFILLTUNING_TXSCHOH_SHIFT) /* Endpoint NAK Register */ - /* Bits 20-31: Reserved */ -#define USBHS_ENDPTNAK_EPTN_SHIFT (16) /* Bits 16-19: TX Endpoint NAK */ -#define USBHS_ENDPTNAK_EPTN_MASK (0xf << USBHS_ENDPTNAK_EPTN_SHIFT) - /* Bits 4-15: Reserved */ -#define USBHS_ENDPTNAK_EPRN_SHIFT (0) /* Bits 0-3: RX Endpoint NAK */ -#define USBHS_ENDPTNAK_EPRN_MASK (0xf << USBHS_ENDPTNAK_EPRN_SHIFT) + /* Bits 20-31: Reserved */ +#define USBHS_ENDPTNAK_EPTN_SHIFT (16) /* Bits 16-19: TX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPTN_MASK (0xf << USBHS_ENDPTNAK_EPTN_SHIFT) + /* Bits 4-15: Reserved */ +#define USBHS_ENDPTNAK_EPRN_SHIFT (0) /* Bits 0-3: RX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPRN_MASK (0xf << USBHS_ENDPTNAK_EPRN_SHIFT) /* Endpoint NAK Enable Register */ - /* Bits 20-31: Reserved */ -#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16) /* Bits 16-19: TX Endpoint NAK */ -#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xf << USBHS_ENDPTNAKEN_EPTNE_SHIFT) - /* Bits 4-15: Reserved */ -#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0) /* Bits 0-3: RX Endpoint NAK */ -#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xf << USBHS_ENDPTNAKEN_EPRNE_SHIFT) + /* Bits 20-31: Reserved */ +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16) /* Bits 16-19: TX Endpoint NAK */ +#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xf << USBHS_ENDPTNAKEN_EPTNE_SHIFT) + /* Bits 4-15: Reserved */ +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0) /* Bits 0-3: RX Endpoint NAK */ +#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xf << USBHS_ENDPTNAKEN_EPRNE_SHIFT) /* Configure Flag Register (reserved) */ /* Port Status and Control Registers */ -#define USBHS_PORTSC1_PTS_SHIFT (30) /* Bits 30-31: Port Transceiver Select [1:0] */ -#define USBHS_PORTSC1_PTS_MASK (0x3 << USBHS_PORTSC1_PTS_SHIFT) - /* Bit 28-29: Reserved */ -#define USBHS_PORTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port Speed */ -#define USBHS_PORTSC1_PSPD_MASK (0x3 << USBHS_PORTSC1_PSPD_SHIFT) -# define USBHS_PORTSC1_PSPD_FS (0 << USBHS_PORTSC1_PSPD_SHIFT) /* Full-speed */ -# define USBHS_PORTSC1_PSPD_LS (1 << USBHS_PORTSC1_PSPD_SHIFT) /* Low-speed */ -# define USBHS_PORTSC1_PSPD_HS (2 << USBHS_PORTSC1_PSPD_SHIFT) /* High-speed */ +#define USBHS_PORTSC1_PTS_SHIFT (30) /* Bits 30-31: Port Transceiver Select [1:0] */ +#define USBHS_PORTSC1_PTS_MASK (0x3 << USBHS_PORTSC1_PTS_SHIFT) + /* Bit 28-29: Reserved */ +#define USBHS_PORTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port Speed */ +#define USBHS_PORTSC1_PSPD_MASK (0x3 << USBHS_PORTSC1_PSPD_SHIFT) +# define USBHS_PORTSC1_PSPD_FS (0 << USBHS_PORTSC1_PSPD_SHIFT) /* Full-speed */ +# define USBHS_PORTSC1_PSPD_LS (1 << USBHS_PORTSC1_PSPD_SHIFT) /* Low-speed */ +# define USBHS_PORTSC1_PSPD_HS (2 << USBHS_PORTSC1_PSPD_SHIFT) /* High-speed */ -#define USBHS_PORTSC1_PTS2 (1 << 25) /* Bit 25: Port Transceiver Select [2] */ -#define USBHS_PORTSC1_PFSC (1 << 24) /* Bit 24: Port force Full-Speed Connect */ -#define USBHS_PORTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend */ -#define USBHS_PORTSC1_WKOC (1 << 22) /* Bit 22: Wake on Over-Current enable */ -#define USBHS_PORTSC1_WKDS (1 << 21) /* Bit 21: Wake on Disconnect enable */ -#define USBHS_PORTSC1_WKCN (1 << 20) /* Bit 20: Wake on Connect enable */ -#define USBHS_PORTSC1_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ -#define USBHS_PORTSC1_PTC_MASK (0xf << USBHS_PORTSC1_PTC_SHIFT) -#define USBHS_PORTSC1_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ -#define USBHS_PORTSC1_PIC_MASK (0x3 << USBHS_PORTSC1_PIC_SHIFT) -#define USBHS_PORTSC1_PO (1 << 13) /* Bit 13: Port Owner */ -#define USBHS_PORTSC1_PP (1 << 12) /* Bit 12: Port Power */ -#define USBHS_PORTSC1_LS_SHIFT (10) /* Bits 10-11: Line Status */ -#define USBHS_PORTSC1_LS_MASK (0x3 << USBHS_PORTSC1_LS_SHIFT) -#define USBHS_PORTSC1_HSP (1 << 9) /* Bit 9: High Speed Port */ -#define USBHS_PORTSC1_PR (1 << 8) /* Bit 8: Port Reset */ -#define USBHS_PORTSC1_SUSP (1 << 7) /* Bit 7: Suspend */ -#define USBHS_PORTSC1_FPR (1 << 6) /* Bit 6: Force Port Resume */ -#define USBHS_PORTSC1_OCC (1 << 5) /* Bit 5: Over-Current Change */ -#define USBHS_PORTSC1_OCA (1 << 4) /* Bit 4: Over-current active */ -#define USBHS_PORTSC1_PEC (1 << 3) /* Bit 3: Port Enable/disable Change */ -#define USBHS_PORTSC1_PE (1 << 2) /* Bit 2: Port Enabled/disabled */ -#define USBHS_PORTSC1_CSC (1 << 1) /* Bit 1: Connect Change Status */ -#define USBHS_PORTSC1_CCS (1 << 0) /* Bit 0: Current Connect Status */ +#define USBHS_PORTSC1_PTS2 (1 << 25) /* Bit 25: Port Transceiver Select [2] */ +#define USBHS_PORTSC1_PFSC (1 << 24) /* Bit 24: Port force Full-Speed Connect */ +#define USBHS_PORTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend */ +#define USBHS_PORTSC1_WKOC (1 << 22) /* Bit 22: Wake on Over-Current enable */ +#define USBHS_PORTSC1_WKDS (1 << 21) /* Bit 21: Wake on Disconnect enable */ +#define USBHS_PORTSC1_WKCN (1 << 20) /* Bit 20: Wake on Connect enable */ +#define USBHS_PORTSC1_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ +#define USBHS_PORTSC1_PTC_MASK (0xf << USBHS_PORTSC1_PTC_SHIFT) +#define USBHS_PORTSC1_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ +#define USBHS_PORTSC1_PIC_MASK (0x3 << USBHS_PORTSC1_PIC_SHIFT) +#define USBHS_PORTSC1_PO (1 << 13) /* Bit 13: Port Owner */ +#define USBHS_PORTSC1_PP (1 << 12) /* Bit 12: Port Power */ +#define USBHS_PORTSC1_LS_SHIFT (10) /* Bits 10-11: Line Status */ +#define USBHS_PORTSC1_LS_MASK (0x3 << USBHS_PORTSC1_LS_SHIFT) +#define USBHS_PORTSC1_HSP (1 << 9) /* Bit 9: High Speed Port */ +#define USBHS_PORTSC1_PR (1 << 8) /* Bit 8: Port Reset */ +#define USBHS_PORTSC1_SUSP (1 << 7) /* Bit 7: Suspend */ +#define USBHS_PORTSC1_FPR (1 << 6) /* Bit 6: Force Port Resume */ +#define USBHS_PORTSC1_OCC (1 << 5) /* Bit 5: Over-Current Change */ +#define USBHS_PORTSC1_OCA (1 << 4) /* Bit 4: Over-current active */ +#define USBHS_PORTSC1_PEC (1 << 3) /* Bit 3: Port Enable/disable Change */ +#define USBHS_PORTSC1_PE (1 << 2) /* Bit 2: Port Enabled/disabled */ +#define USBHS_PORTSC1_CSC (1 << 1) /* Bit 1: Connect Change Status */ +#define USBHS_PORTSC1_CCS (1 << 0) /* Bit 0: Current Connect Status */ /* On-the-Go Status and Control Register */ - /* Bit 31: Reserved */ -#define USBHS_OTGSC_DPIE (1 << 30) /* Bit 30: Data Pulse Interrupt Enable */ -#define USBHS_OTGSC_MSE (1 << 29) /* Bit 29: 1 Milli-Second timer interrupt Enable */ -#define USBHS_OTGSC_BSEIE (1 << 28) /* Bit 28: B Session End Interrupt Enable */ -#define USBHS_OTGSC_BSVIE (1 << 27) /* Bit 27: B Session Valid Interrupt Enable */ -#define USBHS_OTGSC_ASVIE (1 << 26) /* Bit 26: A Session Valid Interrupt Enable */ -#define USBHS_OTGSC_AVVIE (1 << 25) /* Bit 25: A VBUS Valid Interrupt Enable */ -#define USBHS_OTGSC_IDIE (1 << 24) /* Bit 24: USB ID Interrupt Enable */ - /* Bit 23: Reserved */ -#define USBHS_OTGSC_DPIS (1 << 22) /* Bit 22: Data Pulse interrupt Status */ -#define USBHS_OTGSC_MSS (1 << 21) /* Bit 21: 1 Milli-Second timer interrupt Status */ -#define USBHS_OTGSC_BSEIS (1 << 20) /* Bit 20: B Session End Interrupt Status */ -#define USBHS_OTGSC_BSVIS (1 << 19) /* Bit 19: B Session Valid Interrupt Status */ -#define USBHS_OTGSC_ASVIS (1 << 18) /* Bit 18: A Session Valid Interrupt Status */ -#define USBHS_OTGSC_AVVIS (1 << 17) /* Bit 17: A VBUS Valid Interrupt Status */ -#define USBHS_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID Interrupt Status */ - /* Bit 15: Reserved */ -#define USBHS_OTGSC_DPS (1 << 14) /* Bit 14: Data bus Pulsing Status */ -#define USBHS_OTGSC_MST (1 << 13) /* Bit 13: 1 Milli-Second timer Toggle */ -#define USBHS_OTGSC_BSE (1 << 12) /* Bit 12: B Session End */ -#define USBHS_OTGSC_BSV (1 << 11) /* Bit 11: B Session Valid */ -#define USBHS_OTGSC_ASV (1 << 10) /* Bit 10: A Session Valid */ -#define USBHS_OTGSC_AVV (1 << 9) /* Bit 9: A VBus Valid */ -#define USBHS_OTGSC_ID (1 << 8) /* Bit 8: USB ID */ -#define USBHS_OTGSC_HABA (1 << 7) /* Bit 7: Hardware Assist B-Disconnect to A-connect */ - /* Bit 6: Reserved */ -#define USBHS_OTGSC_IDPU (1 << 5) /* Bit 5: ID Pull-Up */ -#define USBHS_OTGSC_DP (1 << 4) /* Bit 4: Data Pulsing */ -#define USBHS_OTGSC_OT (1 << 3) /* Bit 3: OTG Termination */ -#define USBHS_OTGSC_HAAR (1 << 2) /* Bit 2: Hardware Assist Auto-Reset */ -#define USBHS_OTGSC_VC (1 << 1) /* Bit 1: VBUS Charge */ -#define USBHS_OTGSC_VD (1 << 0) /* Bit 0: VBUS Discharge */ + /* Bit 31: Reserved */ +#define USBHS_OTGSC_DPIE (1 << 30) /* Bit 30: Data Pulse Interrupt Enable */ +#define USBHS_OTGSC_MSE (1 << 29) /* Bit 29: 1 Milli-Second timer interrupt Enable */ +#define USBHS_OTGSC_BSEIE (1 << 28) /* Bit 28: B Session End Interrupt Enable */ +#define USBHS_OTGSC_BSVIE (1 << 27) /* Bit 27: B Session Valid Interrupt Enable */ +#define USBHS_OTGSC_ASVIE (1 << 26) /* Bit 26: A Session Valid Interrupt Enable */ +#define USBHS_OTGSC_AVVIE (1 << 25) /* Bit 25: A VBUS Valid Interrupt Enable */ +#define USBHS_OTGSC_IDIE (1 << 24) /* Bit 24: USB ID Interrupt Enable */ + /* Bit 23: Reserved */ +#define USBHS_OTGSC_DPIS (1 << 22) /* Bit 22: Data Pulse interrupt Status */ +#define USBHS_OTGSC_MSS (1 << 21) /* Bit 21: 1 Milli-Second timer interrupt Status */ +#define USBHS_OTGSC_BSEIS (1 << 20) /* Bit 20: B Session End Interrupt Status */ +#define USBHS_OTGSC_BSVIS (1 << 19) /* Bit 19: B Session Valid Interrupt Status */ +#define USBHS_OTGSC_ASVIS (1 << 18) /* Bit 18: A Session Valid Interrupt Status */ +#define USBHS_OTGSC_AVVIS (1 << 17) /* Bit 17: A VBUS Valid Interrupt Status */ +#define USBHS_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID Interrupt Status */ + /* Bit 15: Reserved */ +#define USBHS_OTGSC_DPS (1 << 14) /* Bit 14: Data bus Pulsing Status */ +#define USBHS_OTGSC_MST (1 << 13) /* Bit 13: 1 Milli-Second timer Toggle */ +#define USBHS_OTGSC_BSE (1 << 12) /* Bit 12: B Session End */ +#define USBHS_OTGSC_BSV (1 << 11) /* Bit 11: B Session Valid */ +#define USBHS_OTGSC_ASV (1 << 10) /* Bit 10: A Session Valid */ +#define USBHS_OTGSC_AVV (1 << 9) /* Bit 9: A VBus Valid */ +#define USBHS_OTGSC_ID (1 << 8) /* Bit 8: USB ID */ +#define USBHS_OTGSC_HABA (1 << 7) /* Bit 7: Hardware Assist B-Disconnect to A-connect */ + /* Bit 6: Reserved */ +#define USBHS_OTGSC_IDPU (1 << 5) /* Bit 5: ID Pull-Up */ +#define USBHS_OTGSC_DP (1 << 4) /* Bit 4: Data Pulsing */ +#define USBHS_OTGSC_OT (1 << 3) /* Bit 3: OTG Termination */ +#define USBHS_OTGSC_HAAR (1 << 2) /* Bit 2: Hardware Assist Auto-Reset */ +#define USBHS_OTGSC_VC (1 << 1) /* Bit 1: VBUS Charge */ +#define USBHS_OTGSC_VD (1 << 0) /* Bit 0: VBUS Discharge */ /* USB Mode Register */ - /* Bits 15-31: Reserved */ -#define USBHS_USBMODE_TXHSD_SHIFT (12) /* Bits 12-14: Tx to Tx HS Delay */ -#define USBHS_USBMODE_TXHSD_MASK (0x7 << USBHS_USBMODE_TXHSD_SHIFT) - /* Bits 5-11: Reserved */ -#define USBHS_USBMODE_SDIS (1 << 4) /* Bit 4: Stream DISable */ -#define USBHS_USBMODE_SLOM (1 << 3) /* Bit 3: Setup Lock-Out Mode */ -#define USBHS_USBMODE_ES (1 << 2) /* Bit 2: Endian Select */ -#define USBHS_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller Mode */ -#define USBHS_USBMODE_CM_MASK (0x3 << USBHS_USBMODE_CM_SHIFT) -# define USBHS_USBMODE_CM_IDLE (0 << USBHS_USBMODE_CM_SHIFT) /* Idle */ -# define USBHS_USBMODE_CM_DEVICE (2 << USBHS_USBMODE_CM_SHIFT) /* Device controller */ -# define USBHS_USBMODE_CM_HOST (3 << USBHS_USBMODE_CM_SHIFT) /* Host controller */ + /* Bits 15-31: Reserved */ +#define USBHS_USBMODE_TXHSD_SHIFT (12) /* Bits 12-14: Tx to Tx HS Delay */ +#define USBHS_USBMODE_TXHSD_MASK (0x7 << USBHS_USBMODE_TXHSD_SHIFT) + /* Bits 5-11: Reserved */ +#define USBHS_USBMODE_SDIS (1 << 4) /* Bit 4: Stream DISable */ +#define USBHS_USBMODE_SLOM (1 << 3) /* Bit 3: Setup Lock-Out Mode */ +#define USBHS_USBMODE_ES (1 << 2) /* Bit 2: Endian Select */ +#define USBHS_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller Mode */ +#define USBHS_USBMODE_CM_MASK (0x3 << USBHS_USBMODE_CM_SHIFT) +# define USBHS_USBMODE_CM_IDLE (0 << USBHS_USBMODE_CM_SHIFT) /* Idle */ +# define USBHS_USBMODE_CM_DEVICE (2 << USBHS_USBMODE_CM_SHIFT) /* Device controller */ +# define USBHS_USBMODE_CM_HOST (3 << USBHS_USBMODE_CM_SHIFT) /* Host controller */ /* Endpoint Setup Status Register */ - /* Bits 4_31: Reserved */ -#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0) /* Bits 0-3: Setup Endpoint Status */ -#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xf << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT) + /* Bits 4_31: Reserved */ +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0) /* Bits 0-3: Setup Endpoint Status */ +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xf << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT) /* Endpoint Initialization Register */ - /* Bits 20-31: Reserved */ -#define USBHS_EPPRIME_PETB_SHIFT (16) /* Bits 16-19: Prime Endpoint Transmit Buffer */ -#define USBHS_EPPRIME_PETB_MASK (0xf << USBHS_EPPRIME_PETB_SHIFT) - /* Bits 4-15: Reserved */ -#define USBHS_EPPRIME_PERB_SHIFT (0) /* Bits 0-3: Prime Endpoint Receive Buffer */ -#define USBHS_EPPRIME_PERB_MASK (0xf << USBHS_EPPRIME_PERB_SHIFT) + /* Bits 20-31: Reserved */ +#define USBHS_EPPRIME_PETB_SHIFT (16) /* Bits 16-19: Prime Endpoint Transmit Buffer */ +#define USBHS_EPPRIME_PETB_MASK (0xf << USBHS_EPPRIME_PETB_SHIFT) + /* Bits 4-15: Reserved */ +#define USBHS_EPPRIME_PERB_SHIFT (0) /* Bits 0-3: Prime Endpoint Receive Buffer */ +#define USBHS_EPPRIME_PERB_MASK (0xf << USBHS_EPPRIME_PERB_SHIFT) /* Endpoint Flush Register */ - /* Bits 20-31: Reserved */ -#define USBHS_EPFLUSH_FETB_SHIFT (16) /* Bits 16-19: Flush Endpoint Transmit Buffer */ -#define USBHS_EPFLUSH_FETB_MASK (0xf << USBHS_EPFLUSH_FETB_SHIFT) - /* Bits 4-15: Reserved */ -#define USBHS_EPFLUSH_FERB_SHIFT (0) /* Bits 0-3: Flush Endpoint Receive Buffer */ -#define USBHS_EPFLUSH_FERB_MASK (0xf << USBHS_EPFLUSH_FERB_SHIFT) + /* Bits 20-31: Reserved */ +#define USBHS_EPFLUSH_FETB_SHIFT (16) /* Bits 16-19: Flush Endpoint Transmit Buffer */ +#define USBHS_EPFLUSH_FETB_MASK (0xf << USBHS_EPFLUSH_FETB_SHIFT) + /* Bits 4-15: Reserved */ +#define USBHS_EPFLUSH_FERB_SHIFT (0) /* Bits 0-3: Flush Endpoint Receive Buffer */ +#define USBHS_EPFLUSH_FERB_MASK (0xf << USBHS_EPFLUSH_FERB_SHIFT) /* Endpoint Status Register */ - /* Bits 31-20: Reserved */ -#define USBHS_EPSR_ETBR_SHIFT (16) /* Bits 16-19: Endpoint Transmit Buffer Ready */ -#define USBHS_EPSR_ETBR_MASK (0xf << USBHS_EPSR_ETBR_SHIFT) - /* Bits 5-14: Reserved */ -#define USBHS_EPSR_ERBR_SHIFT (0) /* Bits 0-3: Endpoint Receive Buffer Ready */ -#define USBHS_EPSR_ERBR_MASK (0xf << USBHS_EPSR_ERBR_SHIFT) + /* Bits 31-20: Reserved */ +#define USBHS_EPSR_ETBR_SHIFT (16) /* Bits 16-19: Endpoint Transmit Buffer Ready */ +#define USBHS_EPSR_ETBR_MASK (0xf << USBHS_EPSR_ETBR_SHIFT) + /* Bits 5-14: Reserved */ +#define USBHS_EPSR_ERBR_SHIFT (0) /* Bits 0-3: Endpoint Receive Buffer Ready */ +#define USBHS_EPSR_ERBR_MASK (0xf << USBHS_EPSR_ERBR_SHIFT) /* Endpoint Complete Register */ - /* Bits 20-31: Reserved */ -#define USBHS_EPCOMPLETE_ETCE_SHIFT (16) /* Bits 16-19: Endpoint Transmit Complete Event */ -#define USBHS_EPCOMPLETE_ETCE_MASK (0xf << USBHS_EPCOMPLETE_ETCE_SHIFT) - /* Bits 4-15: Reserved */ -#define USBHS_EPCOMPLETE_ERCE_SHIFT (0) /* Bits 0-3: Endpoint Receive Complete Event */ -#define USBHS_EPCOMPLETE_ERCE_MASK (0xf << USBHS_EPCOMPLETE_ERCE_SHIFT) + /* Bits 20-31: Reserved */ +#define USBHS_EPCOMPLETE_ETCE_SHIFT (16) /* Bits 16-19: Endpoint Transmit Complete Event */ +#define USBHS_EPCOMPLETE_ETCE_MASK (0xf << USBHS_EPCOMPLETE_ETCE_SHIFT) + /* Bits 4-15: Reserved */ +#define USBHS_EPCOMPLETE_ERCE_SHIFT (0) /* Bits 0-3: Endpoint Receive Complete Event */ +#define USBHS_EPCOMPLETE_ERCE_MASK (0xf << USBHS_EPCOMPLETE_ERCE_SHIFT) /* Endpoint Control Register 0 */ - /* Bits 24-31: Undefined */ -#define USBHS_EPCR0_TXE (1 << 23) /* Bit 23: TX Endpoint Enable */ - /* Bits 20-22: Reserved */ -#define USBHS_EPCR0_TXT_SHIFT (18) /* Bits 18-19: TX Endpoint Type */ -#define USBHS_EPCR0_TXT_MASK (0x3 << USBHS_EPCR0_TXT_SHIFT) - /* Bit 17: Reserved */ -#define USBHS_EPCR0_TXS (1 << 16) /* Bit 16: TX Endpoint Stall */ - /* Bits 8-15: Reserved */ -#define USBHS_EPCR0_RXE (1 << 7) /* Bit 7: RX endpoint Enable */ - /* Bits 4-6: Reserved */ -#define USBHS_EPCR0_RXT_SHIFT (2) /* Bits 2-3: RX endpoint Type */ -#define USBHS_EPCR0_RXT_MASK (0x3 << USBHS_EPCR0_RXT_SHIFT) - /* Bit 1: Reserved */ -#define USBHS_EPCR0_RXS (1 << 0) /* Bit 0: RX endpoint Stall */ + /* Bits 24-31: Undefined */ +#define USBHS_EPCR0_TXE (1 << 23) /* Bit 23: TX Endpoint Enable */ + /* Bits 20-22: Reserved */ +#define USBHS_EPCR0_TXT_SHIFT (18) /* Bits 18-19: TX Endpoint Type */ +#define USBHS_EPCR0_TXT_MASK (0x3 << USBHS_EPCR0_TXT_SHIFT) + /* Bit 17: Reserved */ +#define USBHS_EPCR0_TXS (1 << 16) /* Bit 16: TX Endpoint Stall */ + /* Bits 8-15: Reserved */ +#define USBHS_EPCR0_RXE (1 << 7) /* Bit 7: RX endpoint Enable */ + /* Bits 4-6: Reserved */ +#define USBHS_EPCR0_RXT_SHIFT (2) /* Bits 2-3: RX endpoint Type */ +#define USBHS_EPCR0_RXT_MASK (0x3 << USBHS_EPCR0_RXT_SHIFT) + /* Bit 1: Reserved */ +#define USBHS_EPCR0_RXS (1 << 0) /* Bit 0: RX endpoint Stall */ /* Endpoint Control Register n */ - /* Bits 24-31: Reserved */ -#define USBHS_EPCRn_TXE (1 << 23) /* Bit 23: TX endpoint Enable */ -#define USBHS_EPCRn_TXR (1 << 22) /* Bit 22: TX data toggle Reset */ -#define USBHS_EPCRn_TXI (1 << 21) /* Bit 21: TX data toggle Inhibit */ - /* Bit 20: Reserved */ -#define USBHS_EPCRn_TXT_SHIFT (18) /* Bits 18-19: TX endpoint Type */ -#define USBHS_EPCRn_TXT_MASK (0x3 << USBHS_EPCRn_TXT_SHIFT) -#define USBHS_EPCRn_TXD (1 << 17) /* Bit 17: TX endpoint Data source */ -#define USBHS_EPCRn_TXS (1 << 16) /* Bit 16: TX endpoint Stall */ - /* Bits 8-15: Reserved */ -#define USBHS_EPCRn_RXE (1 << 7) /* Bit 7: RX endpoint Enable */ -#define USBHS_EPCRn_RXR (1 << 6) /* Bit 6: RX data toggle Reset */ -#define USBHS_EPCRn_RXI (1 << 5) /* Bit 5: RX data toggle Inhibit */ - /* Bit 4: Reserved */ -#define USBHS_EPCRn_RXT_SHIFT (2) /* Bits 2-3: RX endpoint Type */ -#define USBHS_EPCRn_RXT_MASK (0x3 << USBHS_EPCRn_RXT_SHIFT) -#define USBHS_EPCRn_RXD (1 << 1) /* Bit 1: RX endpoint Data sink */ -#define USBHS_EPCRn_RXS (1 << 0) /* Bit 0: RX endpoint Stall */ + /* Bits 24-31: Reserved */ +#define USBHS_EPCRn_TXE (1 << 23) /* Bit 23: TX endpoint Enable */ +#define USBHS_EPCRn_TXR (1 << 22) /* Bit 22: TX data toggle Reset */ +#define USBHS_EPCRn_TXI (1 << 21) /* Bit 21: TX data toggle Inhibit */ + /* Bit 20: Reserved */ +#define USBHS_EPCRn_TXT_SHIFT (18) /* Bits 18-19: TX endpoint Type */ +#define USBHS_EPCRn_TXT_MASK (0x3 << USBHS_EPCRn_TXT_SHIFT) +#define USBHS_EPCRn_TXD (1 << 17) /* Bit 17: TX endpoint Data source */ +#define USBHS_EPCRn_TXS (1 << 16) /* Bit 16: TX endpoint Stall */ + /* Bits 8-15: Reserved */ +#define USBHS_EPCRn_RXE (1 << 7) /* Bit 7: RX endpoint Enable */ +#define USBHS_EPCRn_RXR (1 << 6) /* Bit 6: RX data toggle Reset */ +#define USBHS_EPCRn_RXI (1 << 5) /* Bit 5: RX data toggle Inhibit */ + /* Bit 4: Reserved */ +#define USBHS_EPCRn_RXT_SHIFT (2) /* Bits 2-3: RX endpoint Type */ +#define USBHS_EPCRn_RXT_MASK (0x3 << USBHS_EPCRn_RXT_SHIFT) +#define USBHS_EPCRn_RXD (1 << 1) /* Bit 1: RX endpoint Data sink */ +#define USBHS_EPCRn_RXS (1 << 0) /* Bit 0: RX endpoint Stall */ /* USB General Control Register */ - /* Bits 6-31: Reserved */ -#define USBHS_USBGENCTRL_WU_INT_CLR (1 << 5) /* Bit 5: Wakeup Interrupt Clear */ - /* Bits 1-4: Reserved */ -#define USBHS_USBGENCTRL_WU_IE (1 << 0) /* Bit 0: Wakeup Interrupt Enable */ + /* Bits 6-31: Reserved */ +#define USBHS_USBGENCTRL_WU_INT_CLR (1 << 5) /* Bit 5: Wakeup Interrupt Clear */ + /* Bits 1-4: Reserved */ +#define USBHS_USBGENCTRL_WU_IE (1 << 0) /* Bit 0: Wakeup Interrupt Enable */ /* USB PHY Power-Down Register */ - /* Bits 21-31: Reserved */ -#define USBPHY_PWDn_RXPWDRX (1 << 20) /* Bit 20: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ -#define USBPHY_PWDn_RXPWDDIFF (1 << 19) /* Bit 19: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ -#define USBPHY_PWDn_RXPWD1PT1 (1 << 18) /* Bit 18: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ -#define USBPHY_PWDn_RXPWDENV (1 << 17) /* Bit 17: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ - /* Bits 13-16: Reserved */ -#define USBPHY_PWDn_TXPWDV2I (1 << 12) /* Bit 12: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ -#define USBPHY_PWDn_TXPWDIBIAS (1 << 11) /* Bit 11: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ -#define USBPHY_PWDn_TXPWDFS (1 << 10) /* Bit 10: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ - /* Bits 0-9: Reserved */ + /* Bits 21-31: Reserved */ +#define USBPHY_PWDn_RXPWDRX (1 << 20) /* Bit 20: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ +#define USBPHY_PWDn_RXPWDDIFF (1 << 19) /* Bit 19: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ +#define USBPHY_PWDn_RXPWD1PT1 (1 << 18) /* Bit 18: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ +#define USBPHY_PWDn_RXPWDENV (1 << 17) /* Bit 17: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ + /* Bits 13-16: Reserved */ +#define USBPHY_PWDn_TXPWDV2I (1 << 12) /* Bit 12: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ +#define USBPHY_PWDn_TXPWDIBIAS (1 << 11) /* Bit 11: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ +#define USBPHY_PWDn_TXPWDFS (1 << 10) /* Bit 10: Auto cleared if USB wakeup while ENAUTOCLR_PHY_PWD */ + /* Bits 0-9: Reserved */ /* USB PHY Transmitter Control Register */ -#define USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT (26) /* Bits 26-28: Edge-rate of the current sensing in HS transmit */ -#define USBPHY_TXn_USBPHY_TX_EDGECTRL_MASK (0x7 << USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT) - /* Bit 20-25: Reserved */ -#define USBPHY_TXn_TXCAL45DP_SHIFT (16) /* Bits 16-19: Trim termination resistance to the USB_DP output */ -#define USBPHY_TXn_TXCAL45DP_MASK (0xf << USBPHY_TXn_TXCAL45DP_SHIFT) - /* Bits 12-15: Reserved */ -#define USBPHY_TXn_TXCAL45DM_SHIFT (8) /* Bits 8-11: Trim termination resistance to the USB_DM output */ -#define USBPHY_TXn_TXCAL45DM_MASK (0xf << USBPHY_TXn_TXCAL45DM_SHIFT) - /* Bits 4-7: Reserved */ -#define USBPHY_TXn_D_CAL_SHIFT (0) /* Bits 7-0: Trim current source for the High Speed TX drivers */ -#define USBPHY_TXn_D_CAL_MASK (0xf << USBPHY_TXn_D_CAL_SHIFT) +#define USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT (26) /* Bits 26-28: Edge-rate of the current sensing in HS transmit */ +#define USBPHY_TXn_USBPHY_TX_EDGECTRL_MASK (0x7 << USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT) + /* Bit 20-25: Reserved */ +#define USBPHY_TXn_TXCAL45DP_SHIFT (16) /* Bits 16-19: Trim termination resistance to the USB_DP output */ +#define USBPHY_TXn_TXCAL45DP_MASK (0xf << USBPHY_TXn_TXCAL45DP_SHIFT) + /* Bits 12-15: Reserved */ +#define USBPHY_TXn_TXCAL45DM_SHIFT (8) /* Bits 8-11: Trim termination resistance to the USB_DM output */ +#define USBPHY_TXn_TXCAL45DM_MASK (0xf << USBPHY_TXn_TXCAL45DM_SHIFT) + /* Bits 4-7: Reserved */ +#define USBPHY_TXn_D_CAL_SHIFT (0) /* Bits 7-0: Trim current source for the High Speed TX drivers */ +#define USBPHY_TXn_D_CAL_MASK (0xf << USBPHY_TXn_D_CAL_SHIFT) /* USB PHY Receiver Control Register */ - /* Bits 23-31: Reserved */ -#define USBPHY_RXn_RXDBYPASS (1 << 22) /* Bit 22: Test mode, replace FS differential receiver with DP single ended receiver */ - /* Bits 7-21: Reserved */ -#define USBPHY_RXn_DISCONADJ_SHIFT (4) /* Bits 4-6: Adjusts the trip point for the disconnect detector */ -#define USBPHY_RXn_DISCONADJ_MASK (0x7 << USBPHY_RXn_DISCONADJ_SHIFT) - /* Bit 3: Reserved */ -#define USBPHY_RXn_ENVADJ_SHIFT (0) /* Bits 0-3: Adjusts the trip point for the envelope detector */ -#define USBPHY_RXn_ENVADJ_MASK (0x7 << USBPHY_RXn_ENVADJ_SHIFT) + /* Bits 23-31: Reserved */ +#define USBPHY_RXn_RXDBYPASS (1 << 22) /* Bit 22: Test mode, replace FS differential receiver with DP single ended receiver */ + /* Bits 7-21: Reserved */ +#define USBPHY_RXn_DISCONADJ_SHIFT (4) /* Bits 4-6: Adjusts the trip point for the disconnect detector */ +#define USBPHY_RXn_DISCONADJ_MASK (0x7 << USBPHY_RXn_DISCONADJ_SHIFT) + /* Bit 3: Reserved */ +#define USBPHY_RXn_ENVADJ_SHIFT (0) /* Bits 0-3: Adjusts the trip point for the envelope detector */ +#define USBPHY_RXn_ENVADJ_MASK (0x7 << USBPHY_RXn_ENVADJ_SHIFT) /* USB PHY General Control Register */ -#define USBPHY_CTRLN_SFTRST (1 << 31) /* Bit 31: Soft-reset the USBPHY_PWD, USBPHY_TX, USBPHY_RX, and USBPHY_CTRL */ -#define USBPHY_CTRLN_CLKGATE (1 << 30) /* Bit 30: Gate UTMI Clocks */ -#define USBPHY_CTRLn_UTMI_SUSPENDM (1 << 29) /* Bit 29: Indicats powered-down state */ -#define USBPHY_CTRLn_HOST_FORCE_LS_SE0 (1 << 28) /* Bit 28: Forces next FS packet tohave a EOP with low-speed timing */ -#define USBPHY_CTRLn_OTG_ID_VALUE (1 << 27) /* Bit 27: Indicates the results of USB_ID pin */ - /* Bit 25-26: Reserved */ -#define USBPHY_CTRLn_FSDLL_RST_EN (1 << 24) /* Bit 24: Reset of the FSDLL lock detection logic at the end of each TX packet */ - /* Bit 21-23: Reserved */ -#define USBPHY_CTRLn_ENAUTOCLR_PHY_PWD (1 << 20) /* Bit 20: Auto-clear the PWD register bits in USBPHY_PWD if wakeup event while suspended */ -#define USBPHY_CTRLn_ENAUTOCLR_CLKGATE (1 << 19) /* Bit 19: Auto-clear the CLKGATE bit if wakeup event while suspended */ -#define USBPHY_CTRLn_AUTORESUME_EN (1 << 18) /* Bit 18: Auto resume, HW will send Resume to respond to the device remote wakeup */ - /* Bit 16-17: Reserved */ -#define USBPHY_CTRLN_ENUTMILEVEL3 (1 << 15) /* Bit 15: Enables UTMI+ Level 3 operation for the USB HS PHY */ -#define USBPHY_CTRLN_ENUTMILEVEL2 (1 << 14) /* Bit 14: Enables UTMI+ Level 2 operation for the USB HS PHY */ - /* Bit 13: Reserved */ -#define USBPHY_CTRLn_DEVPLUGIN_IRQ (1 << 12) /* Bit 12: Indicates device is connected */ - /* Bits 5-11: Reserved */ -#define USBPHY_CTRLn_ENDEVPLUGINDET (1 << 4) /* Bit 4: Enables non-standard resistive plugged-in detection */ -#define USBPHY_CTRLn_HOSTDISCONDETECT_IRQ (1 << 3) /* Bit 3: Indicates that the device has disconnected in High-Speed mode */ - /* Bit 2: Reserved */ -#define USBPHY_CTRLn_ENHOSTDISCONDETECT (1 << 1) /* Bit 1: For host mode, enables high-speed disconnect detector */ - /* Bit 0: Reserved */ +#define USBPHY_CTRLN_SFTRST (1 << 31) /* Bit 31: Soft-reset the USBPHY_PWD, USBPHY_TX, USBPHY_RX, and USBPHY_CTRL */ +#define USBPHY_CTRLN_CLKGATE (1 << 30) /* Bit 30: Gate UTMI Clocks */ +#define USBPHY_CTRLn_UTMI_SUSPENDM (1 << 29) /* Bit 29: Indicats powered-down state */ +#define USBPHY_CTRLn_HOST_FORCE_LS_SE0 (1 << 28) /* Bit 28: Forces next FS packet tohave a EOP with low-speed timing */ +#define USBPHY_CTRLn_OTG_ID_VALUE (1 << 27) /* Bit 27: Indicates the results of USB_ID pin */ + /* Bit 25-26: Reserved */ +#define USBPHY_CTRLn_FSDLL_RST_EN (1 << 24) /* Bit 24: Reset of the FSDLL lock detection logic at the end of each TX packet */ + /* Bit 21-23: Reserved */ +#define USBPHY_CTRLn_ENAUTOCLR_PHY_PWD (1 << 20) /* Bit 20: Auto-clear the PWD register bits in USBPHY_PWD if wakeup event while suspended */ +#define USBPHY_CTRLn_ENAUTOCLR_CLKGATE (1 << 19) /* Bit 19: Auto-clear the CLKGATE bit if wakeup event while suspended */ +#define USBPHY_CTRLn_AUTORESUME_EN (1 << 18) /* Bit 18: Auto resume, HW will send Resume to respond to the device remote wakeup */ + /* Bit 16-17: Reserved */ +#define USBPHY_CTRLN_ENUTMILEVEL3 (1 << 15) /* Bit 15: Enables UTMI+ Level 3 operation for the USB HS PHY */ +#define USBPHY_CTRLN_ENUTMILEVEL2 (1 << 14) /* Bit 14: Enables UTMI+ Level 2 operation for the USB HS PHY */ + /* Bit 13: Reserved */ +#define USBPHY_CTRLn_DEVPLUGIN_IRQ (1 << 12) /* Bit 12: Indicates device is connected */ + /* Bits 5-11: Reserved */ +#define USBPHY_CTRLn_ENDEVPLUGINDET (1 << 4) /* Bit 4: Enables non-standard resistive plugged-in detection */ +#define USBPHY_CTRLn_HOSTDISCONDETECT_IRQ (1 << 3) /* Bit 3: Indicates that the device has disconnected in High-Speed mode */ + /* Bit 2: Reserved */ +#define USBPHY_CTRLn_ENHOSTDISCONDETECT (1 << 1) /* Bit 1: For host mode, enables high-speed disconnect detector */ + /* Bit 0: Reserved */ /* USB PHY Status Register */ - /* Bits 11-31: Reserved */ -#define USBPHY_STATUS_RESUME_STATUS (1 << 10) /* Bit 10: Indicates that the host is sending a wake-up after Suspend */ - /* Bit 9: Reserved */ -#define USBPHY_STATUS_OTGID_STATUS (1 << 8) /* Bit 8: Indicates the results of USB_ID pin on the USB cable */ - /* Bit 7: Reserved */ -#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) /* Bit 6: Status indicator for non-standard resistive plugged-in detection */ - /* Bits 4-5: Reserved */ -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) /* Bit 3: Indicates at that the remote device has disconnected while in High-Speed mode */ - /* Bits 0-2: Reserved */ + /* Bits 11-31: Reserved */ +#define USBPHY_STATUS_RESUME_STATUS (1 << 10) /* Bit 10: Indicates that the host is sending a wake-up after Suspend */ + /* Bit 9: Reserved */ +#define USBPHY_STATUS_OTGID_STATUS (1 << 8) /* Bit 8: Indicates the results of USB_ID pin on the USB cable */ + /* Bit 7: Reserved */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) /* Bit 6: Status indicator for non-standard resistive plugged-in detection */ + /* Bits 4-5: Reserved */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) /* Bit 3: Indicates at that the remote device has disconnected while in High-Speed mode */ + /* Bits 0-2: Reserved */ /* USB PHY Debug Register */ - /* Bit 31: Reserved */ -#define USBPHY_DEBUGn_CLKGATE (1 << 30) /* Bit 30: Gate Test Clocks */ -#define USBPHY_DEBUGn_HOST_RESUME_DEBUG (1 << 29) /* Bit 29: Trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND=1 */ -#define USBPHY_DEBUGn_SQUELCHRESETLENGTH_SHIFT (25) /* Bits 25-28: Duration of RESET in terms of the number of 480-MHz cycles */ -#define USBPHY_DEBUGn_SQUELCHRESETLENGTH_MASK (0xf << USBPHY_DEBUGn_SQUELCHRESETLENGTH_SHIFT) -#define USBPHY_DEBUGn_ENSQUELCHRESET (1 << 24) /* Bit 24: Set bit to allow squelch to reset high-speed receive */ - /* Bits 21-23: Reserved */ -#define USBPHY_DEBUGn_SQUELCHRESETCOUNT_SHIFT (16) /* Bits 16-20: Delay in between the detection of squelch to the reset of high-speed RX */ -#define USBPHY_DEBUGn_SQUELCHRESETCOUNT_MASK (0x1f << USBPHY_DEBUGn_SQUELCHRESETCOUNT_SHIFT) - /* Bits 13-15: Reserved */ -#define USBPHY_DEBUGn_ENTX2RXCOUNT (1 << 12) /* Bit 12: Allow a countdown to transition in between TX and RX */ -#define USBPHY_DEBUGn_TX2RXCOUNT_SHIFT (8) /* Bits 8-11: Delay in between the end of transmit to the beginning of receive */ -#define USBPHY_DEBUGn_TX2RXCOUNT_MASK (0xf << USBPHY_DEBUGn_TX2RXCOUNT_SHIFT) - /* Bits 6-7: Reserved */ -#define USBPHY_DEBUGn_ENHSTPULLDOWN_SHIFT (4) /* Bits 4-5: Host pulldown overdrive mode */ -#define USBPHY_DEBUGn_ENHSTPULLDOWN_MASK (0x3 << USBPHY_DEBUGn_ENHSTPULLDOWN_SHIFT) -#define USBPHY_DEBUGn_HSTPULLDOWN_SHIFT (2) /* Bits 2-3: Connect pulldown resistors on USB_DP/USB_DM pins if pulldown overdrive mode enabled */ -#define USBPHY_DEBUGn_HSTPULLDOWN_MASK (0x3 << USBPHY_DEBUGn_HSTPULLDOWN_SHIFT) -#define USBPHY_DEBUGn_DEBUG_INTERFACE_HOLD (1 << 1) /* Bit 1: Use holding registers to assist in timing for external UTMI interface */ -#define USBPHY_DEBUGn_OTGIDPIOLOCK (1 << 0) /* Bit 0: Hold sampled OTG ID from USBPHY_STATUS_OTGID_STATUS */ + /* Bit 31: Reserved */ +#define USBPHY_DEBUGn_CLKGATE (1 << 30) /* Bit 30: Gate Test Clocks */ +#define USBPHY_DEBUGn_HOST_RESUME_DEBUG (1 << 29) /* Bit 29: Trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND=1 */ +#define USBPHY_DEBUGn_SQUELCHRESETLENGTH_SHIFT (25) /* Bits 25-28: Duration of RESET in terms of the number of 480-MHz cycles */ +#define USBPHY_DEBUGn_SQUELCHRESETLENGTH_MASK (0xf << USBPHY_DEBUGn_SQUELCHRESETLENGTH_SHIFT) +#define USBPHY_DEBUGn_ENSQUELCHRESET (1 << 24) /* Bit 24: Set bit to allow squelch to reset high-speed receive */ + /* Bits 21-23: Reserved */ +#define USBPHY_DEBUGn_SQUELCHRESETCOUNT_SHIFT (16) /* Bits 16-20: Delay in between the detection of squelch to the reset of high-speed RX */ +#define USBPHY_DEBUGn_SQUELCHRESETCOUNT_MASK (0x1f << USBPHY_DEBUGn_SQUELCHRESETCOUNT_SHIFT) + /* Bits 13-15: Reserved */ +#define USBPHY_DEBUGn_ENTX2RXCOUNT (1 << 12) /* Bit 12: Allow a countdown to transition in between TX and RX */ +#define USBPHY_DEBUGn_TX2RXCOUNT_SHIFT (8) /* Bits 8-11: Delay in between the end of transmit to the beginning of receive */ +#define USBPHY_DEBUGn_TX2RXCOUNT_MASK (0xf << USBPHY_DEBUGn_TX2RXCOUNT_SHIFT) + /* Bits 6-7: Reserved */ +#define USBPHY_DEBUGn_ENHSTPULLDOWN_SHIFT (4) /* Bits 4-5: Host pulldown overdrive mode */ +#define USBPHY_DEBUGn_ENHSTPULLDOWN_MASK (0x3 << USBPHY_DEBUGn_ENHSTPULLDOWN_SHIFT) +#define USBPHY_DEBUGn_HSTPULLDOWN_SHIFT (2) /* Bits 2-3: Connect pulldown resistors on USB_DP/USB_DM pins if pulldown overdrive mode enabled */ +#define USBPHY_DEBUGn_HSTPULLDOWN_MASK (0x3 << USBPHY_DEBUGn_HSTPULLDOWN_SHIFT) +#define USBPHY_DEBUGn_DEBUG_INTERFACE_HOLD (1 << 1) /* Bit 1: Use holding registers to assist in timing for external UTMI interface */ +#define USBPHY_DEBUGn_OTGIDPIOLOCK (1 << 0) /* Bit 0: Hold sampled OTG ID from USBPHY_STATUS_OTGID_STATUS */ /* UTMI Debug Status Register 0 */ @@ -839,37 +841,37 @@ /* UTMI Debug Status Register 1 */ - /* Bits 15-31: Reserved */ -#define USBPHY_DEBUG1n_ENTAILADJVD_SHIFT (13) /* Bits 14-13: Delay increment of the rise of squelch */ -#define USBPHY_DEBUG1n_ENTAILADJVD_MASK (0x3 << USBPHY_DEBUG1n_ENTAILADJVD_SHIFT) - /* Bits 0-12: Reserved */ + /* Bits 15-31: Reserved */ +#define USBPHY_DEBUG1n_ENTAILADJVD_SHIFT (13) /* Bits 14-13: Delay increment of the rise of squelch */ +#define USBPHY_DEBUG1n_ENTAILADJVD_MASK (0x3 << USBPHY_DEBUG1n_ENTAILADJVD_SHIFT) + /* Bits 0-12: Reserved */ /* UTMI RTL Version */ -#define USBPHY_VERSION_MAJOR_SHIFT (24) /* Bits 24-31: Fixed read-only value reflecting the MAJOR field of the RTL version */ -#define USBPHY_VERSION_MAJOR_MASK (0xff << USBPHY_VERSION_MAJOR_SHIFT) -#define USBPHY_VERSION_MINOR_SHIFT (16) /* Bits 16-23: Fixed read-only value reflecting the MINOR field of the RTL version */ -#define USBPHY_VERSION_MINOR_MASK (0xff << USBPHY_VERSION_MINOR_SHIFT) -#define USBPHY_VERSION_STEP_SHIFT (0) /* Bits 0-15: Fixed read-only value reflecting the stepping of the RTL version */ -#define USBPHY_VERSION_STEP_MASK (0xffff << USBPHY_VERSION_STEP_SHIFT) +#define USBPHY_VERSION_MAJOR_SHIFT (24) /* Bits 24-31: Fixed read-only value reflecting the MAJOR field of the RTL version */ +#define USBPHY_VERSION_MAJOR_MASK (0xff << USBPHY_VERSION_MAJOR_SHIFT) +#define USBPHY_VERSION_MINOR_SHIFT (16) /* Bits 16-23: Fixed read-only value reflecting the MINOR field of the RTL version */ +#define USBPHY_VERSION_MINOR_MASK (0xff << USBPHY_VERSION_MINOR_SHIFT) +#define USBPHY_VERSION_STEP_SHIFT (0) /* Bits 0-15: Fixed read-only value reflecting the stepping of the RTL version */ +#define USBPHY_VERSION_STEP_MASK (0xffff << USBPHY_VERSION_STEP_SHIFT) /* USB PHY PLL Control/Status Register */ -#define USBPHY_PLL_SICN_PLL_LOCK (1 << 31) /* Bit 31: USB PLL lock status indicator */ - /* Bits 17-30: Reserved */ -#define USBPHY_PLL_SICN_PLL_BYPASS (1 << 16) /* Bit 16: Bypass the USB PLL */ - /* Bits 14-15: Reserved */ -#define USBPHY_PLL_SICn_PLL_ENABLE (1 << 13) /* Bit 13: Enable the clock output from the USB PLL */ -#define USBPHY_PLL_SICN_PLL_POWER (1 << 12) /* Bit 12: Power up the USB PLL */ -#define USBPHY_PLL_SICn_PLL_HOLD_RING_OFF (1 << 11) /* Bit 11: Analog debug bit */ - /* Bits 7-10: Reserved */ -#define USBPHY_PLL_SICN_PLL_EN_USB_CLKS (1 << 6) /* Bit 6: Enable the USB clock output from the USB PHY PLL */ - /* Bits 2-5: Reserved */ -#define USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT (0) /* Bits 0-4: Controls the USB PLL feedback loop divider */ -#define USBPHY_PLL_SICN_PLL_DIV_SEL_MASK (0x1f << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) -# define USBPHY_PLL_SICN_PLL_DIV_SEL_24MHZ (0 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 24Mhz XTAL */ -# define USBPHY_PLL_SICN_PLL_DIV_SEL_16MHZ (1 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 16Mhz XTAL */ -# define USBPHY_PLL_SICN_PLL_DIV_SEL_12MHZ (2 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 12Mhz XTAL */ +#define USBPHY_PLL_SICN_PLL_LOCK (1 << 31) /* Bit 31: USB PLL lock status indicator */ + /* Bits 17-30: Reserved */ +#define USBPHY_PLL_SICN_PLL_BYPASS (1 << 16) /* Bit 16: Bypass the USB PLL */ + /* Bits 14-15: Reserved */ +#define USBPHY_PLL_SICn_PLL_ENABLE (1 << 13) /* Bit 13: Enable the clock output from the USB PLL */ +#define USBPHY_PLL_SICN_PLL_POWER (1 << 12) /* Bit 12: Power up the USB PLL */ +#define USBPHY_PLL_SICn_PLL_HOLD_RING_OFF (1 << 11) /* Bit 11: Analog debug bit */ + /* Bits 7-10: Reserved */ +#define USBPHY_PLL_SICN_PLL_EN_USB_CLKS (1 << 6) /* Bit 6: Enable the USB clock output from the USB PHY PLL */ + /* Bits 2-5: Reserved */ +#define USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT (0) /* Bits 0-4: Controls the USB PLL feedback loop divider */ +#define USBPHY_PLL_SICN_PLL_DIV_SEL_MASK (0x1f << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) +# define USBPHY_PLL_SICN_PLL_DIV_SEL_24MHZ (0 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 24Mhz XTAL */ +# define USBPHY_PLL_SICN_PLL_DIV_SEL_16MHZ (1 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 16Mhz XTAL */ +# define USBPHY_PLL_SICN_PLL_DIV_SEL_12MHZ (2 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 12Mhz XTAL */ /* USB PHY VBUS Detect Control Register */ @@ -894,7 +896,7 @@ /* USB PHY VBUS Detector Status Register */ - /* Bits 5-31: Reserved */ + /* Bits 5-31: Reserved */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V (1 << 4) /* Bit 4: VBUS_VALID_3V detector status */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID (1 << 3) /* Bit 3: VBUS voltage status */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID (1 << 2) /* Bit 2: A-Device Session Valid status */ @@ -903,7 +905,7 @@ /* USB PHY Charger Detect Status Register */ - /* Bits 5-31: Reserved */ + /* Bits 5-31: Reserved */ #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP (1 << 4) /* Bit 4: Battery Charging Secondary Detection phase output */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE (1 << 3) /* Bit 3: Single ended receiver output for the USB_DP pin, from charger detection circuits */ #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE (1 << 2) /* Bit 2: Single ended receiver output for the USB_DM pin, from charger detection circuits */ @@ -929,7 +931,7 @@ /* USB PHY Loopback Control/Status Register */ - /* Bits 24-31: Reserved */ + /* Bits 24-31: Reserved */ #define USBPHY_USB1_LOOPBACKn_TSTPKT_SHIFT (16) /* Bits 16-23: Selects the packet data byte used for USB loopback testing in Pulse mode */ #define USBPHY_USB1_LOOPBACKn_TSTPKT_MASK (0xff << USBPHY_USB1_LOOPBACKn_TSTPKT_SHIFT) #define USBPHY_USB1_LOOPBACKn_TSTI_HSFS_MODE_EN (1 << 15) /* Bit 15: Enable the loopback test to dynamically change the packet speed */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_usbotg.h b/arch/arm/src/kinetis/hardware/kinetis_usbotg.h index 50d462258d..04edaf2f15 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/hardware/kinetis_usbotg.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_usbotg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBOTG_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBOTG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */ #define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */ @@ -59,6 +59,7 @@ #define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */ #define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */ + #define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */ #define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */ #define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */ @@ -88,7 +89,7 @@ # define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET 0x15c /* Clock recovery sperated interrupt status */ #endif -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET) #define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET) @@ -147,9 +148,10 @@ (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET) #endif -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Peripheral ID Register (8-bit) */ + /* Bits 6-7: Reserved */ #define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */ @@ -201,6 +203,7 @@ #define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */ /* OTG Control Register (8-bit) */ + /* Bits 0-1: Reserved */ #define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */ /* Bit 3: Reserved */ @@ -222,7 +225,9 @@ #define USB_INT_ALL 0xFF -/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */ +/* Error Interrupt Status Register and + * Error Interrupt Enable Register (8-bit) + */ #define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */ #define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */ @@ -261,6 +266,7 @@ #define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT) /* BDT Page Register 1 (8-bit) */ + /* Bit 0: Reserved */ #define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */ #define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT) @@ -268,6 +274,7 @@ /* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */ #define USB_FRMNUML_MASK 0xFF /* Frame Number Register High (8-bit) */ + /* Bits 3-7: Reserved */ #define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */ #define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT) @@ -283,6 +290,7 @@ # define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */ /* SOF Threshold Register (8-bit count value) */ + /* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */ /* Endpoint n Control Register (8-bit) */ @@ -297,11 +305,13 @@ #define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */ /* USB Control Register (8-bit) */ + /* Bits 0-5: Reserved */ #define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */ #define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */ /* USB OTG Observe Register (8-bit) */ + /* Bits 0-3: Reserved */ #define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */ /* Bit 5: Reserved */ @@ -309,9 +319,11 @@ #define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */ /* USB OTG Control Register (8-bit) */ + /* Bits 0-3: Reserved */ #define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */ /* Bits 5-7: Reserved */ + /* USB Transceiver Control Register 0 (8-bit) */ #define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */ @@ -321,7 +333,8 @@ #define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */ #define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */ -/* Buffer Descriptor Table (BDT) ****************************************************/ +/* Buffer Descriptor Table (BDT) ********************************************/ + /* Offset 0: On write (software->hardware) */ #define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */ @@ -351,12 +364,12 @@ #define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */ #define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBOTG_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_vrefv1.h b/arch/arm/src/kinetis/hardware/kinetis_vrefv1.h index a59be8c4b0..fed02a38e4 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_vrefv1.h +++ b/arch/arm/src/kinetis/hardware/kinetis_vrefv1.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_vrefv1.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,40 +16,41 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_VREFV1_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_VREFV1_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_VREF_TRM_OFFSET 0x0000 /* VREF Trim Register */ #define KINETIS_VREF_SC_OFFSET 0x0001 /* VREF Status and Control Register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_VREF_TRM (KINETIS_VREF_BASE+KINETIS_VREF_TRM_OFFSET) #define KINETIS_VREF_SC (KINETIS_VREF_BASE+KINETIS_VREF_SC_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* VREF Trim Register (8-bit) */ #define VREF_TRM_SHIFT (0) /* Bits 0-5: Trim bits */ #define VREF_TRM_MASK (63 << VREF_TRM_SHIFT) /* Bits 6-7: Reserved */ + /* VREF Status and Control Register (8-bit) */ #define VREF_SC_MODE_LV_SHIFT (0) /* Bits 0-1: Buffer Mode selection */ @@ -57,21 +58,22 @@ # define VREF_SC_MODE_LV_BANDGAP (0 << VREF_SC_MODE_LV_SHIFT) /* Bandgap on only */ # define VREF_SC_MODE_LV_LOWPWR (1 << VREF_SC_MODE_LV_SHIFT) /* Low-power buffer enabled */ # define VREF_SC_MODE_LV_TIGHT (2 << VREF_SC_MODE_LV_SHIFT) /* Tight-regulation buffer enabled */ + #define VREF_SC_VREFST (1 << 2) /* Bit 2: Internal Voltage Reference stable */ /* Bits 3-5: Reserved */ #define VREF_SC_REGEN (1 << 6) /* Bit 6: Regulator enable */ #define VREF_SC_VREFEN (1 << 7) /* Bit 7: Internal Voltage Reference enable */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_VREFV1_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_wdog.h b/arch/arm/src/kinetis/hardware/kinetis_wdog.h index 90c94c0c0b..050048cfd5 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_wdog.h +++ b/arch/arm/src/kinetis/hardware/kinetis_wdog.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_wdog.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_WDOG_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_WDOG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define KINETIS_WDOG_STCTRLH_OFFSET 0x0000 /* Watchdog Status and Control Register High */ #define KINETIS_WDOG_STCTRLL_OFFSET 0x0002 /* Watchdog Status and Control Register Low */ @@ -48,7 +48,7 @@ #define KINETIS_WDOG_RSTCNT_OFFSET 0x0014 /* Watchdog Reset Count Register */ #define KINETIS_WDOG_PRESC_OFFSET 0x0016 /* Watchdog Prescaler Register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ #define KINETIS_WDOG_STCTRLH (KINETIS_WDOG_BASE+KINETIS_WDOG_STCTRLH_OFFSET) #define KINETIS_WDOG_STCTRLL (KINETIS_WDOG_BASE+KINETIS_WDOG_STCTRLL_OFFSET) @@ -63,7 +63,7 @@ #define KINETIS_WDOG_RSTCNT (KINETIS_WDOG_BASE+KINETIS_WDOG_RSTCNT_OFFSET) #define KINETIS_WDOG_PRESC (KINETIS_WDOG_BASE+KINETIS_WDOG_PRESC_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Watchdog Status and Control Register High (16-bit) */ @@ -87,36 +87,44 @@ # define WDOG_STCTRLH_BYTESEL_BYTE1 (1 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 1 selected */ # define WDOG_STCTRLH_BYTESEL_BYTE2 (2 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 2 selected */ # define WDOG_STCTRLH_BYTESEL_BYTE3 (3 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 3 selected */ + #define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG’s functional test mode */ /* Bit 15: Reserved */ + /* Watchdog Status and Control Register Low (16-bit) */ #define WDOG_STCTRLL_INTFLG (1 << 15) /* Bit 15: Interrupt flag */ /* Bits 0-14: Reserved */ /* Watchdog Time-out Value Register High/Low (16-bit timeout values) */ + /* Watchdog Window Register High/Low (16-bit window values) */ + /* Watchdog Refresh Register (16-bit, 0xa602 followed by 0xb480) */ + /* Watchdog Unlock Register (16-bit, 0xc520 followed by 0xd928) */ + /* Watchdog Timer Output Register High/Low (16-bit timer values) */ + /* Watchdog Reset Count Register (16-bit reset count) */ /* Watchdog Prescaler Register (16-bit) */ + /* Bits 0-7: Reserved */ #define WDOG_PRESC_PRESCVAL_SHIFT (8) /* Bits 8-10: Watchdog clock source prescaler */ #define WDOG_PRESC_PRESCVAL_MASK (7 << WDOG_PRESC_PRESCVAL_SHIFT) /* Bits 11-15: Reserved */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_WDOG_H */ diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index 04a3aef729..7e20767fcc 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -39,13 +39,13 @@ #include "chip.h" #include "hardware/kinetis_port.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ -/* Bit-encoded input to kinetis_pinconfig() *****************************************/ +/* Bit-encoded input to kinetis_pinconfig() *********************************/ /* General form (32-bits, only 22 bits are unused in the encoding): * @@ -66,7 +66,7 @@ /* Port Modes */ - /* Unshifted versions: */ + /* Unshifted versions: */ #define PIN_MODE_ANALOG (0) /* 000 Pin Disabled (Analog) */ #define PIN_MODE_ALT1 (1) /* 001 Alternative 1 */ #define PIN_MODE_GPIO PIN_MODE_ALT1 /* 001 Alternative 1 (GPIO) */ @@ -76,7 +76,8 @@ #define PIN_MODE_ALT5 (5) /* 101 Alternative 5 */ #define PIN_MODE_ALT6 (6) /* 110 Alternative 6 */ #define PIN_MODE_ALT7 (7) /* 111 Alternative 7 */ - /* Shifted versions: */ + + /* Shifted versions: */ #define _PIN_MODE_ANALOG (0 << _PIN_MODE_SHIFT) /* 000 Pin Disabled (Analog) */ #define _PIN_MODE_ALT1 (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 */ #define _PIN_MODE_GPIO (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 (GPIO) */ @@ -87,8 +88,8 @@ #define _PIN_MODE_ALT6 (6 << _PIN_MODE_SHIFT) /* 110 Alternative 6 */ #define _PIN_MODE_ALT7 (7 << _PIN_MODE_SHIFT) /* 111 Alternative 7 */ -/* Options for all digital modes (Alternatives 1-7). None of the digital - * options apply if the analog mode is selected. +/* Options for all digital modes (Alternatives 1-7). + * None of the digital options apply if the analog mode is selected. */ #define _PIN_IO_MASK (1 << _PIN_OPTIONS_SHIFT) /* xxx1 Digital input/output mask */ @@ -108,9 +109,11 @@ #define _PIN_OUTPUT_LOWDRIVE (1 << _PIN_OPTIONS_SHIFT) /* 0xx1 Output with low drive strength */ #define _PIN_OUTPUT_HIGHDRIVE (9 << _PIN_OPTIONS_SHIFT) /* 1xx1 Output with high drive strength */ -/* End-user pin modes and configurations. Notes: (1) None of the digital options - * are available for the analog mode, (2) digital settings may be combined (OR'ed) - * provided that input-only and output-only options are not intermixed. +/* End-user pin modes and configurations. + * Notes: + * (1) None of the digital options are available for the analog mode, + * (2) digital settings may be combined (OR'ed) provided that input-only + * and output-only options are not intermixed. */ #define PIN_ANALOG _PIN_MODE_ANALOG @@ -305,15 +308,15 @@ #define PIN30 (30 << _PIN_SHIFT) #define PIN31 (31 << _PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -324,23 +327,23 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_clockconfig * * Description: - * Called to initialize the Kinetis chip. This does whatever setup is needed to - * put the MCU in a usable state. This includes the initialization of clocking - * using the settings in board.h. + * Called to initialize the Kinetis chip. This does whatever setup is + * needed to put the MCU in a usable state. This includes the + * initialization of clocking using the settings in board.h. * - ************************************************************************************/ + ****************************************************************************/ void kinetis_clockconfig(void); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_earlyserialinit * * Description: @@ -348,13 +351,13 @@ void kinetis_clockconfig(void); * the serial console will be available during bootup. This must be called * before arm_serialinit. * - ************************************************************************************/ + ****************************************************************************/ #ifdef USE_EARLYSERIALINIT void kinetis_earlyserialinit(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_uart_earlyserialinit * * Description: @@ -362,13 +365,13 @@ void kinetis_earlyserialinit(void); * serial console will be available during bootup. This must be called * before arm_serialinit. * - ************************************************************************************/ + ****************************************************************************/ #ifdef USE_EARLYSERIALINIT void kinetis_uart_earlyserialinit(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_lpuart_earlyserialinit * * Description: @@ -376,25 +379,26 @@ void kinetis_uart_earlyserialinit(void); * serial console will be available during bootup. This must be called * before arm_serialinit. * - ************************************************************************************/ + ****************************************************************************/ #ifdef USE_EARLYSERIALINIT void kinetis_lpuart_earlyserialinit(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void kinetis_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_uart_serialinit * * Description: @@ -407,13 +411,13 @@ void kinetis_lowsetup(void); * Returned Value: * The next TTY number available for assignment * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_UART_DEVICE unsigned int kinetis_uart_serialinit(unsigned int first); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_lpuart_serialinit * * Description: @@ -426,92 +430,95 @@ unsigned int kinetis_uart_serialinit(unsigned int first); * Returned Value: * The next TTY number available for assignment * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_LPUART_DEVICE unsigned int kinetis_lpuart_serialinit(unsigned int first); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_uartreset * * Description: * Reset a UART. * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_UART_DEVICE void kinetis_uartreset(uintptr_t uart_base); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_lpuartreset * * Description: * Reset a UART. * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_LPUART_DEVICE void kinetis_lpuartreset(uintptr_t uart_base); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_uartconfigure * * Description: * Configure a UART as a RS-232 UART. * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_UART_DEVICE -void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, +void kinetis_uartconfigure(uintptr_t uart_base, + uint32_t baud, uint32_t clock, unsigned int parity, unsigned int nbits, unsigned int stop2, bool iflow, bool oflow); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_lpuartconfigure * * Description: * Configure a UART as a RS-232 UART. * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_LPUART_DEVICE -void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, - unsigned int parity, unsigned int nbits, - unsigned int stop2, - bool iflow, bool oflow); +void kinetis_lpuartconfigure(uintptr_t uart_base, + uint32_t baud, uint32_t clock, + unsigned int parity, unsigned int nbits, + unsigned int stop2, + bool iflow, bool oflow); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_wddisable * * Description: * Disable the watchdog timer * - ************************************************************************************/ + ****************************************************************************/ void kinetis_wddisable(void); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinconfig * * Description: * Configure a pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int kinetis_pinconfig(uint32_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinfilter * * Description: * Configure the digital filter associated with a port. The digital filter - * capabilities of the PORT module are available in all digital pin muxing modes. + * capabilities of the PORT module are available in all digital pin muxing + * modes. * * Input Parameters: * port - See KINETIS_PORTn definitions in kinetis_port.h @@ -519,37 +526,38 @@ int kinetis_pinconfig(uint32_t cfgset); * false: Digital Filters are clocked by the 1 kHz LPO clock * width - Filter Length * - ************************************************************************************/ + ****************************************************************************/ int kinetis_pinfilter(unsigned int port, bool lpo, unsigned int width); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void kinetis_gpiowrite(uint32_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool kinetis_gpioread(uint32_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_GPIOIRQ void kinetis_pinirqinitialize(void); @@ -557,37 +565,39 @@ void kinetis_pinirqinitialize(void); # define kinetis_pinirqinitialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinirqattach * * Description: * Attach a pin interrupt handler. The normal initialization sequence is: * - * 1. Call kinetis_pinconfig() to configure the interrupting pin (pin interrupts - * will be disabled. - * 2. Call kinetis_pinirqattach() to attach the pin interrupt handling function. + * 1. Call kinetis_pinconfig() to configure the interrupting pin (pin + * interrupts will be disabled. + * 2. Call kinetis_pinirqattach() to attach the pin interrupt handling + * function. * 3. Call kinetis_pinirqenable() to enable interrupts on the pin. * * Input Parameters: * pinset - Pin configuration * pinisr - Pin interrupt service routine - * arg - An argument that will be provided to the interrupt service routine. + * arg - An argument that will be provided to the interrupt service + * routine. * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on any - * failure to indicate the nature of the failure. + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure to indicate the nature of the failure. * - ************************************************************************************/ + ****************************************************************************/ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinirqenable * * Description: * Enable the interrupt for specified pin IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_GPIOIRQ void kinetis_pinirqenable(uint32_t pinset); @@ -595,13 +605,13 @@ void kinetis_pinirqenable(uint32_t pinset); # define kinetis_pinirqenable(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinirqdisable * * Description: * Disable the interrupt for specified pin * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_GPIOIRQ void kinetis_pinirqdisable(uint32_t pinset); @@ -609,37 +619,38 @@ void kinetis_pinirqdisable(uint32_t pinset); # define kinetis_pinirqdisable(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pindmaenable * * Description: * Enable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_DMA void kinetis_pindmaenable(uint32_t pinset); #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pindmadisable * * Description: * Disable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_DMA void kinetis_pindmadisable(uint32_t pinset); #endif -/************************************************************************************ +/**************************************************************************** * Function: kinetis_pindump * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the + * provided pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO void kinetis_pindump(uint32_t pinset, const char *msg); @@ -647,18 +658,18 @@ void kinetis_pindump(uint32_t pinset, const char *msg); # define kinetis_pindump(p,m) #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_clrpend * * Description: - * Clear a pending interrupt at the NVIC. This does not seem to be required - * for most interrupts. + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. * - ************************************************************************************/ + ****************************************************************************/ void kinetis_clrpend(int irq); -/************************************************************************************ +/**************************************************************************** * Name: sdhc_initialize * * Description: @@ -668,16 +679,17 @@ void kinetis_clrpend(int irq); * slotno - Not used. * * Returned Value: - * A reference to an SDIO interface structure. NULL is returned on failures. + * A reference to an SDIO interface structure. + * NULL is returned on failures. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_SDHC struct sdio_dev_s; FAR struct sdio_dev_s *sdhc_initialize(int slotno); #endif -/************************************************************************************ +/**************************************************************************** * Name: sdhc_mediachange * * Description: @@ -694,13 +706,13 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno); * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_SDHC void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot); #endif -/************************************************************************************ +/**************************************************************************** * Name: sdio_wrprotect * * Description: @@ -714,7 +726,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot); * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_SDHC void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect); @@ -724,7 +736,7 @@ void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect); } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_netinitialize * * Description: @@ -739,13 +751,13 @@ void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_ENET int kinetis_netinitialize(int intf); #endif -/************************************************************************************ +/**************************************************************************** * Function: kinetis_caninitialize * * Description: @@ -760,7 +772,7 @@ int kinetis_netinitialize(int intf); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_FLEXCAN int kinetis_caninitialize(int intf); #endif diff --git a/arch/arm/src/kinetis/kinetis_alarm.h b/arch/arm/src/kinetis/kinetis_alarm.h index b1ec7d8f51..1a3ae797c7 100644 --- a/arch/arm/src/kinetis/kinetis_alarm.h +++ b/arch/arm/src/kinetis/kinetis_alarm.h @@ -85,7 +85,7 @@ struct alm_setalarm_s }; /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #undef EXTERN @@ -114,7 +114,7 @@ extern "C" int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); -/************************************************************************************ +/**************************************************************************** * Name: kinetis_rtc_rdalarm * * Description: @@ -126,7 +126,7 @@ int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int kinetis_rtc_rdalarm(FAR struct timespec *tp); diff --git a/arch/arm/src/kinetis/kinetis_allocateheap.c b/arch/arm/src/kinetis/kinetis_allocateheap.c index 67d0ff31dd..e1d819d70d 100644 --- a/arch/arm/src/kinetis/kinetis_allocateheap.c +++ b/arch/arm/src/kinetis/kinetis_allocateheap.c @@ -80,7 +80,8 @@ * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE). * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -97,7 +98,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; @@ -122,7 +124,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - kinetis_mpu_uheap((uintptr_t)ubase, usize); + kinetis_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -151,7 +153,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; diff --git a/arch/arm/src/kinetis/kinetis_cfmconfig.c b/arch/arm/src/kinetis/kinetis_cfmconfig.c index 0c38ccd458..0bac66e5da 100644 --- a/arch/arm/src/kinetis/kinetis_cfmconfig.c +++ b/arch/arm/src/kinetis/kinetis_cfmconfig.c @@ -7,27 +7,28 @@ * Copyright (c) 2012-2013 Andrew Payne * * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * ****************************************************************************/ /**************************************************************************** - * Included files + * Included Files ****************************************************************************/ #include @@ -42,3 +43,7 @@ const uint8_t __flashconfigbytes[16] = 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_clrpend.c b/arch/arm/src/kinetis/kinetis_clrpend.c index abcdccaca4..7342dcfa4a 100644 --- a/arch/arm/src/kinetis/kinetis_clrpend.c +++ b/arch/arm/src/kinetis/kinetis_clrpend.c @@ -54,8 +54,8 @@ * Name: kinetis_clrpend * * Description: - * Clear a pending interrupt at the NVIC. This does not seem to be required - * for most interrupts. Don't know why... + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. Don't know why... * * I keep it in a separate file so that it will not increase the footprint * on Kinetis platforms that do not need this function. @@ -68,21 +68,25 @@ void kinetis_clrpend(int irq) if (irq >= KINETIS_IRQ_FIRST) { - if (irq < (KINETIS_IRQ_FIRST+32)) + if (irq < (KINETIS_IRQ_FIRST + 32)) { - putreg32(1 << (irq - KINETIS_IRQ_FIRST), NVIC_IRQ0_31_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST), + NVIC_IRQ0_31_CLRPEND); } - else if (irq < (KINETIS_IRQ_FIRST+64)) + else if (irq < (KINETIS_IRQ_FIRST + 64)) { - putreg32(1 << (irq - KINETIS_IRQ_FIRST - 32), NVIC_IRQ32_63_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST - 32), + NVIC_IRQ32_63_CLRPEND); } - else if (irq < (KINETIS_IRQ_FIRST+96)) + else if (irq < (KINETIS_IRQ_FIRST + 96)) { - putreg32(1 << (irq - KINETIS_IRQ_FIRST - 64), NVIC_IRQ64_95_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST - 64), + NVIC_IRQ64_95_CLRPEND); } else if (irq < NR_IRQS) { - putreg32(1 << (irq - KINETIS_IRQ_FIRST - 96), NVIC_IRQ96_127_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST - 96), + NVIC_IRQ96_127_CLRPEND); } } } diff --git a/arch/arm/src/kinetis/kinetis_dma.c b/arch/arm/src/kinetis/kinetis_dma.c index d33a97d881..13aec599f7 100644 --- a/arch/arm/src/kinetis/kinetis_dma.c +++ b/arch/arm/src/kinetis/kinetis_dma.c @@ -73,16 +73,16 @@ * Private Types ****************************************************************************/ - struct kinetis_dma_ch - { - bool used; - uint8_t ind; - uint8_t irq; - enum kinetis_dma_direction_e dir; - enum kinetis_dma_data_sz_e data_sz; - dma_callback_t callback; - void *arg; - }; +struct kinetis_dma_ch +{ + bool used; + uint8_t ind; + uint8_t irq; + enum kinetis_dma_direction_e dir; + enum kinetis_dma_data_sz_e data_sz; + dma_callback_t callback; + void *arg; +}; /**************************************************************************** * Private Data @@ -145,8 +145,8 @@ size_t kinetis_dmaresidual(DMA_HANDLE handle) /* Channel Linking Disabled */ - return ((getreg16(KINETIS_DMA_TCD_CITER(ch->ind)) >> DMA_TCD_CITER2_SHIFT) & - DMA_TCD_CITER2_MASK); + return ((getreg16(KINETIS_DMA_TCD_CITER(ch->ind)) >> + DMA_TCD_CITER2_SHIFT) & DMA_TCD_CITER2_MASK); } /**************************************************************************** @@ -207,7 +207,7 @@ void weak_function arm_dma_initialize(void) regval |= DMA_CR_ERCA | DMA_CR_ERGA; putreg32(regval, KINETIS_DMA_CR); - /* Enable clocking for the DMA mux*/ + /* Enable clocking for the DMA mux */ regval = getreg32(KINETIS_SIM_SCGC6); regval |= SIM_SCGC6_DMAMUX0; @@ -314,8 +314,8 @@ DMA_HANDLE kinetis_dmachannel(uint8_t src, uint32_t per_addr, * * Description: * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until kinetis_dmachannel() is called again to re-gain - * a valid handle. + * NEVER be used again until kinetis_dmachannel() is called again to + * re-gain a valid handle. * * Returned Value: * None diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/kinetis_dma.h index 68aae63525..f352080b5c 100644 --- a/arch/arm/src/kinetis/kinetis_dma.h +++ b/arch/arm/src/kinetis/kinetis_dma.h @@ -118,7 +118,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c index fe3806d3b6..8a8c611dbf 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.c +++ b/arch/arm/src/kinetis/kinetis_i2c.c @@ -1,4 +1,5 @@ /**************************************************************************** + * arch/arm/src/kinetis/kinetis_i2c.c * * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Authors: Matias v01d diff --git a/arch/arm/src/kinetis/kinetis_mpuinit.h b/arch/arm/src/kinetis/kinetis_mpuinit.h index 0c58936813..8cb6aab133 100644 --- a/arch/arm/src/kinetis/kinetis_mpuinit.h +++ b/arch/arm/src/kinetis/kinetis_mpuinit.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_mpuinit.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MPUINIT_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_MPUINIT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: kinetis_mpuinitialize diff --git a/arch/arm/src/kinetis/kinetis_pin.c b/arch/arm/src/kinetis/kinetis_pin.c index acfd041f12..d06ac47ea4 100644 --- a/arch/arm/src/kinetis/kinetis_pin.c +++ b/arch/arm/src/kinetis/kinetis_pin.c @@ -93,6 +93,7 @@ int kinetis_pinconfig(uint32_t cfgset) if ((cfgset & _PIN_IO_MASK) == _PIN_INPUT) { /* Handle input-only digital options */ + /* Check for pull-up or pull-down */ if ((cfgset & _PIN_INPUT_PULLMASK) == _PIN_INPUT_PULLDOWN) @@ -107,6 +108,7 @@ int kinetis_pinconfig(uint32_t cfgset) else { /* Handle output-only digital options */ + /* Check for slow slew rate setting */ if ((cfgset & _PIN_OUTPUT_SLEW_MASK) == _PIN_OUTPUT_SLOW) @@ -155,9 +157,12 @@ int kinetis_pinconfig(uint32_t cfgset) { regval &= ~(1 << pin); } + putreg32(regval, base + KINETIS_PORT_DFER_OFFSET); - /* Additional configuration for the case of Alternative 1 (GPIO) modes */ + /* Additional configuration for the case of Alternative 1 (GPIO) + * modes + */ if (mode == PIN_MODE_GPIO) { @@ -181,7 +186,8 @@ int kinetis_pinconfig(uint32_t cfgset) /* Set the initial value of the GPIO output */ - kinetis_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_ONE) != 0)); + kinetis_gpiowrite(cfgset, + ((cfgset & GPIO_OUTPUT_ONE) != 0)); } } } @@ -192,12 +198,13 @@ int kinetis_pinconfig(uint32_t cfgset) return -EINVAL; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinfilter * * Description: * Configure the digital filter associated with a port. The digital filter - * capabilities of the PORT module are available in all digital pin muxing modes. + * capabilities of the PORT module are available in all digital pin muxing + * modes. * * Input Parameters: * port - Port number. See KINETIS_PORTn definitions in kinetis_port.h @@ -205,7 +212,7 @@ int kinetis_pinconfig(uint32_t cfgset) * false: Digital Filters are clocked by the 1 kHz LPO clock * width - Filter Length * - ************************************************************************************/ + ****************************************************************************/ int kinetis_pinfilter(unsigned int port, bool lpo, unsigned int width) { @@ -230,5 +237,6 @@ int kinetis_pinfilter(unsigned int port, bool lpo, unsigned int width) putreg32(width, base + KINETIS_PORT_DFWR_OFFSET); return OK; } + return -EINVAL; } diff --git a/arch/arm/src/kinetis/kinetis_pindma.c b/arch/arm/src/kinetis/kinetis_pindma.c index 7ca112d4a1..e308ef8818 100644 --- a/arch/arm/src/kinetis/kinetis_pindma.c +++ b/arch/arm/src/kinetis/kinetis_pindma.c @@ -58,13 +58,13 @@ * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pindmaenable * * Description: * Enable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ void kinetis_pindmaenable(uint32_t pinset) { @@ -85,7 +85,9 @@ void kinetis_pindmaenable(uint32_t pinset) base = KINETIS_PORT_BASE(port); - /* Modify the IRQC field of the port PCR register in order to enable DMA. */ + /* Modify the IRQC field of the port PCR register in order to + * enable DMA. + */ regval = getreg32(base + KINETIS_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; @@ -112,13 +114,13 @@ void kinetis_pindmaenable(uint32_t pinset) } } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pindmadisable * * Description: * Disable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ void kinetis_pindmadisable(uint32_t pinset) { @@ -139,7 +141,9 @@ void kinetis_pindmadisable(uint32_t pinset) base = KINETIS_PORT_BASE(port); - /* Clear the IRQC field of the port PCR register in order to disable DMA. */ + /* Clear the IRQC field of the port PCR register in order to disable + * DMA. + */ regval = getreg32(base + KINETIS_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; diff --git a/arch/arm/src/kinetis/kinetis_pingpio.c b/arch/arm/src/kinetis/kinetis_pingpio.c index aec3fa7dd2..e5ca8d23cb 100644 --- a/arch/arm/src/kinetis/kinetis_pingpio.c +++ b/arch/arm/src/kinetis/kinetis_pingpio.c @@ -118,5 +118,6 @@ bool kinetis_gpioread(uint32_t pinset) regval = getreg32(base + KINETIS_GPIO_PDIR_OFFSET); ret = ((regval & (1 << pin)) != 0); } + return ret; } diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c index 8289daa67b..ebb25d64a3 100644 --- a/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/arch/arm/src/kinetis/kinetis_pinirq.c @@ -43,10 +43,13 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ -/* The Kinetis port interrupt logic is very flexible and will program interrupts on - * most all pin events. In order to keep the memory usage to a minimum, the NuttX - * port supports enabling interrupts on a per-port basis. + +/* The Kinetis port interrupt logic is very flexible and will program + * interrupts on most all pin events. In order to keep the memory usage to + * a minimum, the NuttX port supports enabling interrupts on a per-port + * basis. */ #if defined (CONFIG_KINETIS_PORTAINTS) || defined (CONFIG_KINETIS_PORTBINTS) || \ @@ -61,13 +64,14 @@ struct kinetis_pinirq_s { - xcpt_t handler; - void *arg; + xcpt_t handler; + void *arg; }; /**************************************************************************** * Private Data ****************************************************************************/ + /* Per pin port interrupt vectors. NOTE: Not all pins in each port * correspond to externally available GPIOs. However, I believe that the * Kinesis will support interrupts even if the pin is not available as @@ -105,7 +109,8 @@ static struct kinetis_pinirq_s g_porteisrs[32]; #ifdef HAVE_PORTINTS static int kinetis_portinterrupt(int irq, FAR void *context, - uintptr_t addr, struct kinetis_pinirq_s *isrtab) + uintptr_t addr, + struct kinetis_pinirq_s *isrtab) { uint32_t isfr = getreg32(addr); int i; @@ -166,31 +171,40 @@ static int kinetis_portinterrupt(int irq, FAR void *context, #ifdef CONFIG_KINETIS_PORTAINTS static int kinetis_portainterrupt(int irq, FAR void *context, FAR void *arg) { - return kinetis_portinterrupt(irq, context, KINETIS_PORTA_ISFR, g_portaisrs); + return kinetis_portinterrupt(irq, context, + KINETIS_PORTA_ISFR, g_portaisrs); } #endif + #ifdef CONFIG_KINETIS_PORTBINTS static int kinetis_portbinterrupt(int irq, FAR void *context, FAR void *arg) { - return kinetis_portinterrupt(irq, context, KINETIS_PORTB_ISFR, g_portbisrs); + return kinetis_portinterrupt(irq, context, + KINETIS_PORTB_ISFR, g_portbisrs); } #endif + #ifdef CONFIG_KINETIS_PORTCINTS static int kinetis_portcinterrupt(int irq, FAR void *context, FAR void *arg) { - return kinetis_portinterrupt(irq, context, KINETIS_PORTC_ISFR, g_portcisrs); + return kinetis_portinterrupt(irq, context, + KINETIS_PORTC_ISFR, g_portcisrs); } #endif + #ifdef CONFIG_KINETIS_PORTDINTS static int kinetis_portdinterrupt(int irq, FAR void *context, FAR void *arg) { - return kinetis_portinterrupt(irq, context, KINETIS_PORTD_ISFR, g_portdisrs); + return kinetis_portinterrupt(irq, context, + KINETIS_PORTD_ISFR, g_portdisrs); } #endif + #ifdef CONFIG_KINETIS_PORTEINTS static int kinetis_porteinterrupt(int irq, FAR void *context, FAR void *arg) { - return kinetis_portinterrupt(irq, context, KINETIS_PORTE_ISFR, g_porteisrs); + return kinetis_portinterrupt(irq, context, + KINETIS_PORTE_ISFR, g_porteisrs); } #endif @@ -242,21 +256,23 @@ void kinetis_pinirqinitialize(void) * Description: * Attach a pin interrupt handler. The normal initialization sequence is: * - * 1. Call kinetis_pinconfig() to configure the interrupting pin (pin interrupts - * will be disabled. - * 2. Call kinetis_pinirqattach() to attach the pin interrupt handling function. + * 1. Call kinetis_pinconfig() to configure the interrupting pin (pin + * interrupts will be disabled. + * 2. Call kinetis_pinirqattach() to attach the pin interrupt handling + * function. * 3. Call kinetis_pinirqenable() to enable interrupts on the pin. * * Input Parameters: * pinset - Pin configuration * pinisr - Pin interrupt service routine - * arg - An argument that will be provided to the interrupt service routine. + * arg - An argument that will be provided to the interrupt service + * routine. * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on any - * failure to indicate the nature of the failure. + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. * - ************************************************************************************/ + ****************************************************************************/ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) { @@ -266,8 +282,8 @@ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) unsigned int port; unsigned int pin; - /* It only makes sense to call this function for input pins that are configured - * as interrupts. + /* It only makes sense to call this function for input pins that are + * configured as interrupts. */ DEBUGASSERT((pinset & _PIN_INTDMA_MASK) == _PIN_INTERRUPT); @@ -314,27 +330,27 @@ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg) return -EINVAL; } - /* Get the old PIN ISR and set the new PIN ISR */ + /* Get the old PIN ISR and set the new PIN ISR */ - isrtab[pin].handler = pinisr; - isrtab[pin].arg = arg; + isrtab[pin].handler = pinisr; + isrtab[pin].arg = arg; - /* And return the old PIN isr address */ + /* And return the old PIN isr address */ - leave_critical_section(flags); - return OK; + leave_critical_section(flags); + return OK; #else - return -ENOSYS; + return -ENOSYS; #endif /* HAVE_PORTINTS */ } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinirqenable * * Description: * Enable the interrupt for specified pin IRQ * - ************************************************************************************/ + ****************************************************************************/ void kinetis_pinirqenable(uint32_t pinset) { @@ -406,13 +422,13 @@ void kinetis_pinirqenable(uint32_t pinset) #endif /* HAVE_PORTINTS */ } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pinirqdisable * * Description: * Disable the interrupt for specified pin * - ************************************************************************************/ + ****************************************************************************/ void kinetis_pinirqdisable(uint32_t pinset) { diff --git a/arch/arm/src/kinetis/kinetis_pwm.h b/arch/arm/src/kinetis/kinetis_pwm.h index 140fbf0f6e..67c7cb1bfc 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.h +++ b/arch/arm/src/kinetis/kinetis_pwm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_pwm.h * * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. @@ -34,28 +34,30 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PWM_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_PWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ -/* Configuration ********************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to generate modulated outputs for such things as motor control. If CONFIG_KINETIS_FTMn - * is defined then the CONFIG_KINETIS_FTMn_PWM must also be defined to indicate that - * timer "n" is intended to be used for pulsed output signal generation. + * to generate modulated outputs for such things as motor control. + * If CONFIG_KINETIS_FTMn is defined then the CONFIG_KINETIS_FTMn_PWM must + * also be defined to indicate that timer "n" is intended to be used for + * pulsed output signal generation. */ #ifndef CONFIG_KINETIS_FTM0 @@ -79,13 +81,13 @@ #include #include "hardware/kinetis_pinmux.h" -/* For each timer that is enabled for PWM usage, we need the following additional - * configuration settings: +/* For each timer that is enabled for PWM usage, we need the following + * additional configuration settings: * * CONFIG_KINETIS_FTMx_CHANNEL - Specifies the timer output channel {1,..,4} - * PWM_FTMx_CHn - One of the values defined in kinetis*_pinmap.h. In the case - * where there are multiple pin selections, the correct setting must be provided - * in the arch/board/board.h file. + * PWM_FTMx_CHn - One of the values defined in kinetis*_pinmap.h. In the + * case where there are multiple pin selections, the correct setting must + * be provided in the arch/board/board.h file. */ #ifdef CONFIG_KINETIS_FTM0_PWM @@ -176,13 +178,13 @@ # endif #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -195,11 +197,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_pwminitialize * * Description: @@ -212,7 +214,7 @@ extern "C" * On success, a pointer to the kinetis lower half PWM driver is returned. * NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer); diff --git a/arch/arm/src/kinetis/kinetis_rtc_if.h b/arch/arm/src/kinetis/kinetis_rtc_if.h index 78dd7774f2..be1b35c7d8 100644 --- a/arch/arm/src/kinetis/kinetis_rtc_if.h +++ b/arch/arm/src/kinetis/kinetis_rtc_if.h @@ -54,7 +54,7 @@ #include "kinetis_alarm.h" /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -69,7 +69,7 @@ extern "C" #endif /**************************************************************************** - * Name: KINETIS_rtc_getdatetime_with_subseconds + * Name: kinetis_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -91,7 +91,8 @@ extern "C" ****************************************************************************/ #ifdef CONFIG_KINETIS_HAVE_RTC_SUBSECONDS -int KINETIS_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec); +int kinetis_rtc_getdatetime_with_subseconds(FAR struct tm *tp, + FAR long *nsec); #endif /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c index cceb4c8a7d..7dcc52a253 100644 --- a/arch/arm/src/kinetis/kinetis_spi.c +++ b/arch/arm/src/kinetis/kinetis_spi.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_spi.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,9 +16,9 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * The external functions, kinetis_spi0/1/2select and kinetis_spi0/1/26status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by structure @@ -35,16 +35,16 @@ * configured. * 3. Add a calls to kinetis_spibus_initialize() in your low level * application initialization logic. - * 4. The handle returned by kinetis_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling + * 4. The handle returned by kinetis_spibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -75,16 +75,16 @@ #if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI1) || \ defined(CONFIG_KINETIS_SPI2) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define KINETIS_SPI_CLK_MAX (BOARD_BUS_FREQ / 2) #define KINETIS_SPI_CLK_INIT 400000 -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ struct kinetis_spidev_s { @@ -98,9 +98,9 @@ struct kinetis_spidev_s uint8_t ctarsel; /* Which CTAR */ }; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /* Helpers */ @@ -120,7 +120,8 @@ static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv); static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, uint16_t word); -static inline void spi_run(FAR struct kinetis_spidev_s *priv, bool enable); +static inline void spi_run(FAR struct kinetis_spidev_s *priv, + bool enable); static inline void spi_write_control(FAR struct kinetis_spidev_s *priv, uint32_t control); static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, @@ -149,13 +150,14 @@ static void spi_exchange(FAR struct spi_dev_s *dev, #ifndef CONFIG_SPI_EXCHANGE static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, size_t nwords); -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, +static void spi_recvblock(FAR struct spi_dev_s *dev, + FAR void *rxbuffer, size_t nwords); #endif -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_SPI0 static const struct spi_ops_s g_spi0ops = @@ -277,11 +279,11 @@ static struct kinetis_spidev_s g_spi2dev = }; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: spi_getreg * * Description: @@ -294,14 +296,15 @@ static struct kinetis_spidev_s g_spi2dev = * Returned Value: * The contents of the 32-bit register * - ************************************************************************************/ + ****************************************************************************/ -static inline uint32_t spi_getreg(FAR struct kinetis_spidev_s *priv, uint8_t offset) +static inline uint32_t spi_getreg(FAR struct kinetis_spidev_s *priv, + uint8_t offset) { return getreg32(priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: spi_putreg * * Description: @@ -315,15 +318,16 @@ static inline uint32_t spi_getreg(FAR struct kinetis_spidev_s *priv, uint8_t off * Returned Value: * Nothing * - ************************************************************************************/ + ****************************************************************************/ -static inline void spi_putreg(FAR struct kinetis_spidev_s *priv, uint8_t offset, +static inline void spi_putreg(FAR struct kinetis_spidev_s *priv, + uint8_t offset, uint32_t value) { putreg32(value, priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: spi_getreg16 * * Description: @@ -336,7 +340,7 @@ static inline void spi_putreg(FAR struct kinetis_spidev_s *priv, uint8_t offset, * Returned Value: * The contents of the 16-bit register * - ************************************************************************************/ + ****************************************************************************/ static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, uint8_t offset) @@ -344,7 +348,7 @@ static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, return getreg16(priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: spi_putreg16 * * Description: @@ -358,15 +362,16 @@ static inline uint16_t spi_getreg16(FAR struct kinetis_spidev_s *priv, * Returned Value: * Nothing * - ************************************************************************************/ + ****************************************************************************/ -static inline void spi_putreg16(FAR struct kinetis_spidev_s *priv, uint8_t offset, - uint16_t value) +static inline void spi_putreg16(FAR struct kinetis_spidev_s *priv, + uint8_t offset, + uint16_t value) { putreg16(value, priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: spi_getreg8 * * Description: @@ -379,14 +384,15 @@ static inline void spi_putreg16(FAR struct kinetis_spidev_s *priv, uint8_t offse * Returned Value: * The contents of the 8-bit register * - ************************************************************************************/ + ****************************************************************************/ -static inline uint8_t spi_getreg8(FAR struct kinetis_spidev_s *priv, uint8_t offset) +static inline uint8_t spi_getreg8(FAR struct kinetis_spidev_s *priv, + uint8_t offset) { return getreg8(priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: spi_putreg8 * * Description: @@ -400,15 +406,16 @@ static inline uint8_t spi_getreg8(FAR struct kinetis_spidev_s *priv, uint8_t off * Returned Value: * Nothing * - ************************************************************************************/ + ****************************************************************************/ -static inline void spi_putreg8(FAR struct kinetis_spidev_s *priv, uint8_t offset, - uint8_t value) +static inline void spi_putreg8(FAR struct kinetis_spidev_s *priv, + uint8_t offset, + uint8_t value) { putreg8(value, priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: spi_write_status * * Description: @@ -421,7 +428,7 @@ static inline void spi_putreg8(FAR struct kinetis_spidev_s *priv, uint8_t offset * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, uint32_t status) @@ -431,7 +438,7 @@ static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, spi_putreg(priv, KINETIS_SPI_SR_OFFSET, status); } -/************************************************************************************ +/**************************************************************************** * Name: spi_wait_status * * Description: @@ -444,7 +451,7 @@ static inline void spi_write_status(FAR struct kinetis_spidev_s *priv, * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, uint32_t status) @@ -452,7 +459,7 @@ static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, while (status != (spi_getreg(priv, KINETIS_SPI_SR_OFFSET) & status)); } -/************************************************************************************ +/**************************************************************************** * Name: spi_write_control * * Description: @@ -465,17 +472,18 @@ static inline void spi_wait_status(FAR struct kinetis_spidev_s *priv, * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void spi_write_control(FAR struct kinetis_spidev_s *priv, uint32_t control) { /* Write the control word to the SPI Data Register */ - spi_putreg16(priv, KINETIS_SPI_PUSHR_OFFSET + 2, (uint16_t) (control >> 16)); + spi_putreg16(priv, KINETIS_SPI_PUSHR_OFFSET + 2, + (uint16_t) (control >> 16)); } -/************************************************************************************ +/**************************************************************************** * Name: spi_writeword * * Description: @@ -488,9 +496,10 @@ static inline void spi_write_control(FAR struct kinetis_spidev_s *priv, * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, uint16_t word) +static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, + uint16_t word) { /* Wait until there is space in the fifo */ @@ -501,7 +510,7 @@ static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, uint16_t wor spi_putreg16(priv, KINETIS_SPI_PUSHR_OFFSET, SPI_PUSHR_TXDATA(word)); } -/************************************************************************************ +/**************************************************************************** * Name: spi_readword * * Description: @@ -513,7 +522,7 @@ static inline void spi_writeword(FAR struct kinetis_spidev_s *priv, uint16_t wor * Returned Value: * The 8-bit value from the FIFO * - ************************************************************************************/ + ****************************************************************************/ static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv) { @@ -526,7 +535,7 @@ static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv) return spi_getreg16(priv, KINETIS_SPI_POPR_OFFSET); } -/************************************************************************************ +/**************************************************************************** * Name: spi_run * * Description: @@ -539,7 +548,7 @@ static inline uint16_t spi_readword(FAR struct kinetis_spidev_s *priv) * Returned Value: * Last enable setting * - ************************************************************************************/ + ****************************************************************************/ void inline spi_run(FAR struct kinetis_spidev_s *priv, bool enable) { @@ -551,7 +560,7 @@ void inline spi_run(FAR struct kinetis_spidev_s *priv, bool enable) spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, regval); } -/************************************************************************************ +/**************************************************************************** * Name: spi_lock * * Description: @@ -570,7 +579,7 @@ void inline spi_run(FAR struct kinetis_spidev_s *priv, bool enable) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) { @@ -589,7 +598,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: spi_setfrequency * * Description: @@ -602,9 +611,10 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) * Returned Value: * Returns the actual frequency selected * - ************************************************************************************/ + ****************************************************************************/ -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency) { FAR struct kinetis_spidev_s *priv = (FAR struct kinetis_spidev_s *)dev; @@ -633,7 +643,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) frequency = KINETIS_SPI_CLK_INIT; } - /* Check if the requested frequency is the same as the frequency selection */ + /* Check if the requested frequency is the same as the frequency + * selection + */ if (priv->frequency == frequency) { @@ -703,7 +715,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) return priv->actual; } -/************************************************************************************ +/**************************************************************************** * Name: spi_setmode * * Description: @@ -716,7 +728,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * Returned Value: * Returns the actual frequency selected * - ************************************************************************************/ + ****************************************************************************/ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { @@ -764,7 +776,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) } } -/************************************************************************************ +/**************************************************************************** * Name: spi_setbits * * Description: @@ -777,7 +789,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) { @@ -798,13 +810,15 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) regval |= SPI_CTARM_FMSZ(nbits - 1); spi_putreg(priv, priv->ctarsel, regval); - /* Save the selection so that subsequent re-configurations will be faster. */ + /* Save the selection so that subsequent re-configurations will be + * faster. + */ priv->nbits = nbits; } } -/************************************************************************************ +/**************************************************************************** * Name: spi_hwfeatures * * Description: @@ -818,10 +832,11 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) * Zero (OK) if the selected H/W features are enabled; A negated errno * value if any H/W feature is not supportable. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SPI_HWFEATURES -static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features) +static int spi_hwfeatures(FAR struct spi_dev_s *dev, + spi_hwfeatures_t features) { #ifdef CONFIG_SPI_BITORDER FAR struct kinetis_spidev_s *priv = (FAR struct spi_dev_s *)dev; @@ -857,7 +872,7 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features) } #endif -/************************************************************************************ +/**************************************************************************** * Name: spi_send_data * * Description: @@ -871,7 +886,7 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features) * Returned Value: * response * - ************************************************************************************/ + ****************************************************************************/ static uint16_t spi_send_data(FAR struct kinetis_spidev_s *priv, uint16_t wd, bool last) @@ -906,7 +921,7 @@ static uint16_t spi_send_data(FAR struct kinetis_spidev_s *priv, uint16_t wd, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: spi_send * * Description: @@ -920,7 +935,7 @@ static uint16_t spi_send_data(FAR struct kinetis_spidev_s *priv, uint16_t wd, * Returned Value: * response * - ************************************************************************************/ + ****************************************************************************/ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) { @@ -929,7 +944,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) return (uint32_t)spi_send_data(priv, (uint16_t)wd, true); } -/************************************************************************************ +/**************************************************************************** * Name: spi_exchange * * Description: @@ -948,7 +963,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, FAR void *rxbuffer, size_t nwords) @@ -1024,7 +1039,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, } } -/************************************************************************************ +/**************************************************************************** * Name: spi_sndblock * * Description: @@ -1033,19 +1048,20 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, * Input Parameters: * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's + * nwords - the length of data to send from the buffer in number of + * words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, +static void spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, size_t nwords) { spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); @@ -1053,7 +1069,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, } #endif -/************************************************************************************ +/**************************************************************************** * Name: spi_recvblock * * Description: @@ -1062,16 +1078,16 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, * Input Parameters: * dev - Device-specific state data * rxbuffer - A pointer to the buffer in which to receive data - * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, @@ -1082,11 +1098,11 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, } #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_spibus_initialize * * Description: @@ -1098,7 +1114,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - ************************************************************************************/ + ****************************************************************************/ FAR struct spi_dev_s *kinetis_spibus_initialize(int port) { diff --git a/arch/arm/src/kinetis/kinetis_start.h b/arch/arm/src/kinetis/kinetis_start.h index c3682e8699..eb6a091ea4 100644 --- a/arch/arm/src/kinetis/kinetis_start.h +++ b/arch/arm/src/kinetis/kinetis_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_START_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_boardinitialize * * Description: - * All Kinetis architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All Kinetis architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void kinetis_boardinitialize(void); diff --git a/arch/arm/src/kinetis/kinetis_uart.h b/arch/arm/src/kinetis/kinetis_uart.h index 2d96962c92..29ef3666be 100644 --- a/arch/arm/src/kinetis/kinetis_uart.h +++ b/arch/arm/src/kinetis/kinetis_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_uart.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,21 +32,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H #if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ - + ****************************************************************************/ /* Is DMA available on any (enabled) UART? */ @@ -69,13 +68,13 @@ # endif #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -88,22 +87,22 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_serial_dma_poll * * Description: - * Must be called periodically if any Kinetis UART is configured for DMA. The DMA - * callback is triggered for each fifo size/2 bytes, but this can result in some - * bytes being transferred but not collected if the incoming data is not a whole - * multiple of half the FIFO size. + * Must be called periodically if any Kinetis UART is configured for DMA. + * The DMA callback is triggered for each fifo size/2 bytes, but this can + * result in some bytes being transferred but not collected if the incoming + * data is not a whole multiple of half the FIFO size. * * May be safely called from either interrupt or thread context. * - ************************************************************************************/ + ****************************************************************************/ #ifdef SERIAL_HAVE_DMA void kinetis_serial_dma_poll(void); diff --git a/arch/arm/src/kinetis/kinetis_uid.c b/arch/arm/src/kinetis/kinetis_uid.c index 6667a792a9..320b88020b 100644 --- a/arch/arm/src/kinetis/kinetis_uid.c +++ b/arch/arm/src/kinetis/kinetis_uid.c @@ -63,7 +63,7 @@ void kinetis_get_uniqueid(uint8_t *uniqueid) for (i = 0; i < (KINETIS_UID_SIZE / sizeof(uint32_t)); i++) { - unique_u32[i] = *((uint32_t*)(KINETIS_SIM_UIDL) - i); + unique_u32[i] = *((uint32_t *)(KINETIS_SIM_UIDL) - i); } } diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index cd76099128..4af48c2164 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -1,4 +1,4 @@ -/****************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/kinetis_usbdev.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -27,11 +27,11 @@ * K66 Sub-Family Reference Manual, Rev. 2, May 2015 * How to Implement USB Suspend/Resume - Document Number: AN5385 * - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************************/ + ****************************************************************************/ #include @@ -60,11 +60,11 @@ #if defined(CONFIG_USBDEV) -/****************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************************/ + ****************************************************************************/ -/* Configuration **************************************************************************/ +/* Configuration ************************************************************/ #ifndef CONFIG_USBDEV_EP0_MAXSIZE # define CONFIG_USBDEV_EP0_MAXSIZE 64 @@ -93,7 +93,7 @@ #undef CONFIG_USBDEV_NOWRITEAHEAD #define CONFIG_USBDEV_NOWRITEAHEAD /* Fixes some problems with IN transfers */ -/* Interrupts *****************************************************************************/ +/* Interrupts ***************************************************************/ /* Initial interrupt sets */ @@ -110,7 +110,7 @@ #define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \ USB_INT_TOKDNE | USB_INT_SLEEP | USB_INT_STALL) -/* Endpoints ******************************************************************************/ +/* Endpoints ****************************************************************/ #define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */ @@ -175,7 +175,7 @@ #define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK) -/* Request queue operations ***************************************************************/ +/* Request queue operations *************************************************/ #define khci_rqempty(q) ((q)->head == NULL) #define khci_rqhead(q) ((q)->head) @@ -187,7 +187,7 @@ * Kinetis lib */ -/* USB trace ******************************************************************************/ +/* USB trace ****************************************************************/ /* Trace error codes */ @@ -339,7 +339,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = }; #endif -/* Misc Helper Macros *********************************************************************/ +/* Misc Helper Macros *******************************************************/ /* Ever-present MIN and MAX macros */ @@ -361,7 +361,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = # define MSB 1 #endif -/* Debug **********************************************************************************/ +/* Debug ********************************************************************/ /* CONFIG_KHCI_USBDEV_REGDEBUG enables dumping of all low-level register * access and BDT accesses. Normally, this generates so much debug output @@ -386,9 +386,9 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = # define bdtinfo(x...) #endif -/****************************************************************************************** +/**************************************************************************** * Private Type Definitions - ******************************************************************************************/ + ****************************************************************************/ /* Overvall device state */ @@ -508,18 +508,18 @@ struct khci_usbdev_s struct khci_ep_s eplist[KHCI_NENDPOINTS]; }; -/****************************************************************************************** +/**************************************************************************** * Private Function Prototypes - ******************************************************************************************/ + ****************************************************************************/ -/* Register operations ********************************************************************/ +/* Register operations ******************************************************/ #ifdef CONFIG_KHCI_USBDEV_REGDEBUG static uint16_t khci_getreg(uint32_t addr); static void khci_putreg(uint32_t val, uint32_t addr); #endif -/* Suspend/Resume Helpers *****************************************************************/ +/* Suspend/Resume Helpers ***************************************************/ #ifndef CONFIG_KINETIS_USBOTG static void khci_suspend(struct khci_usbdev_s *priv); @@ -527,7 +527,7 @@ static void khci_suspend(struct khci_usbdev_s *priv); static void khci_remote_resume(struct khci_usbdev_s *priv); static void khci_resume(struct khci_usbdev_s *priv); -/* Request Queue Management ***************************************************************/ +/* Request Queue Management *************************************************/ static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue); static struct khci_req_s *khci_remlast(struct khci_queue_s *queue); @@ -536,7 +536,7 @@ static void khci_addlast(struct khci_queue_s *queue, static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req); -/* Request Helpers ************************************************************************/ +/* Request Helpers **********************************************************/ static void khci_reqreturn(struct khci_ep_s *privep, struct khci_req_s *privreq, int16_t result); @@ -566,7 +566,7 @@ static int khci_rdrequest(struct khci_usbdev_s *priv, static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result); -/* Interrupt level processing *************************************************************/ +/* Interrupt level processing ***********************************************/ static void khci_dispatchrequest(struct khci_usbdev_s *priv); static void khci_ep0stall(struct khci_usbdev_s *priv); @@ -581,7 +581,7 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat); static int khci_interrupt(int irq, void *context, FAR void *arg); -/* Endpoint helpers ***********************************************************************/ +/* Endpoint helpers *********************************************************/ static inline struct khci_ep_s * khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset); @@ -592,7 +592,7 @@ static inline bool khci_epreserved(struct khci_usbdev_s *priv, int epno); static void khci_ep0configure(struct khci_usbdev_s *priv); -/* Endpoint operations ********************************************************************/ +/* Endpoint operations ******************************************************/ static int khci_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); @@ -609,7 +609,7 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin); static int khci_epstall(struct usbdev_ep_s *ep, bool resume); -/* USB device controller operations *******************************************************/ +/* USB device controller operations *****************************************/ static struct usbdev_ep_s * khci_allocep(struct usbdev_s *dev, uint8_t epno, bool in, @@ -619,7 +619,7 @@ static int khci_getframe(struct usbdev_s *dev); static int khci_wakeup(struct usbdev_s *dev); static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered); -/* Initialization/Reset *******************************************************************/ +/* Initialization/Reset *****************************************************/ static void khci_reset(struct khci_usbdev_s *priv); static void khci_attach(struct khci_usbdev_s *priv); @@ -629,9 +629,9 @@ static void khci_swinitialize(struct khci_usbdev_s *priv); static void khci_hwinitialize(struct khci_usbdev_s *priv); static void khci_hwshutdown(struct khci_usbdev_s *priv); -/****************************************************************************************** +/**************************************************************************** * Private Data - ******************************************************************************************/ + ****************************************************************************/ /* Since there is only a single USB interface, all status information can be * be simply retained in a single global instance. @@ -664,8 +664,8 @@ static const struct usbdev_ops_s g_devops = * * The BDT is addressed in the hardware as follows: * - * Bits 9-31: These come the BDT address bits written into the BDTP3, BDTP2 - * and BDTP1 registers + * Bits 9-31: These come the BDT address bits written into the BDTP3, + * BDTP2 and BDTP1 registers * Bits 5-8: The endpoint number * Bit 4: Direction (0=IN/Tx, 1 = OUT/Rx) * Bit 3: PPBI, the ping point buffer index bit. @@ -675,17 +675,17 @@ static const struct usbdev_ops_s g_devops = static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS] __attribute__ ((aligned(512))); -/****************************************************************************************** +/**************************************************************************** * Private Private Functions - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Register Operations - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_getreg - ******************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KHCI_USBDEV_REGDEBUG static uint16_t khci_getreg(uint32_t addr) @@ -741,9 +741,9 @@ static uint16_t khci_getreg(uint32_t addr) } #endif -/****************************************************************************************** +/**************************************************************************** * Name: khci_putreg - ******************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KHCI_USBDEV_REGDEBUG static void khci_putreg(uint32_t val, uint32_t addr) @@ -758,13 +758,13 @@ static void khci_putreg(uint32_t val, uint32_t addr) } #endif -/****************************************************************************************** +/**************************************************************************** * Request Helpers - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_remfirst - ******************************************************************************************/ + ****************************************************************************/ static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue) { @@ -784,9 +784,9 @@ static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue) return ret; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_remlast - ******************************************************************************************/ + ****************************************************************************/ static struct khci_req_s *khci_remlast(struct khci_queue_s *queue) { @@ -820,9 +820,9 @@ static struct khci_req_s *khci_remlast(struct khci_queue_s *queue) return ret; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_addlast - ******************************************************************************************/ + ****************************************************************************/ static void khci_addlast(struct khci_queue_s *queue, struct khci_req_s *req) { @@ -839,9 +839,9 @@ static void khci_addlast(struct khci_queue_s *queue, struct khci_req_s *req) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_addfirst - ******************************************************************************************/ + ****************************************************************************/ static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req) { @@ -854,9 +854,9 @@ static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req) queue->head = req; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_reqreturn - ******************************************************************************************/ + ****************************************************************************/ static void khci_reqreturn(struct khci_ep_s *privep, struct khci_req_s *privreq, int16_t result) @@ -885,9 +885,9 @@ static void khci_reqreturn(struct khci_ep_s *privep, privep->stalled = stalled; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_reqcomplete - ******************************************************************************************/ + ****************************************************************************/ static void khci_reqcomplete(struct khci_ep_s *privep, int16_t result) { @@ -910,9 +910,9 @@ static void khci_reqcomplete(struct khci_ep_s *privep, int16_t result) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epwrite - ******************************************************************************************/ + ****************************************************************************/ static void khci_epwrite(struct khci_ep_s *privep, volatile struct usbotg_bdtentry_s *bdt, @@ -952,9 +952,9 @@ static void khci_epwrite(struct khci_ep_s *privep, bdt->status = status; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_wrcomplete - ******************************************************************************************/ + ****************************************************************************/ static void khci_wrcomplete(struct khci_usbdev_s *priv, struct khci_ep_s *privep) @@ -965,8 +965,8 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv, int epno; /* Check the request at the head of the endpoint's active request queue. - * Since we got here from a write completion event, the active request queue - * should not be empty. + * Since we got here from a write completion event, the active request + * queue should not be empty. */ privreq = khci_rqhead(&privep->active); @@ -990,11 +990,11 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv, bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdtin, bdtin->status, bdtin->addr); - /* We should own the BDT that just completed. But NULLify the entire BDT IN. - * Why? So that we can tell later that the BDT available. No, it is not - * sufficient to look at the UOWN bit. If UOWN==0, then the transfer has - * been completed BUT it may not yet have been processed. But a completely - * NULLified BDT is a sure indication + /* We should own the BDT that just completed. But NULLify the entire BDT + * IN. Why? So that we can tell later that the BDT available. No, it is + * not sufficient to look at the UOWN bit. If UOWN==0, then the transfer + * has been completed BUT it may not yet have been processed. + * But a completely NULLified BDT is a sure indication */ DEBUGASSERT((bdtin->status & USB_BDT_UOWN) == USB_BDT_COWN); @@ -1032,11 +1032,13 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv, * the class driver. */ - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + privreq->req.xfrd); khci_reqcomplete(privep, OK); /* Special case writes to endpoint zero. If there is no transfer in - * progress, then we need to configure to received the next SETUP packet. + * progress, then we need to configure to received the next SETUP + * packet. */ if (USB_EPNO(privep->ep.eplog) == 0) @@ -1046,9 +1048,9 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv, } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_rqrestart - ******************************************************************************************/ + ****************************************************************************/ static void khci_rqrestart(wdparm_t arg) { @@ -1088,7 +1090,9 @@ static void khci_rqrestart(wdparm_t arg) privep->stalled = false; privep->txnullpkt = false; - /* Check the request at the head of the endpoint's pending request queue */ + /* Check the request at the head of the endpoint's pending + * request queue + */ privreq = khci_rqhead(&privep->pend); if (privreq) @@ -1106,9 +1110,9 @@ static void khci_rqrestart(wdparm_t arg) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_delayedrestart - ******************************************************************************************/ + ****************************************************************************/ static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno) { @@ -1122,9 +1126,9 @@ static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno) khci_rqrestart, (wdparm_t)priv); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_rqstop - ******************************************************************************************/ + ****************************************************************************/ static void khci_rqstop(struct khci_ep_s *privep) { @@ -1140,9 +1144,9 @@ static void khci_rqstop(struct khci_ep_s *privep) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_wrstart - ******************************************************************************************/ + ****************************************************************************/ static int khci_wrstart(struct khci_usbdev_s *priv, struct khci_ep_s *privep) @@ -1350,11 +1354,12 @@ static int khci_wrstart(struct khci_usbdev_s *priv, return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_wrrequest - ******************************************************************************************/ + ****************************************************************************/ -static int khci_wrrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep) +static int khci_wrrequest(struct khci_usbdev_s *priv, + struct khci_ep_s *privep) { int ret; @@ -1381,9 +1386,9 @@ static int khci_wrrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep) return khci_rqhead(&privep->active) == NULL ? -ENODATA : OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_rdcomplete - ******************************************************************************************/ + ****************************************************************************/ static int khci_rdcomplete(struct khci_usbdev_s *priv, struct khci_ep_s *privep) @@ -1422,17 +1427,18 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv, /* Get the length of the data received from the BDT. */ - privreq->req.xfrd = (bdtout->status & USB_BDT_BYTECOUNT_MASK) >> USB_BDT_BYTECOUNT_SHIFT; + privreq->req.xfrd = (bdtout->status & USB_BDT_BYTECOUNT_MASK) >> + USB_BDT_BYTECOUNT_SHIFT; /* Complete the transfer and return the request to the class driver. */ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); khci_reqcomplete(privep, OK); - /* Nullify the BDT entry that just completed. Why? So that we can tell later - * that the BDT has been processed. No, it is not sufficient to look at the - * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may not - * yet have been processed. + /* Nullify the BDT entry that just completed. Why? So that we can tell + * later that the BDT has been processed. No, it is not sufficient to look + * at the UOWN bit. If UOWN==0, then the transfer has been completed BUT + * it may not yet have been processed. */ bdtout->status = 0; @@ -1453,9 +1459,9 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv, return khci_rdrequest(priv, privep); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0rdsetup - ******************************************************************************************/ + ****************************************************************************/ static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest, int readlen) @@ -1565,9 +1571,9 @@ static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest, return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_rdsetup - ******************************************************************************************/ + ****************************************************************************/ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen) { @@ -1629,8 +1635,8 @@ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen) usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), readlen); - /* Clear status bits (making sure that UOWN is cleared before doing anything - * else). + /* Clear status bits (making sure that UOWN is cleared before doing + * anything else). */ bdtout->status = 0; @@ -1665,9 +1671,9 @@ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen) return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_rdrequest - ******************************************************************************************/ + ****************************************************************************/ static int khci_rdrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep) @@ -1686,8 +1692,9 @@ static int khci_rdrequest(struct khci_usbdev_s *priv, usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY), USB_EPNO(privep->ep.eplog)); - /* Special case reads from to endpoint zero. If there is no transfer in - * progress, then we need to configure to received the next SETUP packet. + /* Special case reads from to endpoint zero. If there is no transfer + * in progress, then we need to configure to received the next SETUP + * packet. */ if (USB_EPNO(privep->ep.eplog) == 0 && @@ -1743,9 +1750,9 @@ static int khci_rdrequest(struct khci_usbdev_s *priv, return ret; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_cancelrequests - ******************************************************************************************/ + ****************************************************************************/ static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result) { @@ -1753,24 +1760,26 @@ static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result) while ((privreq = khci_remfirst(&privep->active))) { - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + privreq->req.xfrd); khci_reqreturn(privep, privreq, result); } while ((privreq = khci_remfirst(&privep->pend))) { - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + privreq->req.xfrd); khci_reqreturn(privep, privreq, result); } } -/****************************************************************************************** +/**************************************************************************** * Interrupt Level Processing - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_dispatchrequest - ******************************************************************************************/ + ****************************************************************************/ static void khci_dispatchrequest(struct khci_usbdev_s *priv) { @@ -1793,9 +1802,9 @@ static void khci_dispatchrequest(struct khci_usbdev_s *priv) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0stall - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0stall(struct khci_usbdev_s *priv) { @@ -1813,9 +1822,9 @@ static void khci_ep0stall(struct khci_usbdev_s *priv) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_eptransfer - ******************************************************************************************/ + ****************************************************************************/ static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno, uint16_t ustat) @@ -1857,8 +1866,8 @@ static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno, usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINDONE), ustat); - /* An outgoing IN packet has completed. Update the number of bytes transferred - * and check for completion of the transfer. + /* An outgoing IN packet has completed. Update the number of bytes + * transferred and check for completion of the transfer. */ khci_wrcomplete(priv, privep); @@ -1869,7 +1878,7 @@ static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno, } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0nextsetup * * Description: @@ -1878,17 +1887,17 @@ static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno, * transfers). It simply sets up the single BDT to accept the next * SETUP command. * - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0nextsetup(struct khci_usbdev_s *priv) { volatile struct usbotg_bdtentry_s *bdt = priv->eplist[EP0].bdtout; uint32_t bytecount; - /* This operation should be performed no more than once per OUT transaction. - * priv->ep0done is set to zero at the beginning of processing of each EP0 - * transfer. It is set the first time that this function runs after the EP0 - * transfer. + /* This operation should be performed no more than once per OUT + * transaction. priv->ep0done is set to zero at the beginning of processing + * of each EP0 transfer. It is set the first time that this function runs + * after the EP0 transfer. */ if (!priv->ep0done) @@ -1908,7 +1917,7 @@ static void khci_ep0nextsetup(struct khci_usbdev_s *priv) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0rdcomplete * * Description: @@ -1916,7 +1925,7 @@ static void khci_ep0nextsetup(struct khci_usbdev_s *priv) * context, only one BDT is used. Both BDTs must be prepared to receive * SETUP packets. * - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0rdcomplete(struct khci_usbdev_s *priv) { @@ -1924,10 +1933,10 @@ static void khci_ep0rdcomplete(struct khci_usbdev_s *priv) struct khci_ep_s *ep0; uint32_t bytecount; - /* This operation should be performed no more than once per OUT transaction. - * priv->ep0done is set to zero at the beginning of processing of each EP0 - * transfer. It is set the first time that this function runs after the EP0 - * transfer. + /* This operation should be performed no more than once per OUT + * transaction. priv->ep0done is set to zero at the beginning of processing + * of each EP0 transfer. It is set the first time that this function runs + * after the EP0 transfer. */ if (!priv->ep0done) @@ -1954,9 +1963,9 @@ static void khci_ep0rdcomplete(struct khci_usbdev_s *priv) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0setup - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0setup(struct khci_usbdev_s *priv) { @@ -2030,7 +2039,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_NOSTDREQ), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_NOSTDREQ), + priv->ctrl.type); /* Let the class implementation handle all non-standard requests */ @@ -2040,24 +2050,28 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) else { /* Handle standard request. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver + * USB device controller driver; pass what is left to the class + * driver */ switch (priv->ctrl.req) { case USB_REQ_GETSTATUS: { - /* type: device-to-host; recipient = device, interface, endpoint + /* type: device-to-host; recipient = device, interface, + * endpoint * value: 0 * index: zero interface endpoint * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSTATUS), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSTATUS), + priv->ctrl.type); if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || index.b[MSB] != 0 || value.w != 0) { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR( + KHCI_TRACEERR_BADEPGETSTATUS), 0); priv->ctrlstate = CTRLSTATE_STALL; } else @@ -2067,10 +2081,12 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPGETSTATUS), epno); + usbtrace(TRACE_INTDECODE( + KHCI_TRACEINTID_EPGETSTATUS), epno); if (epno >= KHCI_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), epno); + usbtrace(TRACE_DEVERROR( + KHCI_TRACEERR_BADEPGETSTATUS), epno); priv->ctrlstate = CTRLSTATE_STALL; } else @@ -2106,19 +2122,26 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) { if (index.w == 0) { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE( + KHCI_TRACEINTID_DEVGETSTATUS), 0); - /* Features: Remote Wakeup=YES; selfpowered=? */ + /* Features: + * Remote Wakeup=YES; + * selfpowered=? + */ response.w = 0; response.b[LSB] = - (priv->selfpowered << USB_FEATURE_SELFPOWERED) | - (priv->rwakeup << USB_FEATURE_REMOTEWAKEUP); - nbytes = 2; /* Response size: 2 bytes */ + (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | + (priv->rwakeup << + USB_FEATURE_REMOTEWAKEUP); + nbytes = 2; /* Response size: 2 bytes */ } else { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR( + KHCI_TRACEERR_BADDEVGETSTATUS), 0); priv->ctrlstate = CTRLSTATE_STALL; } } @@ -2126,7 +2149,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IFGETSTATUS), 0); + usbtrace(TRACE_INTDECODE( + KHCI_TRACEINTID_IFGETSTATUS), 0); response.w = 0; nbytes = 2; /* Response size: 2 bytes */ } @@ -2134,7 +2158,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR( + KHCI_TRACEERR_BADGETSTATUS), 0); priv->ctrlstate = CTRLSTATE_STALL; } break; @@ -2145,14 +2170,17 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) case USB_REQ_CLEARFEATURE: { - /* type: host-to-device; recipient = device, interface or endpoint + /* type: host-to-device; recipient = device, interface or + * endpoint * value: feature selector * index: zero interface endpoint; * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_CLEARFEATURE), priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_CLEARFEATURE), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) { /* Disable B device from performing HNP */ @@ -2188,7 +2216,9 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) } else { - /* Let the class implementation handle all other device features */ + /* Let the class implementation handle all other + * device features + */ khci_dispatchrequest(priv); dispatched = true; @@ -2198,7 +2228,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) USB_REQ_RECIPIENT_ENDPOINT) { epno = USB_EPNO(index.b[LSB]); - if (epno > 0 && epno < KHCI_NENDPOINTS && index.b[MSB] == 0 && + if (epno > 0 && epno < + KHCI_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -2208,13 +2239,16 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR( + KHCI_TRACEERR_BADCLEARFEATURE), 0); priv->ctrlstate = CTRLSTATE_STALL; } } else { - /* Let the class implementation handle all other recipients. */ + /* Let the class implementation handle all other + * recipients. + */ khci_dispatchrequest(priv); dispatched = true; @@ -2224,15 +2258,18 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) case USB_REQ_SETFEATURE: { - /* type: host-to-device; recipient = device, interface, endpoint + /* type: host-to-device; recipient = device, interface, + * endpoint * value: feature selector * index: zero interface endpoint; * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETFEATURE), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETFEATURE), + priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) { /* Enable B device to perform HNP */ @@ -2273,7 +2310,9 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) } else { - /* Let the class implementation handle all other device features */ + /* Let the class implementation handle all other + * device features + */ khci_dispatchrequest(priv); dispatched = true; @@ -2295,13 +2334,16 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR( + KHCI_TRACEERR_BADSETFEATURE), 0); priv->ctrlstate = CTRLSTATE_STALL; } } else { - /* The class driver handles all recipients except recipient=endpoint */ + /* The class driver handles all recipients except + * recipient=endpoint + */ khci_dispatchrequest(priv); dispatched = true; @@ -2317,7 +2359,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPSETADDRESS), value.w); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPSETADDRESS), + value.w); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) @@ -2327,9 +2370,10 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) } else { - /* Note that setting of the device address will be deferred. - * A zero-length packet will be sent and the device address will - * be set when the zerolength packet transfer completes. + /* Note that setting of the device address will be + * deferred. A zero-length packet will be sent and the + * device address will be set when the zerolength packet + * transfer completes. */ priv->devstate = DEVSTATE_ADDRPENDING; @@ -2352,11 +2396,14 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETDESC), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETDESC), + priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { - /* The request seems valid... let the class implementation handle it */ + /* The request seems valid... + * let the class implementation handle it + */ khci_dispatchrequest(priv); dispatched = true; @@ -2377,11 +2424,15 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETCONFIG), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETCONFIG), + priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && value.w == 0 && index.w == 0 && len.w == 1) + USB_REQ_RECIPIENT_DEVICE && value.w == 0 && + index.w == 0 && len.w == 1) { - /* The request seems valid... let the class implementation handle it */ + /* The request seems valid... let the class + * implementation handle it + */ khci_dispatchrequest(priv); dispatched = true; @@ -2402,11 +2453,14 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETCONFIG), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETCONFIG), + priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) { - /* The request seems valid. Let the class implementation handle it */ + /* The request seems valid. Let the class implementation + * handle it + */ khci_dispatchrequest(priv); dispatched = true; @@ -2436,7 +2490,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) { /* Let the class implementation handle the request */ - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETIF), priv->ctrl.type); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETIF), + priv->ctrl.type); khci_dispatchrequest(priv); dispatched = true; } @@ -2456,7 +2511,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDCTRLREQ), + priv->ctrl.req); priv->ctrlstate = CTRLSTATE_STALL; } break; @@ -2475,27 +2531,30 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) /* At this point, the request has been handled and there are three possible * outcomes: * - * 1. The setup request was successfully handled above and a response packet - * must be sent (may be a zero length packet). - * 2. The request was successfully handled by the class implementation. In - * case, the EP0 IN response has already been queued and the local variable - * 'dispatched' will be set to true and ctrlstate != CTRLSTATE_STALL; - * 3. An error was detected in either the above logic or by the class implementation - * logic. In either case, priv->state will be set CTRLSTATE_STALL - * to indicate this case. + * 1. The setup request was successfully handled above and a response + * packet must be sent (may be a zero length packet). + * 2. The request was successfully handled by the class implementation. + * In case, the EP0 IN response has already been queued and the local + * variable 'dispatched' will be set to true and ctrlstate != + * CTRLSTATE_STALL; + * 3. An error was detected in either the above logic or by the class + * implementation logic. In either case, priv->state will be set + * CTRLSTATE_STALL to indicate this case. * - * NOTE: Non-standard requests are a special case. They are handled by the - * class implementation and this function returned early above, skipping this - * logic altogether. + * NOTE: + * Non-standard requests are a special case. They are handled by the + * class implementation and this function returned early above, skipping + * this logic altogether. */ if (priv->ctrlstate == CTRLSTATE_SETUP_READY) { if (!dispatched) { - /* The SETUP command was not dispatched to the class driver and the SETUP - * command did not cause a stall. We will respond. First, restrict the - * data length to the length requested in the setup packet + /* The SETUP command was not dispatched to the class driver and the + * SETUP command did not cause a stall. We will respond. First, + * restrict the data length to the length requested in the setup + * packet */ if (nbytes > len.w) @@ -2512,14 +2571,16 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) } else if (priv->ctrlstate == CTRLSTATE_STALL) { - /* Did we stall? This might have occurred from the above logic OR the stall - * condition may have been set less obviously in khci_dispatchrequest(). + /* Did we stall? + * This might have occurred from the above logic OR the stall condition + * may have been set less obviously in khci_dispatchrequest(). * In either case, we handle the stall condition the same. * - * However, bad things happen if we try to stall a SETUP packet. So lets - * not. If we wait a bit, things will recover. Hmmm.. If we completed - * the data phase (perhaps by sending a NULL packet), then I think we - * could stall the endpoint and perhaps speed things up a bit???. + * However, bad things happen if we try to stall a SETUP packet. So + * lets So lets not. If we wait a bit, things will recover. + * Hmmm.. If we completed the data phase (perhaps by sending a NULL + * packet), then I think we could stall the endpoint and perhaps speed + * things up a bit???. */ priv->ctrlstate = CTRLSTATE_WAITSETUP; @@ -2530,9 +2591,9 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) khci_ep0nextsetup(priv); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0incomplete - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0incomplete(struct khci_usbdev_s *priv) { @@ -2631,14 +2692,15 @@ static void khci_ep0incomplete(struct khci_usbdev_s *priv) else { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate); + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), + priv->ctrlstate); priv->ctrlstate = CTRLSTATE_STALL; } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0outcomplete - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0outcomplete(struct khci_usbdev_s *priv) { @@ -2669,30 +2731,31 @@ static void khci_ep0outcomplete(struct khci_usbdev_s *priv) case CTRLSTATE_WAITSETUP: { /* In this case the last OUT transaction must have been a status - * stage of a CTRLSTATE_WRREQUEST: Prepare EP0 OUT for the next SETUP - * transaction. + * stage of a CTRLSTATE_WRREQUEST: Prepare EP0 OUT for the next + * SETUP transaction. */ khci_ep0nextsetup(priv); } break; - /* Unexpected state OR host aborted the OUT transfer before it completed, - * STALL the endpoint in either case + /* Unexpected state OR host aborted the OUT transfer before it + * completed, STALL the endpoint in either case */ default: { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate); + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), + priv->ctrlstate); priv->ctrlstate = CTRLSTATE_STALL; } break; } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0transfer - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) { @@ -2719,11 +2782,13 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) bdt = &g_bdt[index]; priv->eplist[0].bdtout = bdt; - bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr); + bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, + bdt->addr); /* Check the current EP0 OUT buffer contains a SETUP packet */ - if (((bdt->status & USB_BDT_PID_MASK) >> USB_BDT_PID_SHIFT) == USB_PID_SETUP_TOKEN) + if (((bdt->status & USB_BDT_PID_MASK) >> + USB_BDT_PID_SHIFT) == USB_PID_SETUP_TOKEN) { void *src = (void *)bdt->addr; void *dest = &priv->ctrl; @@ -2736,11 +2801,13 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) if (priv->ctrlstate == CTRLSTATE_WAITSETUP) { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), bdt->status); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), + bdt->status); } else { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPOUT), bdt->status); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPOUT), + bdt->status); } } else if (priv->ctrlstate == CTRLSTATE_SETUP_OUT) @@ -2763,11 +2830,13 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) if (priv->ctrlstate == CTRLSTATE_WAITSETUP) { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), bdt->status); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), + bdt->status); } else { - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPOUTDATA), bdt->status); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPOUTDATA), + bdt->status); } } else @@ -2796,14 +2865,15 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) { /* Stall EP0 */ - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EP0SETUPSTALLED), priv->ctrlstate); + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EP0SETUPSTALLED), + priv->ctrlstate); khci_epstall(&priv->eplist[EP0].ep, false); } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_interrupt - ******************************************************************************************/ + ****************************************************************************/ static int khci_interrupt(int irq, void *context, FAR void *arg) { @@ -2818,12 +2888,14 @@ static int khci_interrupt(int irq, void *context, FAR void *arg) /* Get the set of pending USB and OTG interrupts interrupts */ - usbir = khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_INTEN); + usbir = khci_getreg(KINETIS_USB0_ISTAT) & + khci_getreg(KINETIS_USB0_INTEN); #if !defined(CONFIG_KINETIS_USBOTG) usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir); #else - otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & khci_getreg(KINETIS_USB0_OTGICR); + otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & + khci_getreg(KINETIS_USB0_OTGICR); usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir | otgir); @@ -2940,7 +3012,9 @@ static int khci_interrupt(int irq, void *context, FAR void *arg) { uint8_t epno; - /* Check the pending interrupt register. Is token processing complete. */ + /* Check the pending interrupt register. + * Is token processing complete. + */ if ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0) { @@ -2997,17 +3071,22 @@ static int khci_interrupt(int irq, void *context, FAR void *arg) khci_putreg(regval, KINETIS_USB0_USBTRC0); } - /* It is pointless to continue servicing if the device is in suspend mode. */ + /* It is pointless to continue servicing if the device is in suspend + * mode. + */ if ((khci_getreg(KINETIS_USB0_USBCTRL) & USB_USBCTRL_SUSP) != 0) { - /* If we are still suspended then re-enable asynchronous resume interrupt */ + /* If we are still suspended then re-enable asynchronous resume + * interrupt + */ regval = khci_getreg(KINETIS_USB0_USBTRC0); regval |= USB_USBTRC0_USBRESMEN; khci_putreg(regval, KINETIS_USB0_USBTRC0); - usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SUSPENDED), khci_getreg(KINETIS_USB0_CTL)); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SUSPENDED), + khci_getreg(KINETIS_USB0_CTL)); goto interrupt_exit; } @@ -3051,13 +3130,13 @@ interrupt_exit: return OK; } -/****************************************************************************************** +/**************************************************************************** * Suspend/Resume Helpers - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_suspend - ******************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_KINETIS_USBOTG static void khci_suspend(struct khci_usbdev_s *priv) @@ -3098,9 +3177,9 @@ static void khci_suspend(struct khci_usbdev_s *priv) } #endif -/****************************************************************************************** +/**************************************************************************** * Name: khci_remote_resume - ******************************************************************************************/ + ****************************************************************************/ static void khci_remote_resume(struct khci_usbdev_s *priv) { @@ -3120,9 +3199,9 @@ static void khci_remote_resume(struct khci_usbdev_s *priv) khci_putreg(regval, KINETIS_USB0_CTL); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_resume - ******************************************************************************************/ + ****************************************************************************/ static void khci_resume(struct khci_usbdev_s *priv) { @@ -3173,13 +3252,13 @@ static void khci_resume(struct khci_usbdev_s *priv) leave_critical_section(flags); } -/****************************************************************************************** +/**************************************************************************** * Endpoint Helpers - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_epreserve - ******************************************************************************************/ + ****************************************************************************/ static inline struct khci_ep_s * khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset) @@ -3217,9 +3296,9 @@ khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset) return privep; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epunreserve - ******************************************************************************************/ + ****************************************************************************/ static inline void khci_epunreserve(struct khci_usbdev_s *priv, struct khci_ep_s *privep) @@ -3229,9 +3308,9 @@ khci_epunreserve(struct khci_usbdev_s *priv, struct khci_ep_s *privep) leave_critical_section(flags); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epreserved - ******************************************************************************************/ + ****************************************************************************/ static inline bool khci_epreserved(struct khci_usbdev_s *priv, int epno) @@ -3239,9 +3318,9 @@ khci_epreserved(struct khci_usbdev_s *priv, int epno) return ((priv->epavail & KHCI_ENDP_BIT(epno)) == 0); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_ep0configure - ******************************************************************************************/ + ****************************************************************************/ static void khci_ep0configure(struct khci_usbdev_s *priv) { @@ -3293,16 +3372,17 @@ static void khci_ep0configure(struct khci_usbdev_s *priv) khci_putreg(KHCI_EP_CONTROL, KINETIS_USB0_ENDPT0); } -/****************************************************************************************** +/**************************************************************************** * Endpoint operations - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_epconfigure - ******************************************************************************************/ + ****************************************************************************/ -static int khci_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, - bool last) +static int khci_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) { struct khci_ep_s *privep = (struct khci_ep_s *)ep; volatile struct usbotg_bdtentry_s *bdt; @@ -3352,7 +3432,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *d break; default: - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPTYPE), (uint16_t)desc->type); + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPTYPE), + (uint16_t)desc->type); return -EINVAL; } @@ -3418,7 +3499,9 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *d DEBUGASSERT(maxpacket <= KHCI_MAXPACKET_SIZE); ep->maxpacket = maxpacket; - /* Set the full, logic EP number (that includes direction encoded in bit 7) */ + /* Set the full, logic EP number + * (that includes direction encoded in bit 7) + */ if (epin) { @@ -3434,9 +3517,9 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *d return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epdisable - ******************************************************************************************/ + ****************************************************************************/ static int khci_epdisable(struct usbdev_ep_s *ep) { @@ -3482,9 +3565,9 @@ static int khci_epdisable(struct usbdev_ep_s *ep) return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epallocreq - ******************************************************************************************/ + ****************************************************************************/ static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep) { @@ -3511,9 +3594,9 @@ static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep) return &privreq->req; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epfreereq - ******************************************************************************************/ + ****************************************************************************/ static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { @@ -3532,9 +3615,9 @@ static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) kmm_free(privreq); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epsubmit - ******************************************************************************************/ + ****************************************************************************/ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { @@ -3561,7 +3644,8 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } @@ -3624,9 +3708,9 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) return ret; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epcancel - ******************************************************************************************/ + ****************************************************************************/ static int khci_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { @@ -3649,9 +3733,9 @@ static int khci_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epbdtstall - ******************************************************************************************/ + ****************************************************************************/ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) { @@ -3736,7 +3820,8 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) if (epno == 0 && !epin) { - uint32_t bytecount = (CONFIG_USBDEV_EP0_MAXSIZE << USB_BDT_BYTECOUNT_SHIFT); + uint32_t bytecount = (CONFIG_USBDEV_EP0_MAXSIZE << + USB_BDT_BYTECOUNT_SHIFT); /* Configure the other BDT to receive a SETUP command. */ @@ -3784,11 +3869,12 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + epno, epin ? "IN" : "OUT", otherbdt, + otherbdt->status, otherbdt->addr); - /* Restart any queued requests (after a delay so that we can be assured - * that the hardware has recovered from the stall -- I don't know of any - * other way to assure this.). + /* Restart any queued requests (after a delay so that we can be + * assured that the hardware has recovered from the stall -- I + * don't know of any other way to assure this.). */ khci_delayedrestart(priv, epno); @@ -3819,15 +3905,16 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + epno, epin ? "IN" : "OUT", otherbdt, + otherbdt->status, otherbdt->addr); } return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_epstall - ******************************************************************************************/ + ****************************************************************************/ static int khci_epstall(struct usbdev_ep_s *ep, bool resume) { @@ -3865,7 +3952,8 @@ static int khci_epstall(struct usbdev_ep_s *ep, bool resume) /* Set the EP0 control state appropriately */ - privep->dev->ctrlstate = resume ? CTRLSTATE_WAITSETUP : CTRLSTATE_STALLED; + privep->dev->ctrlstate = resume ? + CTRLSTATE_WAITSETUP : CTRLSTATE_STALLED; } /* Otherwise, select the BDT for the endpoint direction */ @@ -3881,13 +3969,13 @@ static int khci_epstall(struct usbdev_ep_s *ep, bool resume) return ret; } -/****************************************************************************************** +/**************************************************************************** * Device Controller Operations - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_allocep - ******************************************************************************************/ + ****************************************************************************/ static struct usbdev_ep_s *khci_allocep(struct usbdev_s *dev, uint8_t epno, bool epin, uint8_t eptype) @@ -3913,11 +4001,12 @@ static struct usbdev_ep_s *khci_allocep(struct usbdev_s *dev, uint8_t epno, if (epno > 0) { - /* Otherwise, we will return the endpoint structure only for the requested - * 'logical' endpoint. All of the other checks will still be performed. + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still + * be performed. * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. + * First, verify that the logical endpoint is in the range supported + * by by the hardware. */ if (epno >= KHCI_NENDPOINTS) @@ -3946,9 +4035,9 @@ static struct usbdev_ep_s *khci_allocep(struct usbdev_s *dev, uint8_t epno, return &privep->ep; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_freeep - ******************************************************************************************/ + ****************************************************************************/ static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) { @@ -3977,9 +4066,9 @@ static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) khci_epunreserve(priv, privep); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_getframe - ******************************************************************************************/ + ****************************************************************************/ static int khci_getframe(struct usbdev_s *dev) { @@ -4019,9 +4108,9 @@ static int khci_getframe(struct usbdev_s *dev) return tmp; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_wakeup - ******************************************************************************************/ + ****************************************************************************/ static int khci_wakeup(struct usbdev_s *dev) { @@ -4042,9 +4131,9 @@ static int khci_wakeup(struct usbdev_s *dev) return OK; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_selfpowered - ******************************************************************************************/ + ****************************************************************************/ static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered) { @@ -4064,18 +4153,18 @@ static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered) return OK; } -/****************************************************************************************** +/**************************************************************************** * Initialization/Reset - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: khci_reset * * Description: * Reset the software and hardware states. At the end of this reset, the * hardware should be in the full up, ready-to-run state. * - ******************************************************************************************/ + ****************************************************************************/ static void khci_reset(struct khci_usbdev_s *priv) { @@ -4092,9 +4181,9 @@ static void khci_reset(struct khci_usbdev_s *priv) khci_attach(priv); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_attach - ******************************************************************************************/ + ****************************************************************************/ static void khci_attach(struct khci_usbdev_s *priv) { @@ -4178,9 +4267,9 @@ static void khci_attach(struct khci_usbdev_s *priv) } } -/****************************************************************************************** +/**************************************************************************** * Name: khci_swreset - ******************************************************************************************/ + ****************************************************************************/ static void khci_swreset(struct khci_usbdev_s *priv) { @@ -4226,13 +4315,13 @@ static void khci_swreset(struct khci_usbdev_s *priv) priv->rxbusy = 0; } -/****************************************************************************************** +/**************************************************************************** * Name: khci_hwreset * * Description: * Reset the hardware and leave it in a known, unready state. * - ******************************************************************************************/ + ****************************************************************************/ static void khci_hwreset(struct khci_usbdev_s *priv) { @@ -4276,13 +4365,13 @@ static void khci_hwreset(struct khci_usbdev_s *priv) khci_putreg(NORMAL_INTERRUPTS, KINETIS_USB0_INTEN); } -/****************************************************************************************** +/**************************************************************************** * Name: khci_hwinitialize * * Description: * Reset the hardware and leave it in a known, unready state. * - ******************************************************************************************/ + ****************************************************************************/ static void khci_hwinitialize(struct khci_usbdev_s *priv) { @@ -4336,9 +4425,9 @@ static void khci_hwinitialize(struct khci_usbdev_s *priv) #endif } -/****************************************************************************************** +/**************************************************************************** * Name: khci_swinitialize - ******************************************************************************************/ + ****************************************************************************/ static void khci_swinitialize(struct khci_usbdev_s *priv) { @@ -4387,9 +4476,9 @@ static void khci_swinitialize(struct khci_usbdev_s *priv) #endif } -/****************************************************************************************** +/**************************************************************************** * Name: khci_hwshutdown - ******************************************************************************************/ + ****************************************************************************/ static void khci_hwshutdown(struct khci_usbdev_s *priv) { @@ -4406,11 +4495,11 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv) kinetis_clrpend(KINETIS_IRQ_USBOTG); } -/****************************************************************************************** +/**************************************************************************** * Public Functions - ******************************************************************************************/ + ****************************************************************************/ -/****************************************************************************************** +/**************************************************************************** * Name: arm_usbinitialize * * Description: @@ -4429,7 +4518,7 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv) * Returned Value: * None * - ******************************************************************************************/ + ****************************************************************************/ void arm_usbinitialize(void) { @@ -4494,7 +4583,7 @@ void arm_usbinitialize(void) khci_hwinitialize(priv); } -/****************************************************************************************** +/**************************************************************************** * Name: arm_usbuninitialize * Description: * Initialize the USB driver @@ -4504,7 +4593,7 @@ void arm_usbinitialize(void) * Returned Value: * None * - ******************************************************************************************/ + ****************************************************************************/ void arm_usbuninitialize(void) { @@ -4548,14 +4637,14 @@ void arm_usbuninitialize(void) leave_critical_section(flags); } -/****************************************************************************************** +/**************************************************************************** * Name: usbdev_register * * Description: * Register a USB device class driver. The class driver's bind() method * will be called to bind it to a USB device driver. * - ******************************************************************************************/ + ****************************************************************************/ int usbdev_register(struct usbdevclass_driver_s *driver) { @@ -4610,7 +4699,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) return ret; } -/****************************************************************************************** +/**************************************************************************** * Name: usbdev_unregister * * Description: @@ -4619,7 +4708,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * unbind() and clean up any device state, before this procedure finally * returns. * - ******************************************************************************************/ + ****************************************************************************/ int usbdev_unregister(struct usbdevclass_driver_s *driver) { diff --git a/arch/arm/src/kinetis/kinetis_usbhshost.c b/arch/arm/src/kinetis/kinetis_usbhshost.c index a73f21e55f..933b9d333a 100644 --- a/arch/arm/src/kinetis/kinetis_usbhshost.c +++ b/arch/arm/src/kinetis/kinetis_usbhshost.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_usbhshost.c * * Copyright (C) 2013-2017, 2020 Gregory Nutt. All rights reserved. @@ -33,11 +33,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -73,11 +73,11 @@ #if defined(CONFIG_KINETIS_USBHS) && defined(CONFIG_USBHOST) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ /* Pre-requisites */ @@ -129,7 +129,7 @@ #undef CONFIG_USBHOST_ISOC_DISABLE #define CONFIG_USBHOST_ISOC_DISABLE 1 -/* Registers ************************************************************************ +/* Registers **************************************************************** * Traditionally, NuttX specifies register locations using individual * register offsets from a base address. That tradition is broken here and, * instead, register blocks are represented as structures. This is done here @@ -149,7 +149,7 @@ #define HCOR ((volatile struct ehci_hcor_s *)KINETIS_USBHS_HCOR_BASE) -/* Interrupts *********************************************************************** +/* Interrupts *************************************************************** * This is the set of interrupts handled by this driver. */ @@ -167,7 +167,7 @@ #define FRAME_LIST_SIZE 1024 -/* DMA ******************************************************************************/ +/* DMA **********************************************************************/ /* For now, we are assuming an identity mapping between physical and virtual * address spaces. @@ -176,7 +176,7 @@ #define kinetis_physramaddr(a) (a) #define kinetis_virtramaddr(a) (a) -/* USB trace ************************************************************************/ +/* USB trace ****************************************************************/ #ifdef HAVE_USBHOST_TRACE # define TR_FMT1 false @@ -198,9 +198,9 @@ #define RHPNDX(rh) ((rh)->hport.hport.port) #define RHPORT(rh) (RHPNDX(rh)+1) -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ /* Internal representation of the EHCI Queue Head (QH) */ @@ -219,7 +219,9 @@ struct kinetis_qh_s struct kinetis_qh_s *flink; /* Link for async await and free list */ }; -/* Internal representation of the EHCI Queue Element Transfer Descriptor (qTD) */ +/* Internal representation of the + * EHCI Queue Element Transfer Descriptor (qTD) + */ struct kinetis_qtd_s { @@ -406,11 +408,11 @@ struct kinetis_ehci_trace_s #endif /* HAVE_USBHOST_TRACE */ -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/* Register operations **************************************************************/ +/* Register operations ******************************************************/ static uint16_t kinetis_read16(const uint8_t *addr); static uint32_t kinetis_read32(const uint8_t *addr); @@ -436,35 +438,37 @@ static uint32_t kinetis_getreg(volatile uint32_t *regaddr); static void kinetis_putreg(uint32_t regval, volatile uint32_t *regaddr); #else static inline uint32_t kinetis_getreg(volatile uint32_t *regaddr); -static inline void kinetis_putreg(uint32_t regval, volatile uint32_t *regaddr); +static inline void kinetis_putreg(uint32_t regval, + volatile uint32_t *regaddr); #endif static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits, unsigned int delay); -/* Semaphores ***********************************************************************/ +/* Semaphores ***************************************************************/ static int kinetis_takesem(sem_t *sem); static int kinetis_takesem_noncancelable(sem_t *sem); #define kinetis_givesem(s) nxsem_post(s); -/* Allocators ***********************************************************************/ +/* Allocators ***************************************************************/ static struct kinetis_qh_s *kinetis_qh_alloc(void); static void kinetis_qh_free(struct kinetis_qh_s *qh); static struct kinetis_qtd_s *kinetis_qtd_alloc(void); static void kinetis_qtd_free(struct kinetis_qtd_s *qtd); -/* List Management ******************************************************************/ +/* List Management **********************************************************/ static int kinetis_qh_foreach(struct kinetis_qh_s *qh, uint32_t **bp, foreach_qh_t handler, void *arg); -static int kinetis_qtd_foreach(struct kinetis_qh_s *qh, foreach_qtd_t handler, +static int kinetis_qtd_foreach(struct kinetis_qh_s *qh, + foreach_qtd_t handler, void *arg); static int kinetis_qtd_discard(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg); static int kinetis_qh_discard(struct kinetis_qh_s *qh); -/* Cache Operations *****************************************************************/ +/* Cache Operations *********************************************************/ #if 0 /* Not used */ static int kinetis_qtd_invalidate(struct kinetis_qtd_s *qtd, uint32_t **bp, @@ -475,13 +479,15 @@ static int kinetis_qtd_flush(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg); static int kinetis_qh_flush(struct kinetis_qh_s *qh); -/* Endpoint Transfer Handling *******************************************************/ +/* Endpoint Transfer Handling ***********************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static void kinetis_qtd_print(struct kinetis_qtd_s *qtd); static void kinetis_qh_print(struct kinetis_qh_s *qh); -static int kinetis_qtd_dump(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg); -static int kinetis_qh_dump(struct kinetis_qh_s *qh, uint32_t **bp, void *arg); +static int kinetis_qtd_dump(struct kinetis_qtd_s *qtd, + uint32_t **bp, void *arg); +static int kinetis_qh_dump(struct kinetis_qh_s *qh, + uint32_t **bp, void *arg); #else # define kinetis_qtd_print(qtd) # define kinetis_qh_print(qh) @@ -495,13 +501,15 @@ static int kinetis_ioc_setup(struct kinetis_rhport_s *rhport, static int kinetis_ioc_wait(struct kinetis_epinfo_s *epinfo); static void kinetis_qh_enqueue(struct kinetis_qh_s *qhead, struct kinetis_qh_s *qh); -static struct kinetis_qh_s *kinetis_qh_create(struct kinetis_rhport_s *rhport, +static struct +kinetis_qh_s *kinetis_qh_create(struct kinetis_rhport_s *rhport, struct kinetis_epinfo_s *epinfo); static int kinetis_qtd_addbpl(struct kinetis_qtd_s *qtd, const void *buffer, size_t buflen); static struct kinetis_qtd_s *kinetis_qtd_setupphase( struct kinetis_epinfo_s *epinfo, const struct usb_ctrlreq_s *req); -static struct kinetis_qtd_s *kinetis_qtd_dataphase(struct kinetis_epinfo_s *epinfo, +static struct +kinetis_qtd_s *kinetis_qtd_dataphase(struct kinetis_epinfo_s *epinfo, void *buffer, int buflen, uint32_t tokenbits); static struct kinetis_qtd_s *kinetis_qtd_statusphase(uint32_t tokenbits); static ssize_t kinetiskinetis_virtramaddr_async_setup( @@ -519,7 +527,7 @@ static inline int kinetis_ioc_async_setup(struct kinetis_rhport_s *rhport, static void kinetis_asynch_completion(struct kinetis_epinfo_s *epinfo); #endif -/* Interrupt Handling ***************************************************************/ +/* Interrupt Handling *******************************************************/ static int kinetis_qtd_ioccheck(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg); @@ -528,16 +536,18 @@ static int kinetis_qh_ioccheck(struct kinetis_qh_s *qh, uint32_t **bp, #ifdef CONFIG_USBHOST_ASYNCH static int kinetis_qtd_cancel(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg); -static int kinetis_qh_cancel(struct kinetis_qh_s *qh, uint32_t **bp, void *arg); +static int kinetis_qh_cancel(struct kinetis_qh_s *qh, + uint32_t **bp, void *arg); #endif static inline void kinetis_ioc_bottomhalf(void); static inline void kinetis_portsc_bottomhalf(void); static inline void kinetis_syserr_bottomhalf(void); static inline void kinetis_async_advance_bottomhalf(void); static void kinetis_ehci_bottomhalf(FAR void *arg); -static int kinetis_ehci_interrupt(int irq, FAR void *context, FAR void *arg); +static int kinetis_ehci_interrupt(int irq, + FAR void *context, FAR void *arg); -/* USB Host Controller Operations ***************************************************/ +/* USB Host Controller Operations *******************************************/ static int kinetis_wait(FAR struct usbhost_connection_s *conn, FAR struct usbhost_hubport_s **hport); @@ -551,7 +561,8 @@ static int kinetis_ep0configure(FAR struct usbhost_driver_s *drvr, uint16_t maxpacketsize); static int kinetis_epalloc(FAR struct usbhost_driver_s *drvr, const FAR struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int kinetis_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int kinetis_epfree(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep); static int kinetis_alloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer, FAR size_t *maxlen); static int kinetis_free(FAR struct usbhost_driver_s *drvr, @@ -560,18 +571,26 @@ static int kinetis_ioalloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer, size_t buflen); static int kinetis_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer); -static int kinetis_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - FAR const struct usb_ctrlreq_s *req, FAR uint8_t *buffer); -static int kinetis_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - FAR const struct usb_ctrlreq_s *req, FAR const uint8_t *buffer); +static int kinetis_ctrlin(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR uint8_t *buffer); +static int kinetis_ctrlout(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR const uint8_t *buffer); static ssize_t kinetis_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, FAR uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static int kinetis_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, - FAR uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, - FAR void *arg); +static int kinetis_asynch(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep, + FAR uint8_t *buffer, + size_t buflen, + usbhost_asynch_t callback, + FAR void *arg); #endif -static int kinetis_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int kinetis_cancel(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep); #ifdef CONFIG_USBHOST_HUB static int kinetis_connect(FAR struct usbhost_driver_s *drvr, FAR struct usbhost_hubport_s *hport, bool connected); @@ -579,13 +598,13 @@ static int kinetis_connect(FAR struct usbhost_driver_s *drvr, static void kinetis_disconnect(FAR struct usbhost_driver_s *drvr, FAR struct usbhost_hubport_s *hport); -/* Initialization *******************************************************************/ +/* Initialization ***********************************************************/ static int kinetis_reset(void); -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* In this driver implementation, support is provided for only a single * USB device. All status information can be simply retained in a @@ -775,17 +794,17 @@ static const struct kinetis_ehci_trace_s g_trace2[TRACE2_NSTRINGS] = }; #endif /* HAVE_USBHOST_TRACE */ -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_read16 * * Description: * Read 16-bit little endian data * - ************************************************************************************/ + ****************************************************************************/ static uint16_t kinetis_read16(const uint8_t *addr) { @@ -796,13 +815,13 @@ static uint16_t kinetis_read16(const uint8_t *addr) #endif } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_read32 * * Description: * Read 32-bit little endian data * - ************************************************************************************/ + ****************************************************************************/ static inline uint32_t kinetis_read32(const uint8_t *addr) { @@ -815,13 +834,13 @@ static inline uint32_t kinetis_read32(const uint8_t *addr) #endif } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_write16 * * Description: * Write 16-bit little endian data * - ************************************************************************************/ + ****************************************************************************/ #if 0 /* Not used */ static void kinetis_write16(uint16_t memval, uint8_t *addr) @@ -836,13 +855,13 @@ static void kinetis_write16(uint16_t memval, uint8_t *addr) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_write32 * * Description: * Write 32-bit little endian data * - ************************************************************************************/ + ****************************************************************************/ #if 0 /* Not used */ static void kinetis_write32(uint32_t memval, uint8_t *addr) @@ -857,13 +876,13 @@ static void kinetis_write32(uint32_t memval, uint8_t *addr) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_swap16 * * Description: * Swap bytes on a 16-bit value * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_ENDIAN_BIG static uint16_t kinetis_swap16(uint16_t value) @@ -872,13 +891,13 @@ static uint16_t kinetis_swap16(uint16_t value) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_swap32 * * Description: * Swap bytes on a 32-bit value * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_ENDIAN_BIG static uint32_t kinetis_swap32(uint32_t value) @@ -888,13 +907,13 @@ static uint32_t kinetis_swap32(uint32_t value) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_printreg * * Description: * Print the contents of a KINETIS EHCI register * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static void kinetis_printreg(volatile uint32_t *regaddr, uint32_t regval, @@ -904,14 +923,14 @@ static void kinetis_printreg(volatile uint32_t *regaddr, uint32_t regval, } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_checkreg * * Description: - * Check if it is time to output debug information for accesses to a KINETIS - * EHCI register + * Check if it is time to output debug information for accesses to a + * KINETIS EHCI register * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static void kinetis_checkreg(volatile uint32_t *regaddr, uint32_t regval, @@ -970,13 +989,13 @@ static void kinetis_checkreg(volatile uint32_t *regaddr, uint32_t regval, } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_getreg * * Description: * Get the contents of an KINETIS register * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static uint32_t kinetis_getreg(volatile uint32_t *regaddr) @@ -997,13 +1016,13 @@ static inline uint32_t kinetis_getreg(volatile uint32_t *regaddr) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_putreg * * Description: * Set the contents of an KINETIS register to a value * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static void kinetis_putreg(uint32_t regval, volatile uint32_t *regaddr) @@ -1017,13 +1036,14 @@ static void kinetis_putreg(uint32_t regval, volatile uint32_t *regaddr) *regaddr = regval; } #else -static inline void kinetis_putreg(uint32_t regval, volatile uint32_t *regaddr) +static inline void kinetis_putreg(uint32_t regval, + volatile uint32_t *regaddr) { *regaddr = regval; } #endif -/************************************************************************************ +/**************************************************************************** * Name: ehci_wait_usbsts * * Description: @@ -1031,7 +1051,7 @@ static inline void kinetis_putreg(uint32_t regval, volatile uint32_t *regaddr) * value, (2) for a timeout to occur, or (3) a error to occur. Return * a value to indicate which terminated the wait. * - ************************************************************************************/ + ****************************************************************************/ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits, unsigned int delay) @@ -1073,21 +1093,21 @@ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits, return (regval == donebits) ? OK : -ETIMEDOUT; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_takesem * * Description: * This is just a wrapper to handle the annoying behavior of semaphore * waits that return due to the receipt of a signal. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_takesem(sem_t *sem) { return nxsem_wait_uninterruptible(sem); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_takesem_noncancelable * * Description: @@ -1095,7 +1115,7 @@ static int kinetis_takesem(sem_t *sem) * waits that return due to the receipt of a signal. This version also * ignores attempts to cancel the thread. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_takesem_noncancelable(sem_t *sem) { @@ -1121,7 +1141,7 @@ static int kinetis_takesem_noncancelable(sem_t *sem) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_alloc * * Description: @@ -1129,7 +1149,7 @@ static int kinetis_takesem_noncancelable(sem_t *sem) * * Assumption: Caller holds the exclsem * - ************************************************************************************/ + ****************************************************************************/ static struct kinetis_qh_s *kinetis_qh_alloc(void) { @@ -1147,15 +1167,16 @@ static struct kinetis_qh_s *kinetis_qh_alloc(void) return qh; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_aawait * * Description: - * Let a Queue Head (QH) structure wait for free by adding it to the aawait list + * Let a Queue Head (QH) structure wait for free by adding it to the + * aawait list * * Assumption: Caller holds the exclsem * - ************************************************************************************/ + ****************************************************************************/ static void kinetis_qh_aawait(struct kinetis_qh_s *qh) { @@ -1170,7 +1191,7 @@ static void kinetis_qh_aawait(struct kinetis_qh_s *qh) kinetis_putreg(regval | EHCI_USBCMD_IAADB, &HCOR->usbcmd); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_free * * Description: @@ -1178,7 +1199,7 @@ static void kinetis_qh_aawait(struct kinetis_qh_s *qh) * * Assumption: Caller holds the exclsem * - ************************************************************************************/ + ****************************************************************************/ static void kinetis_qh_free(struct kinetis_qh_s *qh) { @@ -1188,7 +1209,7 @@ static void kinetis_qh_free(struct kinetis_qh_s *qh) g_ehci.qhfree = qh; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_alloc * * Description: @@ -1197,7 +1218,7 @@ static void kinetis_qh_free(struct kinetis_qh_s *qh) * * Assumption: Caller holds the exclsem * - ************************************************************************************/ + ****************************************************************************/ static struct kinetis_qtd_s *kinetis_qtd_alloc(void) { @@ -1215,7 +1236,7 @@ static struct kinetis_qtd_s *kinetis_qtd_alloc(void) return qtd; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_free * * Description: @@ -1225,7 +1246,7 @@ static struct kinetis_qtd_s *kinetis_qtd_alloc(void) * Assumption: * Caller holds the exclsem * - ************************************************************************************/ + ****************************************************************************/ static void kinetis_qtd_free(struct kinetis_qtd_s *qtd) { @@ -1237,7 +1258,7 @@ static void kinetis_qtd_free(struct kinetis_qtd_s *qtd) g_ehci.qtdfree = entry; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_foreach * * Description: @@ -1245,7 +1266,7 @@ static void kinetis_qtd_free(struct kinetis_qtd_s *qtd) * handler for each QH structure in the list (including the one at the head * of the list). * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_qh_foreach(struct kinetis_qh_s *qh, uint32_t **bp, foreach_qh_t handler, void *arg) @@ -1319,17 +1340,18 @@ static int kinetis_qh_foreach(struct kinetis_qh_s *qh, uint32_t **bp, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_foreach * * Description: * Give a Queue Head (QH) instance, call the handler for each qTD structure * in the queue. * - ************************************************************************************/ + ****************************************************************************/ -static int kinetis_qtd_foreach(struct kinetis_qh_s *qh, foreach_qtd_t handler, - void *arg) +static int kinetis_qtd_foreach(struct kinetis_qh_s *qh, + foreach_qtd_t handler, + void *arg) { struct kinetis_qtd_s *qtd; struct kinetis_qtd_s *next; @@ -1401,14 +1423,14 @@ static int kinetis_qtd_foreach(struct kinetis_qh_s *qh, foreach_qtd_t handler, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_discard * * Description: * This is a kinetis_qtd_foreach callback. It simply unlinks the QTD, * updates the back pointer, and frees the QTD structure. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_qtd_discard(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg) @@ -1428,7 +1450,7 @@ static int kinetis_qtd_discard(struct kinetis_qtd_s *qtd, uint32_t **bp, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_discard * * Description: @@ -1438,7 +1460,7 @@ static int kinetis_qtd_discard(struct kinetis_qtd_s *qtd, uint32_t **bp, * The QH structure itself has already been unlinked from whatever list it * may have been in. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_qh_discard(struct kinetis_qh_s *qh) { @@ -1460,14 +1482,14 @@ static int kinetis_qh_discard(struct kinetis_qh_s *qh) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_invalidate * * Description: * This is a callback from kinetis_qtd_foreach. It simply invalidates D- * cache for address range of the qTD entry. * - ************************************************************************************/ + ****************************************************************************/ #if 0 /* Not used */ static int kinetis_qtd_invalidate(struct kinetis_qtd_s *qtd, uint32_t **bp, @@ -1483,13 +1505,13 @@ static int kinetis_qtd_invalidate(struct kinetis_qtd_s *qtd, uint32_t **bp, } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_invalidate * * Description: * Invalidate the Queue Head and all qTD entries in the queue. * - ************************************************************************************/ + ****************************************************************************/ #if 0 /* Not used */ static int kinetis_qh_invalidate(struct kinetis_qh_s *qh) @@ -1505,16 +1527,17 @@ static int kinetis_qh_invalidate(struct kinetis_qh_s *qh) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_flush * * Description: * This is a callback from kinetis_qtd_foreach. It simply flushes D-cache * for address range of the qTD entry. * - ************************************************************************************/ + ****************************************************************************/ -static int kinetis_qtd_flush(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg) +static int kinetis_qtd_flush(struct kinetis_qtd_s *qtd, + uint32_t **bp, void *arg) { /* Flush the D-Cache, i.e., make the contents of the memory match the * contents of the D-Cache in the specified address range and invalidate @@ -1527,13 +1550,13 @@ static int kinetis_qtd_flush(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_flush * * Description: * Invalidate the Queue Head and all qTD entries in the queue. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_qh_flush(struct kinetis_qh_s *qh) { @@ -1550,13 +1573,13 @@ static int kinetis_qh_flush(struct kinetis_qh_s *qh) return kinetis_qtd_foreach(qh, kinetis_qtd_flush, NULL); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_print * * Description: * Print the context of one qTD * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static void kinetis_qtd_print(struct kinetis_qtd_s *qtd) @@ -1571,13 +1594,13 @@ static void kinetis_qtd_print(struct kinetis_qtd_s *qtd) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_print * * Description: * Print the context of one QH * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static void kinetis_qh_print(struct kinetis_qh_s *qh) @@ -1613,31 +1636,32 @@ static void kinetis_qh_print(struct kinetis_qh_s *qh) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_dump * * Description: - * This is a kinetis_qtd_foreach callout function. It dumps the context of - * one qTD + * This is a kinetis_qtd_foreach callout function. It dumps the context + * of one qTD * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG -static int kinetis_qtd_dump(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg) +static int kinetis_qtd_dump(struct kinetis_qtd_s *qtd, + uint32_t **bp, void *arg) { kinetis_qtd_print(qtd); return OK; } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_dump * * Description: * This is a kinetis_qh_foreach call-out function. It dumps a QH structure * and all of the qTD structures linked to the QH. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_KINETIS_EHCI_REGDEBUG static int kinetis_qh_dump(struct kinetis_qh_s *qh, uint32_t **bp, void *arg) @@ -1647,14 +1671,14 @@ static int kinetis_qh_dump(struct kinetis_qh_s *qh, uint32_t **bp, void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ehci_speed * * Description: * Map a speed enumeration value per Chapter 9 of the USB specification to * the speed enumeration required in the EHCI queue head. * - ************************************************************************************/ + ****************************************************************************/ static inline uint8_t kinetis_ehci_speed(uint8_t usbspeed) { @@ -1662,7 +1686,7 @@ static inline uint8_t kinetis_ehci_speed(uint8_t usbspeed) return g_ehci_speed[usbspeed]; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ioc_setup * * Description: @@ -1673,7 +1697,7 @@ static inline uint8_t kinetis_ehci_speed(uint8_t usbspeed) * * Assumption: The caller holds the EHCI exclsem * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_ioc_setup(struct kinetis_rhport_s *rhport, struct kinetis_epinfo_s *epinfo) @@ -1711,7 +1735,7 @@ static int kinetis_ioc_setup(struct kinetis_rhport_s *rhport, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ioc_wait * * Description: @@ -1721,7 +1745,7 @@ static int kinetis_ioc_setup(struct kinetis_rhport_s *rhport, * cause a deadlock when the bottom-half, worker thread needs to take the * semaphore. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_ioc_wait(struct kinetis_epinfo_s *epinfo) { @@ -1743,7 +1767,7 @@ static int kinetis_ioc_wait(struct kinetis_epinfo_s *epinfo) return ret < 0 ? ret : epinfo->result; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_enqueue * * Description: @@ -1751,9 +1775,10 @@ static int kinetis_ioc_wait(struct kinetis_epinfo_s *epinfo) * * Assumptions: The caller holds the EHCI exclsem * - ************************************************************************************/ + ****************************************************************************/ -static void kinetis_qh_enqueue(struct kinetis_qh_s *qhead, struct kinetis_qh_s *qh) +static void kinetis_qh_enqueue(struct kinetis_qh_s *qhead, + struct kinetis_qh_s *qh) { uintptr_t physaddr; @@ -1785,16 +1810,17 @@ static void kinetis_qh_enqueue(struct kinetis_qh_s *qhead, struct kinetis_qh_s * (uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s)); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_create * * Description: * Create a new Queue Head (QH) * - ************************************************************************************/ + ****************************************************************************/ -static struct kinetis_qh_s *kinetis_qh_create(struct kinetis_rhport_s *rhport, - struct kinetis_epinfo_s *epinfo) +static struct +kinetis_qh_s *kinetis_qh_create(struct kinetis_rhport_s *rhport, + struct kinetis_epinfo_s *epinfo) { struct kinetis_qh_s *qh; uint32_t rhpndx; @@ -1923,13 +1949,13 @@ static struct kinetis_qh_s *kinetis_qh_create(struct kinetis_rhport_s *rhport, return qh; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_addbpl * * Description: * Add a buffer pointer list to a qTD. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_qtd_addbpl(struct kinetis_qtd_s *qtd, const void *buffer, size_t buflen) @@ -1999,13 +2025,13 @@ static int kinetis_qtd_addbpl(struct kinetis_qtd_s *qtd, const void *buffer, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_setupphase * * Description: * Create a SETUP phase request qTD. * - ************************************************************************************/ + ****************************************************************************/ static struct kinetis_qtd_s * kinetis_qtd_setupphase(struct kinetis_epinfo_s *epinfo, @@ -2067,17 +2093,18 @@ static struct kinetis_qtd_s * return qtd; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_dataphase * * Description: * Create a data transfer or SET data phase qTD. * - ************************************************************************************/ + ****************************************************************************/ -static struct kinetis_qtd_s *kinetis_qtd_dataphase(struct kinetis_epinfo_s *epinfo, - void *buffer, int buflen, - uint32_t tokenbits) +static struct +kinetis_qtd_s *kinetis_qtd_dataphase(struct kinetis_epinfo_s *epinfo, + void *buffer, int buflen, + uint32_t tokenbits) { struct kinetis_qtd_s *qtd; uint32_t regval; @@ -2135,13 +2162,13 @@ static struct kinetis_qtd_s *kinetis_qtd_dataphase(struct kinetis_epinfo_s *epin return qtd; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_statusphase * * Description: * Create a STATUS phase request qTD. * - ************************************************************************************/ + ****************************************************************************/ static struct kinetis_qtd_s *kinetis_qtd_statusphase(uint32_t tokenbits) { @@ -2184,7 +2211,7 @@ static struct kinetis_qtd_s *kinetis_qtd_statusphase(uint32_t tokenbits) return qtd; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_async_setup * * Description: @@ -2202,7 +2229,7 @@ static struct kinetis_qtd_s *kinetis_qtd_statusphase(uint32_t tokenbits) * Zero (OK) is returned on success; a negated errno value is return on * any failure. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_async_setup(struct kinetis_rhport_s *rhport, struct kinetis_epinfo_s *epinfo, @@ -2399,7 +2426,9 @@ static int kinetis_async_setup(struct kinetis_rhport_s *rhport, tokenbits |= QTD_TOKEN_PID_IN; } - /* Allocate a new Queue Element Transfer Descriptor (qTD) for the status */ + /* Allocate a new Queue Element Transfer Descriptor (qTD) for the + * status + */ qtd = kinetis_qtd_statusphase(tokenbits); if (qtd == NULL) @@ -2436,7 +2465,7 @@ errout_with_qh: return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_intr_setup * * Description: @@ -2483,7 +2512,7 @@ errout_with_qh: * Zero (OK) is returned on success; a negated errno value is return on * any failure. * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_USBHOST_INT_DISABLE static int kinetis_intr_setup(struct kinetis_rhport_s *rhport, @@ -2575,7 +2604,7 @@ errout_with_qh: } #endif /* CONFIG_USBHOST_INT_DISABLE */ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_transfer_wait * * Description: @@ -2593,7 +2622,7 @@ errout_with_qh: * bulk transfers, this will be the number of data bytes transfers (which * could be short). * - ************************************************************************************/ + ****************************************************************************/ static ssize_t kinetis_transfer_wait(struct kinetis_epinfo_s *epinfo) { @@ -2664,7 +2693,7 @@ static ssize_t kinetis_transfer_wait(struct kinetis_epinfo_s *epinfo) return epinfo->xfrd; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ioc_async_setup * * Description: @@ -2682,7 +2711,7 @@ static ssize_t kinetis_transfer_wait(struct kinetis_epinfo_s *epinfo) * Assumptions: * - Called from the interrupt level * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH static inline int kinetis_ioc_async_setup(struct kinetis_rhport_s *rhport, @@ -2719,7 +2748,7 @@ static inline int kinetis_ioc_async_setup(struct kinetis_rhport_s *rhport, } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_asynch_completion * * Description: @@ -2736,7 +2765,7 @@ static inline int kinetis_ioc_async_setup(struct kinetis_rhport_s *rhport, * Assumptions: * - Called from the interrupt level * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH static void kinetis_asynch_completion(struct kinetis_epinfo_s *epinfo) @@ -2774,7 +2803,7 @@ static void kinetis_asynch_completion(struct kinetis_epinfo_s *epinfo) } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_ioccheck * * Description: @@ -2782,7 +2811,7 @@ static void kinetis_asynch_completion(struct kinetis_epinfo_s *epinfo) * one qTD in the asynchronous queue. It removes all of the qTD * structures that are no longer active. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_qtd_ioccheck(struct kinetis_qtd_s *qtd, uint32_t **bp, void *arg) @@ -2822,7 +2851,7 @@ static int kinetis_qtd_ioccheck(struct kinetis_qtd_s *qtd, uint32_t **bp, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_ioccheck * * Description: @@ -2831,9 +2860,10 @@ static int kinetis_qtd_ioccheck(struct kinetis_qtd_s *qtd, uint32_t **bp, * and remove all of the structures that are no longer active. if all of * the qTD structures are removed, then QH itself will also be removed. * - ************************************************************************************/ + ****************************************************************************/ -static int kinetis_qh_ioccheck(struct kinetis_qh_s *qh, uint32_t **bp, void *arg) +static int kinetis_qh_ioccheck(struct kinetis_qh_s *qh, + uint32_t **bp, void *arg) { struct kinetis_epinfo_s *epinfo; uint32_t token; @@ -2986,14 +3016,14 @@ static int kinetis_qh_ioccheck(struct kinetis_qh_s *qh, uint32_t **bp, void *arg return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qtd_cancel * * Description: * This function is a kinetis_qtd_foreach() callback function. It removes * each qTD attached to a QH. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH static int kinetis_qtd_cancel(struct kinetis_qtd_s *qtd, uint32_t **bp, @@ -3026,7 +3056,7 @@ static int kinetis_qtd_cancel(struct kinetis_qtd_s *qtd, uint32_t **bp, } #endif /* CONFIG_USBHOST_ASYNCH */ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_qh_cancel * * Description: @@ -3035,10 +3065,11 @@ static int kinetis_qtd_cancel(struct kinetis_qtd_s *qtd, uint32_t **bp, * structures and remove all of the structures that are no longer active. * Then QH itself will also be removed. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int kinetis_qh_cancel(struct kinetis_qh_s *qh, uint32_t **bp, void *arg) +static int kinetis_qh_cancel(struct kinetis_qh_s *qh, + uint32_t **bp, void *arg) { struct kinetis_epinfo_s *epinfo = (struct kinetis_epinfo_s *)arg; uint32_t regval; @@ -3102,7 +3133,7 @@ static int kinetis_qh_cancel(struct kinetis_qh_s *qh, uint32_t **bp, void *arg) } #endif /* CONFIG_USBHOST_ASYNCH */ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ioc_bottomhalf * * Description: @@ -3118,7 +3149,7 @@ static int kinetis_qh_cancel(struct kinetis_qh_s *qh, uint32_t **bp, void *arg) * * Assumptions: The caller holds the EHCI exclsem * - ************************************************************************************/ + ****************************************************************************/ static inline void kinetis_ioc_bottomhalf(void) { @@ -3190,7 +3221,7 @@ static inline void kinetis_ioc_bottomhalf(void) #endif } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_portsc_bottomhalf * * Description: @@ -3210,7 +3241,7 @@ static inline void kinetis_ioc_bottomhalf(void) * change bits (including: Force port resume, over-current change, * enable/disable change and connect status change)." * - ************************************************************************************/ + ****************************************************************************/ static inline void kinetis_portsc_bottomhalf(void) { @@ -3325,7 +3356,7 @@ static inline void kinetis_portsc_bottomhalf(void) } } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_syserr_bottomhalf * * Description: @@ -3336,7 +3367,7 @@ static inline void kinetis_portsc_bottomhalf(void) * When this error occurs, the Host Controller clears the Run/Stop bit in * the Command register to prevent further execution of the scheduled TDs." * - ************************************************************************************/ + ****************************************************************************/ static inline void kinetis_syserr_bottomhalf(void) { @@ -3344,7 +3375,7 @@ static inline void kinetis_syserr_bottomhalf(void) DEBUGPANIC(); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_async_advance_bottomhalf * * Description: @@ -3356,7 +3387,7 @@ static inline void kinetis_syserr_bottomhalf(void) * USBCMD register. This status bit indicates the assertion of that * interrupt source." * - ************************************************************************************/ + ****************************************************************************/ static inline void kinetis_async_advance_bottomhalf(void) { @@ -3371,13 +3402,13 @@ static inline void kinetis_async_advance_bottomhalf(void) } } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ehci_bottomhalf * * Description: * EHCI "Bottom Half" interrupt handler. Runs on a work queue thread. * - ************************************************************************************/ + ****************************************************************************/ static void kinetis_ehci_bottomhalf(FAR void *arg) { @@ -3514,13 +3545,13 @@ static void kinetis_ehci_bottomhalf(FAR void *arg) kinetis_putreg(EHCI_HANDLED_INTS, &HCOR->usbintr); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ehci_interrupt * * Description: * EHCI "Top Half" interrupt handler * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_ehci_interrupt(int irq, FAR void *context, FAR void *arg) { @@ -3566,7 +3597,7 @@ static int kinetis_ehci_interrupt(int irq, FAR void *context, FAR void *arg) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_wait * * Description: @@ -3589,7 +3620,7 @@ static int kinetis_ehci_interrupt(int irq, FAR void *context, FAR void *arg) * - Called from a single thread so no mutual exclusion is required. * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_wait(FAR struct usbhost_connection_s *conn, FAR struct usbhost_hubport_s **hport) @@ -3666,7 +3697,7 @@ static int kinetis_wait(FAR struct usbhost_connection_s *conn, } } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_enumerate * * Description: @@ -3692,7 +3723,7 @@ static int kinetis_wait(FAR struct usbhost_connection_s *conn, * Assumptions: * This function will *not* be called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_rh_enumerate(FAR struct usbhost_connection_s *conn, FAR struct usbhost_hubport_s *hport) @@ -3953,7 +3984,7 @@ static int kinetis_enumerate(FAR struct usbhost_connection_s *conn, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ep0configure * * Description: @@ -3978,7 +4009,7 @@ static int kinetis_enumerate(FAR struct usbhost_connection_s *conn, * Assumptions: * This function will *not* be called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, @@ -4006,7 +4037,7 @@ static int kinetis_ep0configure(FAR struct usbhost_driver_s *drvr, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_epalloc * * Description: @@ -4026,7 +4057,7 @@ static int kinetis_ep0configure(FAR struct usbhost_driver_s *drvr, * Assumptions: * This function will *not* be called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_epalloc(FAR struct usbhost_driver_s *drvr, const FAR struct usbhost_epdesc_s *epdesc, @@ -4094,7 +4125,7 @@ static int kinetis_epalloc(FAR struct usbhost_driver_s *drvr, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_epfree * * Description: @@ -4112,7 +4143,7 @@ static int kinetis_epalloc(FAR struct usbhost_driver_s *drvr, * Assumptions: * This function will *not* be called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { @@ -4128,7 +4159,7 @@ static int kinetis_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_alloc * * Description: @@ -4159,7 +4190,7 @@ static int kinetis_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) * - Called from a single thread so no mutual exclusion is required. * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_alloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer, FAR size_t *maxlen) @@ -4183,7 +4214,7 @@ static int kinetis_alloc(FAR struct usbhost_driver_s *drvr, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_free * * Description: @@ -4205,19 +4236,22 @@ static int kinetis_alloc(FAR struct usbhost_driver_s *drvr, * Assumptions: * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ -static int kinetis_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) +static int kinetis_free(FAR struct usbhost_driver_s *drvr, + FAR uint8_t *buffer) { DEBUGASSERT(drvr && buffer); - /* No special action is require to free the transfer/descriptor buffer memory */ + /* No special action is require to free the transfer/descriptor buffer + * memory + */ kmm_free(buffer); return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ioalloc * * Description: @@ -4244,7 +4278,7 @@ static int kinetis_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) * Assumptions: * This function will *not* be called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_ioalloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer, size_t buflen) @@ -4262,7 +4296,7 @@ static int kinetis_ioalloc(FAR struct usbhost_driver_s *drvr, return *buffer ? OK : -ENOMEM; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_iofree * * Description: @@ -4283,7 +4317,7 @@ static int kinetis_ioalloc(FAR struct usbhost_driver_s *drvr, * Assumptions: * This function will *not* be called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) @@ -4296,7 +4330,7 @@ static int kinetis_iofree(FAR struct usbhost_driver_s *drvr, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ctrlin and kinetis_ctrlout * * Description: @@ -4330,11 +4364,12 @@ static int kinetis_iofree(FAR struct usbhost_driver_s *drvr, * - Called from a single thread so no mutual exclusion is required. * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ -static int kinetis_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - FAR const struct usb_ctrlreq_s *req, - FAR uint8_t *buffer) +static int kinetis_ctrlin(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR uint8_t *buffer) { struct kinetis_rhport_s *rhport = (struct kinetis_rhport_s *)drvr; struct kinetis_epinfo_s *ep0info = (struct kinetis_epinfo_s *)ep0; @@ -4357,7 +4392,9 @@ static int kinetis_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, req->index[1], req->index[0], len); #endif - /* We must have exclusive access to the EHCI hardware and data structures. */ + /* We must have exclusive access to the EHCI hardware and data + * structures. + */ ret = kinetis_takesem(&g_ehci.exclsem); if (ret < 0) @@ -4396,9 +4433,10 @@ errout_with_sem: return ret; } -static int kinetis_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - FAR const struct usb_ctrlreq_s *req, - FAR const uint8_t *buffer) +static int kinetis_ctrlout(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR const uint8_t *buffer) { /* kinetis_ctrlin can handle both directions. We just need to work around * the differences in the function signatures. @@ -4407,7 +4445,7 @@ static int kinetis_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return kinetis_ctrlin(drvr, ep0, req, (uint8_t *)buffer); } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_transfer * * Description: @@ -4444,7 +4482,7 @@ static int kinetis_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, * - Called from a single thread so no mutual exclusion is required. * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static ssize_t kinetis_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, FAR uint8_t *buffer, @@ -4457,7 +4495,9 @@ static ssize_t kinetis_transfer(FAR struct usbhost_driver_s *drvr, DEBUGASSERT(rhport && epinfo && buffer && buflen > 0); - /* We must have exclusive access to the EHCI hardware and data structures. */ + /* We must have exclusive access to the EHCI hardware and data + * structures. + */ ret = kinetis_takesem(&g_ehci.exclsem); if (ret < 0) @@ -4520,7 +4560,7 @@ errout_with_sem: return (ssize_t)ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_asynch * * Description: @@ -4554,7 +4594,7 @@ errout_with_sem: * - Called from a single thread so no mutual exclusion is required. * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH static int kinetis_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, @@ -4567,7 +4607,9 @@ static int kinetis_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, DEBUGASSERT(rhport && epinfo && buffer && buflen > 0); - /* We must have exclusive access to the EHCI hardware and data structures. */ + /* We must have exclusive access to the EHCI hardware and data + * structures. + */ ret = kinetis_takesem(&g_ehci.exclsem); if (ret < 0) @@ -4630,7 +4672,7 @@ errout_with_sem: } #endif /* CONFIG_USBHOST_ASYNCH */ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_cancel * * Description: @@ -4647,7 +4689,7 @@ errout_with_sem: * On success, zero (OK) is returned. On a failure, a negated errno value * is returned indicating the nature of the failure * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { @@ -4832,7 +4874,7 @@ errout_with_sem: return ret; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_connect * * Description: @@ -4851,7 +4893,7 @@ errout_with_sem: * On success, zero (OK) is returned. On a failure, a negated errno value * is returned indicating the nature of the failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_USBHOST_HUB static int kinetis_connect(FAR struct usbhost_driver_s *drvr, @@ -4883,7 +4925,7 @@ static int kinetis_connect(FAR struct usbhost_driver_s *drvr, } #endif -/************************************************************************************ +/**************************************************************************** * Name: kinetis_disconnect * * Description: @@ -4907,7 +4949,7 @@ static int kinetis_connect(FAR struct usbhost_driver_s *drvr, * - Only a single class bound to a single device is supported. * - Never called from an interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ static void kinetis_disconnect(FAR struct usbhost_driver_s *drvr, FAR struct usbhost_hubport_s *hport) @@ -4916,7 +4958,7 @@ static void kinetis_disconnect(FAR struct usbhost_driver_s *drvr, hport->devclass = NULL; } -/************************************************************************************ +/**************************************************************************** * Name: kinetis_reset * * Description: @@ -4958,7 +5000,7 @@ static void kinetis_disconnect(FAR struct usbhost_driver_s *drvr, * Assumptions: * - Called during the initialization of the EHCI. * - ************************************************************************************/ + ****************************************************************************/ static int kinetis_reset(void) { @@ -5004,7 +5046,9 @@ static int kinetis_reset(void) return -ETIMEDOUT; } - /* Now we can set the HCReset bit in the USBCMD register to initiate the reset */ + /* Now we can set the HCReset bit in the USBCMD register to initiate the + * reset + */ regval = kinetis_getreg(&HCOR->usbcmd); regval |= EHCI_USBCMD_HCRESET; @@ -5033,11 +5077,11 @@ static int kinetis_reset(void) return (regval & EHCI_USBCMD_HCRESET) != 0 ? -ETIMEDOUT : OK; } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: kinetis_ehci_initialize * * Description: @@ -5060,7 +5104,7 @@ static int kinetis_reset(void) * - Class drivers should be initialized prior to calling this function. * Otherwise, there is a race condition if the device is already connected. * - ************************************************************************************/ + ****************************************************************************/ FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller) { @@ -5093,7 +5137,7 @@ FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller) # endif # endif /* CONFIG_USBHOST_INT_DISABLE */ - /* Software Configuration *********************************************************/ + /* Software Configuration *************************************************/ usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0); @@ -5383,7 +5427,9 @@ FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller) kinetis_putreg(regval, &HCOR->usbcmd); - /* Start the host controller by setting the RUN bit in the USBCMD register. */ + /* Start the host controller by setting the RUN bit in the + * USBCMD register. + */ regval = kinetis_getreg(&HCOR->usbcmd); regval |= EHCI_USBCMD_RUN; @@ -5404,7 +5450,7 @@ FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller) return NULL; } - /* Interrupt Configuration ********************************************************/ + /* Interrupt Configuration ************************************************/ ret = irq_attach(KINETIS_IRQ_USB1OTG, kinetis_ehci_interrupt, NULL); if (ret != 0) @@ -5453,7 +5499,7 @@ FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller) return &g_ehciconn; } -/************************************************************************************ +/**************************************************************************** * Name: usbhost_trformat1 and usbhost_trformat2 * * Description: @@ -5464,7 +5510,7 @@ FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller) * printf. The returned format is expected to handle two unsigned integer * values. * - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_USBHOST_TRACE FAR const char *usbhost_trformat1(uint16_t id) diff --git a/arch/arm/src/kinetis/kinetis_usbhshost.h b/arch/arm/src/kinetis/kinetis_usbhshost.h index 1c23dbe769..7d1c1e8e00 100644 --- a/arch/arm/src/kinetis/kinetis_usbhshost.h +++ b/arch/arm/src/kinetis/kinetis_usbhshost.h @@ -1,4 +1,4 @@ -/****************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/kinetis_usbhshost.h * * Copyright (C) 2012, 2015, 2019 Gregory Nutt. All rights reserved. @@ -32,31 +32,31 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ******************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBHSHOST_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_USBHSHOST_H -/****************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/****************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Public Types - ******************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/****************************************************************************** +/**************************************************************************** * Public Data - ******************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -67,16 +67,17 @@ extern "C" #define EXTERN extern #endif -/****************************************************************************** +/**************************************************************************** * Public Function Prototypes - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Name: kinetis_usbhost_vbusdrive * * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided - * by each platform that implements the OHCI or EHCI host interface + * Enable/disable driving of VBUS 5V output. This function must be + * provided by each platform that implements the OHCI or EHCI host + * interface * * Input Parameters: * rhport - Selects root hub port to be powered host interface. Since the @@ -87,16 +88,16 @@ extern "C" * Returned Value: * None * - ******************************************************************************/ + ****************************************************************************/ extern void kinetis_usbhost_vbusdrive(int rhport, bool enable); -/****************************************************************************** +/**************************************************************************** * Name: kinetis_setup_overcurrent * * Description: - * Setup to receive an interrupt-level callback if an over-current condition - * is detected. + * Setup to receive an interrupt-level callback if an over-current + * condition is detected. * * Input Parameters: * handler - New over-current interrupt handler @@ -106,11 +107,11 @@ extern void kinetis_usbhost_vbusdrive(int rhport, bool enable); * Zero (OK) returned on success; a negated errno value is returned on * failure. * - ******************************************************************************/ + ****************************************************************************/ extern int kinetis_setup_overcurrent(xcpt_t handler, void *arg); -/****************************************************************************** +/**************************************************************************** * Name: kinetis_ehci_initialize * * Description: @@ -133,7 +134,7 @@ extern int kinetis_setup_overcurrent(xcpt_t handler, void *arg); * - Class drivers should be initialized prior to calling this function. * Otherwise, there is a race condition if the device is already connected. * - ******************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_KINETIS_USBHS) && defined(CONFIG_USBHOST) struct usbhost_connection_s; diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h index fd6e87d92b..c01683464a 100644 --- a/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/kinetis/kinetis_usbotg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/kinetis_usbotg.h" -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -44,9 +44,9 @@ struct usbotg_bdtentry_s }; #endif -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ struct usbdev_s; int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable); diff --git a/arch/arm/src/kinetis/kinetis_userspace.h b/arch/arm/src/kinetis/kinetis_userspace.h index 8c0d676496..aabdebf738 100644 --- a/arch/arm/src/kinetis/kinetis_userspace.h +++ b/arch/arm/src/kinetis/kinetis_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,32 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USERSPACE_H #define __ARCH_ARM_SRC_KINETIS_KINETIS_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: kinetis_userspace