STM32 F7: Add FLASH and SYSCFG header files
This commit is contained in:
Gregory Nutt
parent
d5ebc0ae79
commit
fb129fa354
@ -63,10 +63,6 @@
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static xcpt_t stm32_exti_callbacks[16];
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -225,15 +221,16 @@ static int stm32_exti1510_isr(int irq, void *context)
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* Sets/clears GPIO based event and interrupt triggers.
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*
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* Parameters:
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* - pinset: gpio pin configuration
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* - rising/falling edge: enables
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* - event: generate event when set
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* - func: when non-NULL, generate interrupt
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* - pinset: GPIO pin configuration
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* - risingedge: Enables interrupt on rising edges
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* - fallingedge: Enables interrupt on falling edges
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* - event: Generate event when set
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* - func: When non-NULL, generate interrupt
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*
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* Returns:
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* The previous value of the interrupt handler function pointer. This value may,
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* for example, be used to restore the previous handler when multiple handlers are
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* used.
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* The previous value of the interrupt handler function pointer. This
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* value may, for example, be used to restore the previous handler when
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* multiple handlers are used.
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*
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****************************************************************************/
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@ -42,6 +42,18 @@ config STM32F7_STM32F75XX
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bool
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default n
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choice
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prompt "Embedded FLASH size"
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default STM32F7_FLASH_1024KB
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config STM32F7_FLASH_512KB
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bool "512 KB"
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config STM32F7_FLASH_1024KB
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bool "1024 KB"
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endchoice # Embedded FLASH size
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menu "STM32 Peripheral Support"
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# These "hidden" settings determine is a peripheral option is available for the
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52
arch/arm/src/stm32f7/chip/stm32_flash.h
Normal file
52
arch/arm/src/stm32f7/chip/stm32_flash.h
Normal file
@ -0,0 +1,52 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_flash.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_FLASH_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_FLASH_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_flash.h"
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#else
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# error "Unsupported STM32 F7 part"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_FLASH_H */
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52
arch/arm/src/stm32f7/chip/stm32_syscfg.h
Normal file
52
arch/arm/src/stm32f7/chip/stm32_syscfg.h
Normal file
@ -0,0 +1,52 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_syscfg.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SYSCFG_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SYSCFG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_syscfg.h"
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#else
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# error "Unsupported STM32 F7 part"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SYSCFG_H */
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184
arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
Normal file
184
arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
Normal file
@ -0,0 +1,184 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H
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#define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Flash size is not known from the chip configuration:
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*
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* Parts STM32F74xxE have 512Kb of FLASH
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* Parts STM32F74xxG have 1024Kb of FLASH
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*
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* The user has to tell us the FLASH size by setting CONFIG_STM32F7_FLASH_SIZE
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*/
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#if defined(CONFIG_STM32F7_FLASH_512KB)
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# define STM32_FLASH_NPAGES 2
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# define STM32_FLASH_SIZE (512*1024)
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#elif defined(CONFIG_STM32F7_FLASH_1024KB)
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# define STM32_FLASH_NPAGES 4
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# define STM32_FLASH_SIZE (1024*1024)
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#else
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# warning Assuming FLASH size 1024KB
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# define STM32_FLASH_NPAGES 4
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# define STM32_FLASH_SIZE (1024*1024)
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#endif
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/* The STM32F745xx/46xx have mixed page sizes:
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*
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* Sectors: 0-3: 32 KB
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* Sector 4 128 KB
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* Sectors: 5-7: 256 KB
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*
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* We use the largest page size and set the number of pages equal to the
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* FLASH size assuming that fixed, largest pages size.
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*/
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#define STM32_FLASH_PAGESIZE (256*1024)
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/* Register Offsets *****************************************************************/
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#define STM32_FLASH_ACR_OFFSET 0x0000
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#define STM32_FLASH_KEYR_OFFSET 0x0004
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#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
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#define STM32_FLASH_SR_OFFSET 0x000c
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#define STM32_FLASH_CR_OFFSET 0x0010
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#define STM32_FLASH_OPTCR_OFFSET 0x0014
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#define STM32_FLASH_OPTCR1_OFFSET 0x0018
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/* Register Addresses ***************************************************************/
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#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
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#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
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#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
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#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Flash Access Control Register (ACR) */
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#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */
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#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
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# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
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# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
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# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
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# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
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# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */
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# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */
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# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */
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# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */
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# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */
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#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
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#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */
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#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */
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/* Flash Status Register (SR) */
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#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
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#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
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#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
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#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
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#define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */
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#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
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#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
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/* Flash Control Register (CR) */
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#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
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#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
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#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
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#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
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#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
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# define FLASH_CR_SNB(n) ((uint32_t)(n) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
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#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
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#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
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# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
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# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */
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# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */
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# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */
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#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
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#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
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#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
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#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
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#define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
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/* Flash Option Control Register (OPTCR) */
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#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
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#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
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#define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */
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#define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT)
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# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 3 */
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# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */
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# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */
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# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */
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#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */
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#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT)
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# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 5: WWDG_SW */
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# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */
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# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */
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# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */
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#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */
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#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT)
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# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT)
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#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */
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#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
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# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT)
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#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */
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#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */
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/* Flash Option Control Register (OPTCR1) */
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#define FLASH_OPTCR1_BOOTADD0_SHIFT (0) /* Bits 0-15: Boot base address when Boot pin=0 */
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#define FLASH_OPTCR1_BOOTADD0_MASK (0xffff << FLASH_OPTCR1_BOOTADD0_SHIFT)
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# define FLASH_OPTCR1_BOOTADD0(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD0_SHIFT)
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#define FLASH_OPTCR1_BOOTADD1_SHIFT (16) /* Bits 16-31:Boot base address when Boot pin=1 */
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#define FLASH_OPTCR1_BOOTADD1_MASK (0xffff << FLASH_OPTCR1_BOOTADD1_SHIFT)
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# define FLASH_OPTCR1_BOOTADD1(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD1_SHIFT)
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#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H */
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159
arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h
Normal file
159
arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h
Normal file
@ -0,0 +1,159 @@
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/****************************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_MEMBOOT (1 << 0) /* Bit 0: Memory boot mapping */
|
||||
#define SYSCFG_MEMRMP_MEMBOOT_ADD0 (0 << 0) /* 0=BOOT_ADD0 defines */
|
||||
#define SYSCFG_MEMRMP_MEMBOOT_ADD1 (1 << 0) /* 1=BOOT_ADD1 defines */
|
||||
#define SYSCFG_MEMRMP_SWPFMC_SHIFT (10) /* Bits 10-11: FMC memory mapping swap */
|
||||
#define SYSCFG_MEMRMP_SWPFMC_MASK (3 << SYSCFG_MEMRMP_SWPFMC_SHIFT)
|
||||
# define SYSCFG_MEMRMP_SWPFMC_NONE (0 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* No FMC memory mapping swapping */
|
||||
# define SYSCFG_MEMRMP_SWPFMC_NORRAM (1 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* NOR/RAM and SDRAM memory mapping swapped */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */
|
||||
# define SYSCFG_PMC_MII_SEL (0 << 23) /* 0 selects MII */
|
||||
# define SYSCFG_PMC_RMII_SEL (1 << 23) /* 1 selects RMII */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTJ (9) /* 1001: PJ[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTK (10) /* 1010: PK[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
||||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SYSCFG_H */
|
||||
@ -1,4 +1,4 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_exti.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
@ -31,14 +31,14 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_EXTI_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
@ -47,9 +47,9 @@
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_exti.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@ -62,49 +62,51 @@ extern "C"
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: stm32_gpiosetevent
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
*
|
||||
* Parameters:
|
||||
* - pinset: gpio pin configuration
|
||||
* - rising/falling edge: enables
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - pinset: GPIO pin configuration
|
||||
* - risingedge: Enables interrupt on rising edges
|
||||
* - fallingedge: Enables interrupt on falling edges
|
||||
* - event: Generate event when set
|
||||
* - func: When non-NULL, generate interrupt
|
||||
*
|
||||
* Returns:
|
||||
* The previous value of the interrupt handler function pointer. This value may,
|
||||
* for example, be used to restore the previous handler when multiple handlers are
|
||||
* used.
|
||||
* The previous value of the interrupt handler function pointer. This
|
||||
* value may, for example, be used to restore the previous handler when
|
||||
* multiple handlers are used.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
bool event, xcpt_t func);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: stm32_exti_alarm
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears EXTI alarm interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* - rising/falling edge: enables interrupt on rising/falling edges
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - risingedge: Enables interrupt on rising edges
|
||||
* - fallingedge: Enables interrupt on falling edges
|
||||
* - event: Generate event when set
|
||||
* - func: When non-NULL, generate interrupt
|
||||
*
|
||||
* Returns:
|
||||
* The previous value of the interrupt handler function pointer. This value may,
|
||||
* for example, be used to restore the previous handler when multiple handlers are
|
||||
* used.
|
||||
* The previous value of the interrupt handler function pointer. This
|
||||
* value may, for example, be used to restore the previous handler when
|
||||
* multiple handlers are used.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
xcpt_t stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func);
|
||||
|
||||
@ -76,10 +76,6 @@
|
||||
static xcpt_t stm32_exti_callbacks[16];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
@ -237,15 +233,16 @@ static int stm32_exti1510_isr(int irq, void *context)
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
*
|
||||
* Parameters:
|
||||
* - pinset: gpio pin configuration
|
||||
* - rising/falling edge: enables
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - pinset: GPIO pin configuration
|
||||
* - risingedge: Enables interrupt on rising edges
|
||||
* - fallingedge: Enables interrupt on falling edges
|
||||
* - event: Generate event when set
|
||||
* - func: When non-NULL, generate interrupt
|
||||
*
|
||||
* Returns:
|
||||
* The previous value of the interrupt handler function pointer. This value may,
|
||||
* for example, be used to restore the previous handler when multiple handlers are
|
||||
* used.
|
||||
* The previous value of the interrupt handler function pointer. This
|
||||
* value may, for example, be used to restore the previous handler when
|
||||
* multiple handlers are used.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
@ -50,6 +50,7 @@
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip/stm32_syscfg.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/* Content of this file requires verification before it is used with other
|
||||
|
||||
@ -49,9 +49,8 @@
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_flash.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_flash.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user