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stm32l5: Coding style fixes

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Put blanks around the '+' in register address definitions.

Signed-off-by: Michael Jung <mijung@gmx.net>
This commit is contained in:
Michael Jung 2021-03-16 07:42:19 +01:00 committed by Xiang Xiao
parent 3581289661
commit fb14125320
10 changed files with 513 additions and 513 deletions
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80
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h
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@ -78,46 +78,46 @@
/* Register Addresses *******************************************************/
#define STM32L5_RCC_CR (STM32L5_RCC_BASE+STM32L5_RCC_CR_OFFSET)
#define STM32L5_RCC_ICSCR (STM32L5_RCC_BASE+STM32L5_RCC_ICSCR_OFFSET)
#define STM32L5_RCC_CFGR (STM32L5_RCC_BASE+STM32L5_RCC_CFGR_OFFSET)
#define STM32L5_RCC_PLLCFG (STM32L5_RCC_BASE+STM32L5_RCC_PLLCFG_OFFSET)
#define STM32L5_RCC_PLLSAI1CFG (STM32L5_RCC_BASE+STM32L5_RCC_PLLSAI1CFG_OFFSET)
#define STM32L5_RCC_PLLSAI2CFG (STM32L5_RCC_BASE+STM32L5_RCC_PLLSAI2CFG_OFFSET)
#define STM32L5_RCC_CIER (STM32L5_RCC_BASE+STM32L5_RCC_CIER_OFFSET)
#define STM32L5_RCC_CIFR (STM32L5_RCC_BASE+STM32L5_RCC_CIFR_OFFSET)
#define STM32L5_RCC_CICR (STM32L5_RCC_BASE+STM32L5_RCC_CICR_OFFSET)
#define STM32L5_RCC_AHB1RSTR (STM32L5_RCC_BASE+STM32L5_RCC_AHB1RSTR_OFFSET)
#define STM32L5_RCC_AHB2RSTR (STM32L5_RCC_BASE+STM32L5_RCC_AHB2RSTR_OFFSET)
#define STM32L5_RCC_AHB3RSTR (STM32L5_RCC_BASE+STM32L5_RCC_AHB3RSTR_OFFSET)
#define STM32L5_RCC_APB1RSTR1 (STM32L5_RCC_BASE+STM32L5_RCC_APB1RSTR1_OFFSET)
#define STM32L5_RCC_APB1RSTR2 (STM32L5_RCC_BASE+STM32L5_RCC_APB1RSTR2_OFFSET)
#define STM32L5_RCC_APB2RSTR (STM32L5_RCC_BASE+STM32L5_RCC_APB2RSTR_OFFSET)
#define STM32L5_RCC_AHB1ENR (STM32L5_RCC_BASE+STM32L5_RCC_AHB1ENR_OFFSET)
#define STM32L5_RCC_AHB2ENR (STM32L5_RCC_BASE+STM32L5_RCC_AHB2ENR_OFFSET)
#define STM32L5_RCC_AHB3ENR (STM32L5_RCC_BASE+STM32L5_RCC_AHB3ENR_OFFSET)
#define STM32L5_RCC_APB1ENR1 (STM32L5_RCC_BASE+STM32L5_RCC_APB1ENR1_OFFSET)
#define STM32L5_RCC_APB1ENR2 (STM32L5_RCC_BASE+STM32L5_RCC_APB1ENR2_OFFSET)
#define STM32L5_RCC_APB2ENR (STM32L5_RCC_BASE+STM32L5_RCC_APB2ENR_OFFSET)
#define STM32L5_RCC_AHB1SMENR (STM32L5_RCC_BASE+STM32L5_RCC_AHB1SMENR_OFFSET)
#define STM32L5_RCC_AHB2SMENR (STM32L5_RCC_BASE+STM32L5_RCC_AHB2SMENR_OFFSET)
#define STM32L5_RCC_AHB3SMENR (STM32L5_RCC_BASE+STM32L5_RCC_AHB3SMENR_OFFSET)
#define STM32L5_RCC_APB1SMENR1 (STM32L5_RCC_BASE+STM32L5_RCC_APB1SMENR1_OFFSET)
#define STM32L5_RCC_APB1SMENR2 (STM32L5_RCC_BASE+STM32L5_RCC_APB1SMENR2_OFFSET)
#define STM32L5_RCC_APB2SMENR (STM32L5_RCC_BASE+STM32L5_RCC_APB2SMENR_OFFSET)
#define STM32L5_RCC_CCIPR (STM32L5_RCC_BASE+STM32L5_RCC_CCIPR_OFFSET)
#define STM32L5_RCC_BDCR (STM32L5_RCC_BASE+STM32L5_RCC_BDCR_OFFSET)
#define STM32L5_RCC_CSR (STM32L5_RCC_BASE+STM32L5_RCC_CSR_OFFSET)
#define STM32L5_RCC_CRRCR (STM32L5_RCC_BASE+STM32L5_RCC_CRRCR_OFFSET)
#define STM32L5_RCC_CCIPR2 (STM32L5_RCC_BASE+STM32L5_RCC_CCIPR2_OFFSET)
#define STM32L5_RCC_SECCFGR (STM32L5_RCC_BASE+STM32L5_RCC_SECCFGR_OFFSET)
#define STM32L5_RCC_SECSR (STM32L5_RCC_BASE+STM32L5_RCC_SECSR_OFFSET)
#define STM32L5_RCC_AHB1SECSR (STM32L5_RCC_BASE+STM32L5_RCC_AHB1SECSR_OFFSET)
#define STM32L5_RCC_AHB2SECSR (STM32L5_RCC_BASE+STM32L5_RCC_AHB2SECSR_OFFSET)
#define STM32L5_RCC_AHB3SECSR (STM32L5_RCC_BASE+STM32L5_RCC_AHB3SECSR_OFFSET)
#define STM32L5_RCC_APB1SECSR1 (STM32L5_RCC_BASE+STM32L5_RCC_APB1SECSR1_OFFSET)
#define STM32L5_RCC_APB1SECSR2 (STM32L5_RCC_BASE+STM32L5_RCC_APB1SECSR2_OFFSET)
#define STM32L5_RCC_APB2SECSR (STM32L5_RCC_BASE+STM32L5_RCC_APB2SECSR_OFFSET)
#define STM32L5_RCC_CR (STM32L5_RCC_BASE + STM32L5_RCC_CR_OFFSET)
#define STM32L5_RCC_ICSCR (STM32L5_RCC_BASE + STM32L5_RCC_ICSCR_OFFSET)
#define STM32L5_RCC_CFGR (STM32L5_RCC_BASE + STM32L5_RCC_CFGR_OFFSET)
#define STM32L5_RCC_PLLCFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLCFG_OFFSET)
#define STM32L5_RCC_PLLSAI1CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI1CFG_OFFSET)
#define STM32L5_RCC_PLLSAI2CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI2CFG_OFFSET)
#define STM32L5_RCC_CIER (STM32L5_RCC_BASE + STM32L5_RCC_CIER_OFFSET)
#define STM32L5_RCC_CIFR (STM32L5_RCC_BASE + STM32L5_RCC_CIFR_OFFSET)
#define STM32L5_RCC_CICR (STM32L5_RCC_BASE + STM32L5_RCC_CICR_OFFSET)
#define STM32L5_RCC_AHB1RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1RSTR_OFFSET)
#define STM32L5_RCC_AHB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2RSTR_OFFSET)
#define STM32L5_RCC_AHB3RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3RSTR_OFFSET)
#define STM32L5_RCC_APB1RSTR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR1_OFFSET)
#define STM32L5_RCC_APB1RSTR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR2_OFFSET)
#define STM32L5_RCC_APB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_APB2RSTR_OFFSET)
#define STM32L5_RCC_AHB1ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1ENR_OFFSET)
#define STM32L5_RCC_AHB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2ENR_OFFSET)
#define STM32L5_RCC_AHB3ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3ENR_OFFSET)
#define STM32L5_RCC_APB1ENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR1_OFFSET)
#define STM32L5_RCC_APB1ENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR2_OFFSET)
#define STM32L5_RCC_APB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2ENR_OFFSET)
#define STM32L5_RCC_AHB1SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SMENR_OFFSET)
#define STM32L5_RCC_AHB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SMENR_OFFSET)
#define STM32L5_RCC_AHB3SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SMENR_OFFSET)
#define STM32L5_RCC_APB1SMENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR1_OFFSET)
#define STM32L5_RCC_APB1SMENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR2_OFFSET)
#define STM32L5_RCC_APB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SMENR_OFFSET)
#define STM32L5_RCC_CCIPR (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR_OFFSET)
#define STM32L5_RCC_BDCR (STM32L5_RCC_BASE + STM32L5_RCC_BDCR_OFFSET)
#define STM32L5_RCC_CSR (STM32L5_RCC_BASE + STM32L5_RCC_CSR_OFFSET)
#define STM32L5_RCC_CRRCR (STM32L5_RCC_BASE + STM32L5_RCC_CRRCR_OFFSET)
#define STM32L5_RCC_CCIPR2 (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR2_OFFSET)
#define STM32L5_RCC_SECCFGR (STM32L5_RCC_BASE + STM32L5_RCC_SECCFGR_OFFSET)
#define STM32L5_RCC_SECSR (STM32L5_RCC_BASE + STM32L5_RCC_SECSR_OFFSET)
#define STM32L5_RCC_AHB1SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SECSR_OFFSET)
#define STM32L5_RCC_AHB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SECSR_OFFSET)
#define STM32L5_RCC_AHB3SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SECSR_OFFSET)
#define STM32L5_RCC_APB1SECSR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR1_OFFSET)
#define STM32L5_RCC_APB1SECSR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR2_OFFSET)
#define STM32L5_RCC_APB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SECSR_OFFSET)
/* Register Bitfield Definitions ********************************************/

22
arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h
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@ -50,17 +50,17 @@
/* Register Addresses *******************************************************/
#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SECCFGR_OFFSET)
#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CFGR1_OFFSET)
#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_FPUIMR_OFFSET)
#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CNSLCKR_OFFSET)
#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CSLCKR_OFFSET)
#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CFGR2_OFFSET)
#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SCSR_OFFSET)
#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SKR_OFFSET)
#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SWPR_OFFSET)
#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SWPR2_OFFSET)
#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_RSSCMDR_OFFSET)
#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SECCFGR_OFFSET)
#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR1_OFFSET)
#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_FPUIMR_OFFSET)
#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CNSLCKR_OFFSET)
#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CSLCKR_OFFSET)
#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR2_OFFSET)
#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SCSR_OFFSET)
#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SKR_OFFSET)
#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR_OFFSET)
#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR2_OFFSET)
#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_RSSCMDR_OFFSET)
/* Register Bitfield Definitions ********************************************/

46
arch/arm/src/stm32l5/hardware/stm32l5_exti.h
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@ -60,29 +60,29 @@
/* Register Addresses *******************************************************/
#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_RTSR1_OFFSET)
#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_FTSR1_OFFSET)
#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE+STM32L5_EXTI_SWIER1_OFFSET)
#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_RPR1_OFFSET)
#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_FPR1_OFFSET)
#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_SECCFGR1_OFFSET)
#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_PRIVCFGR1_OFFSET)
#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_RTSR2_OFFSET)
#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_FTSR2_OFFSET)
#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE+STM32L5_EXTI_SWIER2_OFFSET)
#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_RPR2_OFFSET)
#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_FPR2_OFFSET)
#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_SECCFGR2_OFFSET)
#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_PRIVCFGR2_OFFSET)
#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR1_OFFSET)
#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR2_OFFSET)
#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR3_OFFSET)
#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR4_OFFSET)
#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE+STM32L5_EXTI_LOCKR_OFFSET)
#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_IMR1_OFFSET)
#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_EMR1_OFFSET)
#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_IMR2_OFFSET)
#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_EMR2_OFFSET)
#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR1_OFFSET)
#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR1_OFFSET)
#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER1_OFFSET)
#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR1_OFFSET)
#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR1_OFFSET)
#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR1_OFFSET)
#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR1_OFFSET)
#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR2_OFFSET)
#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR2_OFFSET)
#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER2_OFFSET)
#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR2_OFFSET)
#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR2_OFFSET)
#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR2_OFFSET)
#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR2_OFFSET)
#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR1_OFFSET)
#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR2_OFFSET)
#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR3_OFFSET)
#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR4_OFFSET)
#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE + STM32L5_EXTI_LOCKR_OFFSET)
#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR1_OFFSET)
#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR1_OFFSET)
#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR2_OFFSET)
#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR2_OFFSET)
/* Register Bitfield Definitions ********************************************/

66
arch/arm/src/stm32l5/hardware/stm32l5_flash.h
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@ -141,39 +141,39 @@
/* Register Addresses ********************************************************/
#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_ACR_OFFSET)
#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_PDKEYR_OFFSET)
#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSKEYR_OFFSET)
#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECKEYR_OFFSET)
#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_OPTKEYR_OFFSET)
#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_LVEKEYR_OFFSET)
#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSSR_OFFSET)
#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECSR_OFFSET)
#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSCR_OFFSET)
#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECCR_OFFSET)
#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_ECCR_OFFSET)
#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_OPTR_OFFSET)
#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSBOOTADDR0R_OFFSET)
#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSBOOTADDR1R_OFFSET)
#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBOOTADDR0R_OFFSET)
#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM1R1_OFFSET)
#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM1R2_OFFSET)
#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP1AR_OFFSET)
#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP1BR_OFFSET)
#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM2R1_OFFSET)
#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM2R2_OFFSET)
#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP2AR_OFFSET)
#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP2BR_OFFSET)
#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R1_OFFSET)
#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R2_OFFSET)
#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R3_OFFSET)
#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R4_OFFSET)
#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R1_OFFSET)
#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R2_OFFSET)
#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R3_OFFSET)
#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R4_OFFSET)
#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECHDPCR_OFFSET)
#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_PRIVCFGR_OFFSET)
#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ACR_OFFSET)
#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PDKEYR_OFFSET)
#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSKEYR_OFFSET)
#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECKEYR_OFFSET)
#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTKEYR_OFFSET)
#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_LVEKEYR_OFFSET)
#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSSR_OFFSET)
#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECSR_OFFSET)
#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSCR_OFFSET)
#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECCR_OFFSET)
#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ECCR_OFFSET)
#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTR_OFFSET)
#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR0R_OFFSET)
#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR1R_OFFSET)
#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBOOTADDR0R_OFFSET)
#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R1_OFFSET)
#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R2_OFFSET)
#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1AR_OFFSET)
#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1BR_OFFSET)
#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R1_OFFSET)
#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R2_OFFSET)
#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2AR_OFFSET)
#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2BR_OFFSET)
#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R1_OFFSET)
#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R2_OFFSET)
#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R3_OFFSET)
#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R4_OFFSET)
#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R1_OFFSET)
#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R2_OFFSET)
#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R3_OFFSET)
#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R4_OFFSET)
#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECHDPCR_OFFSET)
#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PRIVCFGR_OFFSET)
/* Register Bitfield Definitions *********************************************/

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arch/arm/src/stm32l5/hardware/stm32l5_gpio.h
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@ -50,138 +50,138 @@
/* Register Addresses ********************************************************/
#if STM32L5_NPORTS > 0
# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 1
# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 2
# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 3
# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 4
# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 5
# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 6
# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 7
# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 8
# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE + STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE + STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE + STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE + STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE + STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE + STM32L5_GPIO_SECCFGR_OFFSET)
#endif
/* Register Bitfield Definitions *********************************************/

50
arch/arm/src/stm32l5/hardware/stm32l5_pwr.h
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@ -62,31 +62,31 @@
/* Register Addresses ********************************************************/
#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE+STM32L5_PWR_CR1_OFFSET)
#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE+STM32L5_PWR_CR2_OFFSET)
#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE+STM32L5_PWR_CR3_OFFSET)
#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE+STM32L5_PWR_CR4_OFFSET)
#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE+STM32L5_PWR_SR1_OFFSET)
#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE+STM32L5_PWR_SR2_OFFSET)
#define STM32L5_PWR_SCR (STM32L5_PWR_BASE+STM32L5_PWR_SCR_OFFSET)
#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE+STM32L5_PWR_PUCRA_OFFSET)
#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE+STM32L5_PWR_PDCRA_OFFSET)
#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE+STM32L5_PWR_PUCRB_OFFSET)
#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE+STM32L5_PWR_PDCRB_OFFSET)
#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE+STM32L5_PWR_PUCRC_OFFSET)
#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE+STM32L5_PWR_PDCRC_OFFSET)
#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE+STM32L5_PWR_PUCRD_OFFSET)
#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE+STM32L5_PWR_PDCRD_OFFSET)
#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE+STM32L5_PWR_PUCRE_OFFSET)
#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE+STM32L5_PWR_PDCRE_OFFSET)
#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE+STM32L5_PWR_PUCRF_OFFSET)
#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE+STM32L5_PWR_PDCRF_OFFSET)
#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE+STM32L5_PWR_PUCRG_OFFSET)
#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE+STM32L5_PWR_PDCRG_OFFSET)
#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE+STM32L5_PWR_PUCRH_OFFSET)
#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE+STM32L5_PWR_PDCRH_OFFSET)
#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE+STM32L5_PWR_SECCFGR_OFFSET)
#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE+STM32L5_PWR_PRIVCFGR_OFFSET)
#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE + STM32L5_PWR_CR1_OFFSET)
#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE + STM32L5_PWR_CR2_OFFSET)
#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE + STM32L5_PWR_CR3_OFFSET)
#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE + STM32L5_PWR_CR4_OFFSET)
#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE + STM32L5_PWR_SR1_OFFSET)
#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE + STM32L5_PWR_SR2_OFFSET)
#define STM32L5_PWR_SCR (STM32L5_PWR_BASE + STM32L5_PWR_SCR_OFFSET)
#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE + STM32L5_PWR_PUCRA_OFFSET)
#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE + STM32L5_PWR_PDCRA_OFFSET)
#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE + STM32L5_PWR_PUCRB_OFFSET)
#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE + STM32L5_PWR_PDCRB_OFFSET)
#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE + STM32L5_PWR_PUCRC_OFFSET)
#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE + STM32L5_PWR_PDCRC_OFFSET)
#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE + STM32L5_PWR_PUCRD_OFFSET)
#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE + STM32L5_PWR_PDCRD_OFFSET)
#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE + STM32L5_PWR_PUCRE_OFFSET)
#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE + STM32L5_PWR_PDCRE_OFFSET)
#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE + STM32L5_PWR_PUCRF_OFFSET)
#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE + STM32L5_PWR_PDCRF_OFFSET)
#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE + STM32L5_PWR_PUCRG_OFFSET)
#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE + STM32L5_PWR_PDCRG_OFFSET)
#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE + STM32L5_PWR_PUCRH_OFFSET)
#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE + STM32L5_PWR_PDCRH_OFFSET)
#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE + STM32L5_PWR_SECCFGR_OFFSET)
#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE + STM32L5_PWR_PRIVCFGR_OFFSET)
/* Register Bitfield Definitions *********************************************/

42
arch/arm/src/stm32l5/hardware/stm32l5_spi.h
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@ -53,33 +53,33 @@
/* Register Addresses ********************************************************/
#if STM32L5_NSPI > 0
# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE+STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE+STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE+STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE+STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE+STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE+STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE+STM32L5_SPI_TXCRCR_OFFSET)
# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE + STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE + STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE + STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE + STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE + STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_TXCRCR_OFFSET)
#endif
#if STM32L5_NSPI > 1
# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE+STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE+STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE+STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE+STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE+STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE+STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE+STM32L5_SPI_TXCRCR_OFFSET)
# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE + STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE + STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE + STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE + STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE + STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_TXCRCR_OFFSET)
#endif
#if STM32L5_NSPI > 2
# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE+STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE+STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE+STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE+STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE+STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE+STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE+STM32L5_SPI_TXCRCR_OFFSET)
# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE + STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE + STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE + STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE + STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE + STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions *********************************************/

380
arch/arm/src/stm32l5/hardware/stm32l5_tim.h
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@ -125,59 +125,59 @@
/* Advanced Timers - TIM1 and TIM8 */
#define STM32L5_TIM1_CR1 (STM32L5_TIM1_BASE+STM32L5_ATIM_CR1_OFFSET)
#define STM32L5_TIM1_CR2 (STM32L5_TIM1_BASE+STM32L5_ATIM_CR2_OFFSET)
#define STM32L5_TIM1_SMCR (STM32L5_TIM1_BASE+STM32L5_ATIM_SMCR_OFFSET)
#define STM32L5_TIM1_DIER (STM32L5_TIM1_BASE+STM32L5_ATIM_DIER_OFFSET)
#define STM32L5_TIM1_SR (STM32L5_TIM1_BASE+STM32L5_ATIM_SR_OFFSET)
#define STM32L5_TIM1_EGR (STM32L5_TIM1_BASE+STM32L5_ATIM_EGR_OFFSET)
#define STM32L5_TIM1_CCMR1 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCMR1_OFFSET)
#define STM32L5_TIM1_CCMR2 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCMR2_OFFSET)
#define STM32L5_TIM1_CCER (STM32L5_TIM1_BASE+STM32L5_ATIM_CCER_OFFSET)
#define STM32L5_TIM1_CNT (STM32L5_TIM1_BASE+STM32L5_ATIM_CNT_OFFSET)
#define STM32L5_TIM1_PSC (STM32L5_TIM1_BASE+STM32L5_ATIM_PSC_OFFSET)
#define STM32L5_TIM1_ARR (STM32L5_TIM1_BASE+STM32L5_ATIM_ARR_OFFSET)
#define STM32L5_TIM1_RCR (STM32L5_TIM1_BASE+STM32L5_ATIM_RCR_OFFSET)
#define STM32L5_TIM1_CCR1 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCR1_OFFSET)
#define STM32L5_TIM1_CCR2 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCR2_OFFSET)
#define STM32L5_TIM1_CCR3 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCR3_OFFSET)
#define STM32L5_TIM1_CCR4 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCR4_OFFSET)
#define STM32L5_TIM1_BDTR (STM32L5_TIM1_BASE+STM32L5_ATIM_BDTR_OFFSET)
#define STM32L5_TIM1_DCR (STM32L5_TIM1_BASE+STM32L5_ATIM_DCR_OFFSET)
#define STM32L5_TIM1_DMAR (STM32L5_TIM1_BASE+STM32L5_ATIM_DMAR_OFFSET)
#define STM32L5_TIM1_OR1 (STM32L5_TIM1_BASE+STM32L5_ATIM_OR1_OFFSET)
#define STM32L5_TIM1_CCMR3 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCMR3_OFFSET)
#define STM32L5_TIM1_CCR5 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCR5_OFFSET)
#define STM32L5_TIM1_CCR6 (STM32L5_TIM1_BASE+STM32L5_ATIM_CCR6_OFFSET)
#define STM32L5_TIM1_OR2 (STM32L5_TIM1_BASE+STM32L5_ATIM_OR2_OFFSET)
#define STM32L5_TIM1_OR3 (STM32L5_TIM1_BASE+STM32L5_ATIM_OR3_OFFSET)
#define STM32L5_TIM1_CR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR1_OFFSET)
#define STM32L5_TIM1_CR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR2_OFFSET)
#define STM32L5_TIM1_SMCR (STM32L5_TIM1_BASE + STM32L5_ATIM_SMCR_OFFSET)
#define STM32L5_TIM1_DIER (STM32L5_TIM1_BASE + STM32L5_ATIM_DIER_OFFSET)
#define STM32L5_TIM1_SR (STM32L5_TIM1_BASE + STM32L5_ATIM_SR_OFFSET)
#define STM32L5_TIM1_EGR (STM32L5_TIM1_BASE + STM32L5_ATIM_EGR_OFFSET)
#define STM32L5_TIM1_CCMR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR1_OFFSET)
#define STM32L5_TIM1_CCMR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR2_OFFSET)
#define STM32L5_TIM1_CCER (STM32L5_TIM1_BASE + STM32L5_ATIM_CCER_OFFSET)
#define STM32L5_TIM1_CNT (STM32L5_TIM1_BASE + STM32L5_ATIM_CNT_OFFSET)
#define STM32L5_TIM1_PSC (STM32L5_TIM1_BASE + STM32L5_ATIM_PSC_OFFSET)
#define STM32L5_TIM1_ARR (STM32L5_TIM1_BASE + STM32L5_ATIM_ARR_OFFSET)
#define STM32L5_TIM1_RCR (STM32L5_TIM1_BASE + STM32L5_ATIM_RCR_OFFSET)
#define STM32L5_TIM1_CCR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR1_OFFSET)
#define STM32L5_TIM1_CCR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR2_OFFSET)
#define STM32L5_TIM1_CCR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR3_OFFSET)
#define STM32L5_TIM1_CCR4 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR4_OFFSET)
#define STM32L5_TIM1_BDTR (STM32L5_TIM1_BASE + STM32L5_ATIM_BDTR_OFFSET)
#define STM32L5_TIM1_DCR (STM32L5_TIM1_BASE + STM32L5_ATIM_DCR_OFFSET)
#define STM32L5_TIM1_DMAR (STM32L5_TIM1_BASE + STM32L5_ATIM_DMAR_OFFSET)
#define STM32L5_TIM1_OR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR1_OFFSET)
#define STM32L5_TIM1_CCMR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR3_OFFSET)
#define STM32L5_TIM1_CCR5 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR5_OFFSET)
#define STM32L5_TIM1_CCR6 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR6_OFFSET)
#define STM32L5_TIM1_OR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR2_OFFSET)
#define STM32L5_TIM1_OR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR3_OFFSET)
#define STM32L5_TIM8_CR1 (STM32L5_TIM8_BASE+STM32L5_ATIM_CR1_OFFSET)
#define STM32L5_TIM8_CR2 (STM32L5_TIM8_BASE+STM32L5_ATIM_CR2_OFFSET)
#define STM32L5_TIM8_SMCR (STM32L5_TIM8_BASE+STM32L5_ATIM_SMCR_OFFSET)
#define STM32L5_TIM8_DIER (STM32L5_TIM8_BASE+STM32L5_ATIM_DIER_OFFSET)
#define STM32L5_TIM8_SR (STM32L5_TIM8_BASE+STM32L5_ATIM_SR_OFFSET)
#define STM32L5_TIM8_EGR (STM32L5_TIM8_BASE+STM32L5_ATIM_EGR_OFFSET)
#define STM32L5_TIM8_CCMR1 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCMR1_OFFSET)
#define STM32L5_TIM8_CCMR2 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCMR2_OFFSET)
#define STM32L5_TIM8_CCER (STM32L5_TIM8_BASE+STM32L5_ATIM_CCER_OFFSET)
#define STM32L5_TIM8_CNT (STM32L5_TIM8_BASE+STM32L5_ATIM_CNT_OFFSET)
#define STM32L5_TIM8_PSC (STM32L5_TIM8_BASE+STM32L5_ATIM_PSC_OFFSET)
#define STM32L5_TIM8_ARR (STM32L5_TIM8_BASE+STM32L5_ATIM_ARR_OFFSET)
#define STM32L5_TIM8_RCR (STM32L5_TIM8_BASE+STM32L5_ATIM_RCR_OFFSET)
#define STM32L5_TIM8_CCR1 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCR1_OFFSET)
#define STM32L5_TIM8_CCR2 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCR2_OFFSET)
#define STM32L5_TIM8_CCR3 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCR3_OFFSET)
#define STM32L5_TIM8_CCR4 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCR4_OFFSET)
#define STM32L5_TIM8_BDTR (STM32L5_TIM8_BASE+STM32L5_ATIM_BDTR_OFFSET)
#define STM32L5_TIM8_DCR (STM32L5_TIM8_BASE+STM32L5_ATIM_DCR_OFFSET)
#define STM32L5_TIM8_DMAR (STM32L5_TIM8_BASE+STM32L5_ATIM_DMAR_OFFSET)
#define STM32L5_TIM8_OR1 (STM32L5_TIM8_BASE+STM32L5_ATIM_OR1_OFFSET)
#define STM32L5_TIM8_CCMR3 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCMR3_OFFSET)
#define STM32L5_TIM8_CCR5 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCR5_OFFSET)
#define STM32L5_TIM8_CCR6 (STM32L5_TIM8_BASE+STM32L5_ATIM_CCR6_OFFSET)
#define STM32L5_TIM8_OR2 (STM32L5_TIM8_BASE+STM32L5_ATIM_OR2_OFFSET)
#define STM32L5_TIM8_OR3 (STM32L5_TIM8_BASE+STM32L5_ATIM_OR3_OFFSET)
#define STM32L5_TIM8_CR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR1_OFFSET)
#define STM32L5_TIM8_CR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR2_OFFSET)
#define STM32L5_TIM8_SMCR (STM32L5_TIM8_BASE + STM32L5_ATIM_SMCR_OFFSET)
#define STM32L5_TIM8_DIER (STM32L5_TIM8_BASE + STM32L5_ATIM_DIER_OFFSET)
#define STM32L5_TIM8_SR (STM32L5_TIM8_BASE + STM32L5_ATIM_SR_OFFSET)
#define STM32L5_TIM8_EGR (STM32L5_TIM8_BASE + STM32L5_ATIM_EGR_OFFSET)
#define STM32L5_TIM8_CCMR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR1_OFFSET)
#define STM32L5_TIM8_CCMR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR2_OFFSET)
#define STM32L5_TIM8_CCER (STM32L5_TIM8_BASE + STM32L5_ATIM_CCER_OFFSET)
#define STM32L5_TIM8_CNT (STM32L5_TIM8_BASE + STM32L5_ATIM_CNT_OFFSET)
#define STM32L5_TIM8_PSC (STM32L5_TIM8_BASE + STM32L5_ATIM_PSC_OFFSET)
#define STM32L5_TIM8_ARR (STM32L5_TIM8_BASE + STM32L5_ATIM_ARR_OFFSET)
#define STM32L5_TIM8_RCR (STM32L5_TIM8_BASE + STM32L5_ATIM_RCR_OFFSET)
#define STM32L5_TIM8_CCR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR1_OFFSET)
#define STM32L5_TIM8_CCR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR2_OFFSET)
#define STM32L5_TIM8_CCR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR3_OFFSET)
#define STM32L5_TIM8_CCR4 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR4_OFFSET)
#define STM32L5_TIM8_BDTR (STM32L5_TIM8_BASE + STM32L5_ATIM_BDTR_OFFSET)
#define STM32L5_TIM8_DCR (STM32L5_TIM8_BASE + STM32L5_ATIM_DCR_OFFSET)
#define STM32L5_TIM8_DMAR (STM32L5_TIM8_BASE + STM32L5_ATIM_DMAR_OFFSET)
#define STM32L5_TIM8_OR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR1_OFFSET)
#define STM32L5_TIM8_CCMR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR3_OFFSET)
#define STM32L5_TIM8_CCR5 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR5_OFFSET)
#define STM32L5_TIM8_CCR6 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR6_OFFSET)
#define STM32L5_TIM8_OR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR2_OFFSET)
#define STM32L5_TIM8_OR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR3_OFFSET)
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17.
* TIM3 and 4 are 16-bit.
@ -185,154 +185,154 @@
* TIM15, 16 and 17 are 16-bit.
*/
#define STM32L5_TIM2_CR1 (STM32L5_TIM2_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM2_CR2 (STM32L5_TIM2_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM2_SMCR (STM32L5_TIM2_BASE+STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM2_DIER (STM32L5_TIM2_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM2_SR (STM32L5_TIM2_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM2_EGR (STM32L5_TIM2_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM2_CCMR1 (STM32L5_TIM2_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM2_CCMR2 (STM32L5_TIM2_BASE+STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM2_CCER (STM32L5_TIM2_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM2_CNT (STM32L5_TIM2_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM2_PSC (STM32L5_TIM2_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM2_ARR (STM32L5_TIM2_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM2_CCR1 (STM32L5_TIM2_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM2_CCR2 (STM32L5_TIM2_BASE+STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM2_CCR3 (STM32L5_TIM2_BASE+STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM2_CCR4 (STM32L5_TIM2_BASE+STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM2_DCR (STM32L5_TIM2_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM2_DMAR (STM32L5_TIM2_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM2_OR (STM32L5_TIM2_BASE+STM32L5_GTIM_OR_OFFSET)
#define STM32L5_TIM2_CR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM2_CR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM2_SMCR (STM32L5_TIM2_BASE + STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM2_DIER (STM32L5_TIM2_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM2_SR (STM32L5_TIM2_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM2_EGR (STM32L5_TIM2_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM2_CCMR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM2_CCMR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM2_CCER (STM32L5_TIM2_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM2_CNT (STM32L5_TIM2_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM2_PSC (STM32L5_TIM2_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM2_ARR (STM32L5_TIM2_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM2_CCR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM2_CCR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM2_CCR3 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM2_CCR4 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM2_DCR (STM32L5_TIM2_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM2_DMAR (STM32L5_TIM2_BASE + STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM2_OR (STM32L5_TIM2_BASE + STM32L5_GTIM_OR_OFFSET)
#define STM32L5_TIM3_CR1 (STM32L5_TIM3_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM3_CR2 (STM32L5_TIM3_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM3_SMCR (STM32L5_TIM3_BASE+STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM3_DIER (STM32L5_TIM3_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM3_SR (STM32L5_TIM3_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM3_EGR (STM32L5_TIM3_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM3_CCMR1 (STM32L5_TIM3_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM3_CCMR2 (STM32L5_TIM3_BASE+STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM3_CCER (STM32L5_TIM3_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM3_CNT (STM32L5_TIM3_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM3_PSC (STM32L5_TIM3_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM3_ARR (STM32L5_TIM3_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM3_CCR1 (STM32L5_TIM3_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM3_CCR2 (STM32L5_TIM3_BASE+STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM3_CCR3 (STM32L5_TIM3_BASE+STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM3_CCR4 (STM32L5_TIM3_BASE+STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM3_DCR (STM32L5_TIM3_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM3_DMAR (STM32L5_TIM3_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM3_CR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM3_CR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM3_SMCR (STM32L5_TIM3_BASE + STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM3_DIER (STM32L5_TIM3_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM3_SR (STM32L5_TIM3_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM3_EGR (STM32L5_TIM3_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM3_CCMR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM3_CCMR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM3_CCER (STM32L5_TIM3_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM3_CNT (STM32L5_TIM3_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM3_PSC (STM32L5_TIM3_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM3_ARR (STM32L5_TIM3_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM3_CCR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM3_CCR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM3_CCR3 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM3_CCR4 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM3_DCR (STM32L5_TIM3_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM3_DMAR (STM32L5_TIM3_BASE + STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM4_CR1 (STM32L5_TIM4_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM4_CR2 (STM32L5_TIM4_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM4_SMCR (STM32L5_TIM4_BASE+STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM4_DIER (STM32L5_TIM4_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM4_SR (STM32L5_TIM4_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM4_EGR (STM32L5_TIM4_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM4_CCMR1 (STM32L5_TIM4_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM4_CCMR2 (STM32L5_TIM4_BASE+STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM4_CCER (STM32L5_TIM4_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM4_CNT (STM32L5_TIM4_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM4_PSC (STM32L5_TIM4_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM4_ARR (STM32L5_TIM4_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM4_CCR1 (STM32L5_TIM4_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM4_CCR2 (STM32L5_TIM4_BASE+STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM4_CCR3 (STM32L5_TIM4_BASE+STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM4_CCR4 (STM32L5_TIM4_BASE+STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM4_DCR (STM32L5_TIM4_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM4_DMAR (STM32L5_TIM4_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM4_CR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM4_CR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM4_SMCR (STM32L5_TIM4_BASE + STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM4_DIER (STM32L5_TIM4_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM4_SR (STM32L5_TIM4_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM4_EGR (STM32L5_TIM4_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM4_CCMR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM4_CCMR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM4_CCER (STM32L5_TIM4_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM4_CNT (STM32L5_TIM4_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM4_PSC (STM32L5_TIM4_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM4_ARR (STM32L5_TIM4_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM4_CCR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM4_CCR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM4_CCR3 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM4_CCR4 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM4_DCR (STM32L5_TIM4_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM4_DMAR (STM32L5_TIM4_BASE + STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM5_CR1 (STM32L5_TIM5_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM5_CR2 (STM32L5_TIM5_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM5_SMCR (STM32L5_TIM5_BASE+STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM5_DIER (STM32L5_TIM5_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM5_SR (STM32L5_TIM5_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM5_EGR (STM32L5_TIM5_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM5_CCMR1 (STM32L5_TIM5_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM5_CCMR2 (STM32L5_TIM5_BASE+STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM5_CCER (STM32L5_TIM5_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM5_CNT (STM32L5_TIM5_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM5_PSC (STM32L5_TIM5_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM5_ARR (STM32L5_TIM5_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM5_CCR1 (STM32L5_TIM5_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM5_CCR2 (STM32L5_TIM5_BASE+STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM5_CCR3 (STM32L5_TIM5_BASE+STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM5_CCR4 (STM32L5_TIM5_BASE+STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM5_DCR (STM32L5_TIM5_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM5_DMAR (STM32L5_TIM5_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM5_OR (STM32L5_TIM5_BASE+STM32L5_GTIM_OR_OFFSET)
#define STM32L5_TIM5_CR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM5_CR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM5_SMCR (STM32L5_TIM5_BASE + STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM5_DIER (STM32L5_TIM5_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM5_SR (STM32L5_TIM5_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM5_EGR (STM32L5_TIM5_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM5_CCMR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM5_CCMR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR2_OFFSET)
#define STM32L5_TIM5_CCER (STM32L5_TIM5_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM5_CNT (STM32L5_TIM5_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM5_PSC (STM32L5_TIM5_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM5_ARR (STM32L5_TIM5_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM5_CCR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM5_CCR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM5_CCR3 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR3_OFFSET)
#define STM32L5_TIM5_CCR4 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR4_OFFSET)
#define STM32L5_TIM5_DCR (STM32L5_TIM5_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM5_DMAR (STM32L5_TIM5_BASE + STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM5_OR (STM32L5_TIM5_BASE + STM32L5_GTIM_OR_OFFSET)
#define STM32L5_TIM15_CR1 (STM32L5_TIM15_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM15_CR2 (STM32L5_TIM15_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM15_SMCR (STM32L5_TIM15_BASE+STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM15_DIER (STM32L5_TIM15_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM15_SR (STM32L5_TIM15_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM15_EGR (STM32L5_TIM15_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM15_CCMR1 (STM32L5_TIM15_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM15_CCER (STM32L5_TIM15_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM15_CNT (STM32L5_TIM15_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM15_PSC (STM32L5_TIM15_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM15_ARR (STM32L5_TIM15_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM15_RCR (STM32L5_TIM15_BASE+STM32L5_GTIM_RCR_OFFSET)
#define STM32L5_TIM15_CCR1 (STM32L5_TIM15_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM15_CCR2 (STM32L5_TIM15_BASE+STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM15_BDTR (STM32L5_TIM15_BASE+STM32L5_GTIM_BDTR_OFFSET)
#define STM32L5_TIM15_DCR (STM32L5_TIM15_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM15_DMAR (STM32L5_TIM15_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM15_CR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM15_CR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM15_SMCR (STM32L5_TIM15_BASE + STM32L5_GTIM_SMCR_OFFSET)
#define STM32L5_TIM15_DIER (STM32L5_TIM15_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM15_SR (STM32L5_TIM15_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM15_EGR (STM32L5_TIM15_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM15_CCMR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM15_CCER (STM32L5_TIM15_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM15_CNT (STM32L5_TIM15_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM15_PSC (STM32L5_TIM15_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM15_ARR (STM32L5_TIM15_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM15_RCR (STM32L5_TIM15_BASE + STM32L5_GTIM_RCR_OFFSET)
#define STM32L5_TIM15_CCR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM15_CCR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR2_OFFSET)
#define STM32L5_TIM15_BDTR (STM32L5_TIM15_BASE + STM32L5_GTIM_BDTR_OFFSET)
#define STM32L5_TIM15_DCR (STM32L5_TIM15_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM15_DMAR (STM32L5_TIM15_BASE + STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM16_CR1 (STM32L5_TIM16_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM16_CR2 (STM32L5_TIM16_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM16_DIER (STM32L5_TIM16_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM16_SR (STM32L5_TIM16_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM16_EGR (STM32L5_TIM16_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM16_CCMR1 (STM32L5_TIM16_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM16_CCER (STM32L5_TIM16_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM16_CNT (STM32L5_TIM16_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM16_PSC (STM32L5_TIM16_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM16_ARR (STM32L5_TIM16_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM16_RCR (STM32L5_TIM16_BASE+STM32L5_GTIM_RCR_OFFSET)
#define STM32L5_TIM16_CCR1 (STM32L5_TIM16_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM16_BDTR (STM32L5_TIM16_BASE+STM32L5_GTIM_BDTR_OFFSET)
#define STM32L5_TIM16_DCR (STM32L5_TIM16_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM16_DMAR (STM32L5_TIM16_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM16_OR (STM32L5_TIM16_BASE+STM32L5_GTIM_OR_OFFSET)
#define STM32L5_TIM16_CR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM16_CR2 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM16_DIER (STM32L5_TIM16_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM16_SR (STM32L5_TIM16_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM16_EGR (STM32L5_TIM16_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM16_CCMR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM16_CCER (STM32L5_TIM16_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM16_CNT (STM32L5_TIM16_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM16_PSC (STM32L5_TIM16_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM16_ARR (STM32L5_TIM16_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM16_RCR (STM32L5_TIM16_BASE + STM32L5_GTIM_RCR_OFFSET)
#define STM32L5_TIM16_CCR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM16_BDTR (STM32L5_TIM16_BASE + STM32L5_GTIM_BDTR_OFFSET)
#define STM32L5_TIM16_DCR (STM32L5_TIM16_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM16_DMAR (STM32L5_TIM16_BASE + STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM16_OR (STM32L5_TIM16_BASE + STM32L5_GTIM_OR_OFFSET)
#define STM32L5_TIM17_CR1 (STM32L5_TIM17_BASE+STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM17_CR2 (STM32L5_TIM17_BASE+STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM17_DIER (STM32L5_TIM17_BASE+STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM17_SR (STM32L5_TIM17_BASE+STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM17_EGR (STM32L5_TIM17_BASE+STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM17_CCMR1 (STM32L5_TIM17_BASE+STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM17_CCER (STM32L5_TIM17_BASE+STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM17_CNT (STM32L5_TIM17_BASE+STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM17_PSC (STM32L5_TIM17_BASE+STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM17_ARR (STM32L5_TIM17_BASE+STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM17_RCR (STM32L5_TIM17_BASE+STM32L5_GTIM_RCR_OFFSET)
#define STM32L5_TIM17_CCR1 (STM32L5_TIM17_BASE+STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM17_BDTR (STM32L5_TIM17_BASE+STM32L5_GTIM_BDTR_OFFSET)
#define STM32L5_TIM17_DCR (STM32L5_TIM17_BASE+STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM17_DMAR (STM32L5_TIM17_BASE+STM32L5_GTIM_DMAR_OFFSET)
#define STM32L5_TIM17_CR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR1_OFFSET)
#define STM32L5_TIM17_CR2 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR2_OFFSET)
#define STM32L5_TIM17_DIER (STM32L5_TIM17_BASE + STM32L5_GTIM_DIER_OFFSET)
#define STM32L5_TIM17_SR (STM32L5_TIM17_BASE + STM32L5_GTIM_SR_OFFSET)
#define STM32L5_TIM17_EGR (STM32L5_TIM17_BASE + STM32L5_GTIM_EGR_OFFSET)
#define STM32L5_TIM17_CCMR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCMR1_OFFSET)
#define STM32L5_TIM17_CCER (STM32L5_TIM17_BASE + STM32L5_GTIM_CCER_OFFSET)
#define STM32L5_TIM17_CNT (STM32L5_TIM17_BASE + STM32L5_GTIM_CNT_OFFSET)
#define STM32L5_TIM17_PSC (STM32L5_TIM17_BASE + STM32L5_GTIM_PSC_OFFSET)
#define STM32L5_TIM17_ARR (STM32L5_TIM17_BASE + STM32L5_GTIM_ARR_OFFSET)
#define STM32L5_TIM17_RCR (STM32L5_TIM17_BASE + STM32L5_GTIM_RCR_OFFSET)
#define STM32L5_TIM17_CCR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCR1_OFFSET)
#define STM32L5_TIM17_BDTR (STM32L5_TIM17_BASE + STM32L5_GTIM_BDTR_OFFSET)
#define STM32L5_TIM17_DCR (STM32L5_TIM17_BASE + STM32L5_GTIM_DCR_OFFSET)
#define STM32L5_TIM17_DMAR (STM32L5_TIM17_BASE + STM32L5_GTIM_DMAR_OFFSET)
/* Basic Timers - TIM6 and TIM7 */
#define STM32L5_TIM6_CR1 (STM32L5_TIM6_BASE+STM32L5_BTIM_CR1_OFFSET)
#define STM32L5_TIM6_CR2 (STM32L5_TIM6_BASE+STM32L5_BTIM_CR2_OFFSET)
#define STM32L5_TIM6_DIER (STM32L5_TIM6_BASE+STM32L5_BTIM_DIER_OFFSET)
#define STM32L5_TIM6_SR (STM32L5_TIM6_BASE+STM32L5_BTIM_SR_OFFSET)
#define STM32L5_TIM6_EGR (STM32L5_TIM6_BASE+STM32L5_BTIM_EGR_OFFSET)
#define STM32L5_TIM6_CNT (STM32L5_TIM6_BASE+STM32L5_BTIM_CNT_OFFSET)
#define STM32L5_TIM6_PSC (STM32L5_TIM6_BASE+STM32L5_BTIM_PSC_OFFSET)
#define STM32L5_TIM6_ARR (STM32L5_TIM6_BASE+STM32L5_BTIM_ARR_OFFSET)
#define STM32L5_TIM6_CR1 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR1_OFFSET)
#define STM32L5_TIM6_CR2 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR2_OFFSET)
#define STM32L5_TIM6_DIER (STM32L5_TIM6_BASE + STM32L5_BTIM_DIER_OFFSET)
#define STM32L5_TIM6_SR (STM32L5_TIM6_BASE + STM32L5_BTIM_SR_OFFSET)
#define STM32L5_TIM6_EGR (STM32L5_TIM6_BASE + STM32L5_BTIM_EGR_OFFSET)
#define STM32L5_TIM6_CNT (STM32L5_TIM6_BASE + STM32L5_BTIM_CNT_OFFSET)
#define STM32L5_TIM6_PSC (STM32L5_TIM6_BASE + STM32L5_BTIM_PSC_OFFSET)
#define STM32L5_TIM6_ARR (STM32L5_TIM6_BASE + STM32L5_BTIM_ARR_OFFSET)
#define STM32L5_TIM7_CR1 (STM32L5_TIM7_BASE+STM32L5_BTIM_CR1_OFFSET)
#define STM32L5_TIM7_CR2 (STM32L5_TIM7_BASE+STM32L5_BTIM_CR2_OFFSET)
#define STM32L5_TIM7_DIER (STM32L5_TIM7_BASE+STM32L5_BTIM_DIER_OFFSET)
#define STM32L5_TIM7_SR (STM32L5_TIM7_BASE+STM32L5_BTIM_SR_OFFSET)
#define STM32L5_TIM7_EGR (STM32L5_TIM7_BASE+STM32L5_BTIM_EGR_OFFSET)
#define STM32L5_TIM7_CNT (STM32L5_TIM7_BASE+STM32L5_BTIM_CNT_OFFSET)
#define STM32L5_TIM7_PSC (STM32L5_TIM7_BASE+STM32L5_BTIM_PSC_OFFSET)
#define STM32L5_TIM7_ARR (STM32L5_TIM7_BASE+STM32L5_BTIM_ARR_OFFSET)
#define STM32L5_TIM7_CR1 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR1_OFFSET)
#define STM32L5_TIM7_CR2 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR2_OFFSET)
#define STM32L5_TIM7_DIER (STM32L5_TIM7_BASE + STM32L5_BTIM_DIER_OFFSET)
#define STM32L5_TIM7_SR (STM32L5_TIM7_BASE + STM32L5_BTIM_SR_OFFSET)
#define STM32L5_TIM7_EGR (STM32L5_TIM7_BASE + STM32L5_BTIM_EGR_OFFSET)
#define STM32L5_TIM7_CNT (STM32L5_TIM7_BASE + STM32L5_BTIM_CNT_OFFSET)
#define STM32L5_TIM7_PSC (STM32L5_TIM7_BASE + STM32L5_BTIM_PSC_OFFSET)
#define STM32L5_TIM7_ARR (STM32L5_TIM7_BASE + STM32L5_BTIM_ARR_OFFSET)
/* Register Bitfield Definitions *********************************************/

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arch/arm/src/stm32l5/hardware/stm32l5_uart.h
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@ -51,78 +51,78 @@
/* Register Addresses ********************************************************/
#if STM32L5_NUSART > 0
# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART1_BRR (STM32L5_USART1_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART1_RQR (STM32L5_USART1_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART1_ISR (STM32L5_USART1_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART1_ICR (STM32L5_USART1_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART1_RDR (STM32L5_USART1_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART1_TDR (STM32L5_USART1_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE+STM32L5_USART_PRESC_OFFSET)
# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE + STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE + STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE + STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART1_BRR (STM32L5_USART1_BASE + STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE + STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE + STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART1_RQR (STM32L5_USART1_BASE + STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART1_ISR (STM32L5_USART1_BASE + STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART1_ICR (STM32L5_USART1_BASE + STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART1_RDR (STM32L5_USART1_BASE + STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART1_TDR (STM32L5_USART1_BASE + STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE + STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 1
# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART2_BRR (STM32L5_USART2_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART2_RQR (STM32L5_USART2_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART2_ISR (STM32L5_USART2_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART2_ICR (STM32L5_USART2_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART2_RDR (STM32L5_USART2_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART2_TDR (STM32L5_USART2_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE+STM32L5_USART_PRESC_OFFSET)
# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE + STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE + STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE + STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART2_BRR (STM32L5_USART2_BASE + STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE + STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE + STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART2_RQR (STM32L5_USART2_BASE + STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART2_ISR (STM32L5_USART2_BASE + STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART2_ICR (STM32L5_USART2_BASE + STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART2_RDR (STM32L5_USART2_BASE + STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART2_TDR (STM32L5_USART2_BASE + STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE + STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 2
# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART3_BRR (STM32L5_USART3_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART3_RQR (STM32L5_USART3_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART3_ISR (STM32L5_USART3_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART3_ICR (STM32L5_USART3_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART3_RDR (STM32L5_USART3_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART3_TDR (STM32L5_USART3_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE+STM32L5_USART_PRESC_OFFSET)
# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE + STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE + STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE + STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART3_BRR (STM32L5_USART3_BASE + STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE + STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE + STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART3_RQR (STM32L5_USART3_BASE + STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART3_ISR (STM32L5_USART3_BASE + STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART3_ICR (STM32L5_USART3_BASE + STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART3_RDR (STM32L5_USART3_BASE + STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART3_TDR (STM32L5_USART3_BASE + STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE + STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 3
# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_UART4_BRR (STM32L5_UART4_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_UART4_RQR (STM32L5_UART4_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_UART4_ISR (STM32L5_UART4_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_UART4_ICR (STM32L5_UART4_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_UART4_RDR (STM32L5_UART4_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_UART4_TDR (STM32L5_UART4_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE+STM32L5_USART_PRESC_OFFSET)
# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE + STM32L5_USART_CR1_OFFSET)
# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE + STM32L5_USART_CR2_OFFSET)
# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE + STM32L5_USART_CR3_OFFSET)
# define STM32L5_UART4_BRR (STM32L5_UART4_BASE + STM32L5_USART_BRR_OFFSET)
# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE + STM32L5_USART_GTPR_OFFSET)
# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE + STM32L5_USART_RTOR_OFFSET)
# define STM32L5_UART4_RQR (STM32L5_UART4_BASE + STM32L5_USART_RQR_OFFSET)
# define STM32L5_UART4_ISR (STM32L5_UART4_BASE + STM32L5_USART_ISR_OFFSET)
# define STM32L5_UART4_ICR (STM32L5_UART4_BASE + STM32L5_USART_ICR_OFFSET)
# define STM32L5_UART4_RDR (STM32L5_UART4_BASE + STM32L5_USART_RDR_OFFSET)
# define STM32L5_UART4_TDR (STM32L5_UART4_BASE + STM32L5_USART_TDR_OFFSET)
# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE + STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 4
# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_UART5_BRR (STM32L5_UART5_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_UART5_RQR (STM32L5_UART5_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_UART5_ISR (STM32L5_UART5_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_UART5_ICR (STM32L5_UART5_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_UART5_RDR (STM32L5_UART5_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_UART5_TDR (STM32L5_UART5_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE+STM32L5_USART_PRESC_OFFSET)
# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE + STM32L5_USART_CR1_OFFSET)
# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE + STM32L5_USART_CR2_OFFSET)
# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE + STM32L5_USART_CR3_OFFSET)
# define STM32L5_UART5_BRR (STM32L5_UART5_BASE + STM32L5_USART_BRR_OFFSET)
# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE + STM32L5_USART_GTPR_OFFSET)
# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE + STM32L5_USART_RTOR_OFFSET)
# define STM32L5_UART5_RQR (STM32L5_UART5_BASE + STM32L5_USART_RQR_OFFSET)
# define STM32L5_UART5_ISR (STM32L5_UART5_BASE + STM32L5_USART_ISR_OFFSET)
# define STM32L5_UART5_ICR (STM32L5_UART5_BASE + STM32L5_USART_ICR_OFFSET)
# define STM32L5_UART5_RDR (STM32L5_UART5_BASE + STM32L5_USART_RDR_OFFSET)
# define STM32L5_UART5_TDR (STM32L5_UART5_BASE + STM32L5_USART_TDR_OFFSET)
# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE + STM32L5_USART_PRESC_OFFSET)
#endif
/* Register Bitfield Definitions *********************************************/

4
arch/arm/src/stm32l5/stm32l5_start.c
View File

@ -64,8 +64,8 @@
#define SRAM2_START STM32L5_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE)
#define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
#define IDLE_STACK ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE - 4)
#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task