arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (3/4)
Summary:
- This commit applies the following imxrt_enet.c changes to imx_enet.c
commit 522a949ed5
Author: David Sidrane <David.Sidrane@NscDg.com>
Date: Wed Jul 13 11:00:11 2022 -0700
imxrt:enet Better interrupt state handeling
- NOTE: I also fixed typo and compile error in the above commit
Impact:
- imx_enet.c
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa
David Sidrane
parent
6dfd01885d
commit
fb8562763a
@ -279,6 +279,7 @@ struct imx_driver_s
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uint8_t rxtail; /* The next RX descriptor to use */
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uint8_t phyaddr; /* Selected PHY address */
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struct wdog_s txtimeout; /* TX timeout timer */
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uint32_t ints; /* Enabled interrupts */
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struct work_s irqwork; /* For deferring interrupt work to the work queue */
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struct work_s pollwork; /* For deferring poll work to the work queue */
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struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
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@ -322,6 +323,11 @@ static inline uint32_t imx_enet_getreg32(struct imx_driver_s *priv,
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static inline void imx_enet_putreg32(struct imx_driver_s *priv,
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uint32_t value, uint32_t offset);
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static inline void imx_enet_modifyreg32(struct imx_driver_s *priv,
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unsigned int offset,
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uint32_t clearbits,
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uint32_t setbits);
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#ifndef IMXRT_BUFFERS_SWAP
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# define imx_swap32(value) (value)
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# define imx_swap16(value) (value)
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@ -424,6 +430,31 @@ static inline uint32_t imx_enet_getreg32(struct imx_driver_s *priv,
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return getreg32(priv->base + offset);
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}
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/****************************************************************************
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* Name: imx_enet_modifyreg32
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*
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* Description:
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* Atomically modify the specified bits in a memory mapped register
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*
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* Input Parameters:
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* priv - private SPI device structure
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* offset - offset to the register of interest
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* clearbits - the 32-bit value to be written as 0s
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* setbits - the 32-bit value to be written as 1s
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void imx_enet_modifyreg32(struct imx_driver_s *priv,
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unsigned int offset,
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uint32_t clearbits,
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uint32_t setbits)
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{
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modifyreg32(priv->base + offset, clearbits, setbits);
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}
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/****************************************************************************
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* Name: imx_enet_putreg32
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*
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@ -552,8 +583,6 @@ static bool imx_txringfull(struct imx_driver_s *priv)
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static int imx_transmit(struct imx_driver_s *priv)
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{
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struct enet_desc_s *txdesc;
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irqstate_t flags;
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uint32_t regval;
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uint8_t *buf;
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/* Since this can be called from imx_receive, it is possible that
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@ -627,27 +656,20 @@ static int imx_transmit(struct imx_driver_s *priv)
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DEBUGASSERT(txdesc->data == buf);
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}
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/* Make the following operations atomic */
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/* Start the TX transfer (if it was not already waiting for buffers) */
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flags = spin_lock_irqsave(NULL);
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imx_enet_putreg32(priv, ENET_TDAR, IMX_ENET_TDAR_OFFSET);
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/* Enable TX interrupts */
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regval = imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
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regval |= TX_INTERRUPTS;
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imx_enet_putreg32(priv, regval, IMX_ENET_EIMR_OFFSET);
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priv->ints |= TX_INTERRUPTS;
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imx_enet_modifyreg32(priv, IMX_ENET_EIMR_OFFSET, 0, TX_INTERRUPTS);
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/* Setup the TX timeout watchdog (perhaps restarting the timer) */
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wd_start(&priv->txtimeout, IMX_TXTIMEOUT,
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imx_txtimeout_expiry, (wdparm_t)priv);
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/* Start the TX transfer (if it was not already waiting for buffers) */
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imx_enet_putreg32(priv, ENET_TDAR, IMX_ENET_TDAR_OFFSET);
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spin_unlock_irqrestore(NULL, flags);
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#if CONFIG_IMX_ENET_NTXBUFFERS == 1
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priv->txbusy = false;
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#endif
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@ -991,7 +1013,6 @@ static void imx_receive(struct imx_driver_s *priv)
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static void imx_txdone(struct imx_driver_s *priv)
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{
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struct enet_desc_s *txdesc;
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uint32_t regval;
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bool txdone;
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/* We are here because a transmission completed, so the watchdog can be
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@ -1042,9 +1063,9 @@ static void imx_txdone(struct imx_driver_s *priv)
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wd_cancel(&priv->txtimeout);
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regval = imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
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regval &= ~TX_INTERRUPTS;
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imx_enet_putreg32(priv, regval, IMX_ENET_EIMR_OFFSET);
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priv->ints &= ~TX_INTERRUPTS;
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imx_enet_modifyreg32(priv, IMX_ENET_EIMR_OFFSET, TX_INTERRUPTS,
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priv->ints);
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}
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/* There should be space for a new TX in any event. Poll the network for
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@ -1086,8 +1107,7 @@ static void imx_enet_interrupt_work(void *arg)
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/* Get the set of unmasked, pending interrupt. */
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pending = imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) &
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imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
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pending = imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) & priv->ints;
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/* Clear the pending interrupts */
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@ -1101,8 +1121,7 @@ static void imx_enet_interrupt_work(void *arg)
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NETDEV_ERRORS(&priv->dev);
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nerr("ERROR: Network interface error occurred (0x%08" PRIX32 ")\n",
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(pending & ERROR_INTERRUPTS));
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nerr("pending %" PRIx32 " ints %" PRIx32 "\n", pending, priv->ints);
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}
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if (pending & CRITICAL_ERROR)
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@ -1166,10 +1185,7 @@ static void imx_enet_interrupt_work(void *arg)
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/* Re-enable Ethernet interrupts */
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#if 0
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up_enable_irq(IMX_IRQ_ENET0TMR);
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#endif
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up_enable_irq(IMX_IRQ_ENET0);
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imx_enet_putreg32(priv, priv->ints, IMX_ENET_EIMR_OFFSET);
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}
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/****************************************************************************
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@ -1202,7 +1218,7 @@ static int imx_enet_interrupt(int irq, void *context, void *arg)
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* condition here.
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*/
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up_disable_irq(IMX_IRQ_ENET0);
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imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
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/* Schedule to perform the interrupt processing on the worker thread. */
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@ -1277,7 +1293,8 @@ static void imx_txtimeout_expiry(wdparm_t arg)
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* condition with interrupt work that is already queued and in progress.
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*/
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up_disable_irq(IMX_IRQ_ENET0);
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imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
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priv->ints = 0;
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/* Schedule to perform the TX timeout processing on the worker thread,
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* canceling any pending interrupt work.
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@ -1387,26 +1404,26 @@ static int imx_ifup_action(struct net_driver_s *dev, bool resetphy)
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imx_enet_putreg32(priv, ENET_RDAR, IMX_ENET_RDAR_OFFSET);
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imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
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/* Clear all pending ENET interrupt */
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imx_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS,
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IMX_ENET_EIR_OFFSET);
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imx_enet_putreg32(priv, 0xffffffff, IMX_ENET_EIR_OFFSET);
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/* Mark the interrupt "up" and enable interrupts at the NVIC */
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up_enable_irq(IMX_IRQ_ENET0);
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priv->bifup = true;
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/* Enable RX and error interrupts at the controller (TX interrupts are
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* still disabled).
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*/
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imx_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS,
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IMX_ENET_EIMR_OFFSET);
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priv->ints = RX_INTERRUPTS | ERROR_INTERRUPTS;
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imx_enet_modifyreg32(priv, IMX_ENET_EIMR_OFFSET, TX_INTERRUPTS,
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priv->ints);
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/* Mark the interrupt "up" and enable interrupts at the NVIC */
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priv->bifup = true;
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#if 0
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up_enable_irq(IMX_IRQ_ENET0TMR);
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#endif
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up_enable_irq(IMX_IRQ_ENET0);
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return OK;
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}
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@ -1466,8 +1483,9 @@ static int imx_ifdown(struct net_driver_s *dev)
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flags = enter_critical_section();
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priv->ints = 0;
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imx_enet_putreg32(priv, priv->ints, IMX_ENET_EIMR_OFFSET);
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up_disable_irq(IMX_IRQ_ENET0);
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imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
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/* Cancel the TX timeout timers */
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