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arch/nrf53: add more register definitions (ported from nrf52) and some cosmetics for nrf52

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This commit is contained in:
raiden00pl 2023-03-02 19:26:50 +01:00 committed by Xiang Xiao
parent 6cb649ecf6
commit fb861c0a29
13 changed files with 1274 additions and 4 deletions
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2
arch/arm/src/nrf52/hardware/nrf52_saadc.h
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@ -43,7 +43,7 @@
#define NRF52_SAADC_EVENTS_DONE_OFFSET 0x0108 /* A conversion task has been completed */
#define NRF52_SAADC_EVENTS_RESDONE_OFFSET 0x010c /* Result ready for transfer to RAM */
#define NRF52_SAADC_EVENTS_CALDONE_OFFSET 0x0110 /* Calibration is complete */
#define NRF52_SAADC_EVENTS_STOPPED_OFFSET 0x0110 /* The SAADC has stopped */
#define NRF52_SAADC_EVENTS_STOPPED_OFFSET 0x0114 /* The SAADC has stopped */
#define NRF52_SAADC_EVENTS_CHLIMH_OFFSET(x) (0x118 + ((x) * 0x8)) /* Limit high event for channel x */
#define NRF52_SAADC_EVENTS_CHLIML_OFFSET(x) (0x11c + ((x) * 0x8)) /* Limit low event for channel x */
#define NRF52_SAADC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */

2
arch/arm/src/nrf52/hardware/nrf52_tim.h
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@ -100,7 +100,7 @@
/* PRESCALER Register */
#define TIM_PRESCALER_SHIFT (0) /* Bits 0-3: Prescaler value */
#define TIM_PRESCALER_MAX (0xf)
#define TIM_PRESCALER_MAX (9)
#define TIM_PRESCALER_MASK (TIM_PRESCALER_MAX << TIM_PRESCALER_SHIFT)
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H */

2
arch/arm/src/nrf52/hardware/nrf52_wdt.h
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@ -34,8 +34,6 @@
/* WDT Register Offsets *****************************************************/
/* Registers for the WDT function: */
#define NRF52_WDT_TASKS_START_OFFSET 0x0000 /* Start the watchdog */
#define NRF52_WDT_EVENTS_TIMEOUT_OFFSET 0x0100 /* Watchdog timeout */
#define NRF52_WDT_INTENSET_OFFSET 0x0304 /* Enable interrupt */

61
arch/arm/src/nrf53/hardware/nrf53_dppi.h Normal file
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@ -0,0 +1,61 @@
/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_dppi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_DPPI_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_DPPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets for DPPI ************************************************/
#define NRF53_DPPI_TASK_CHGEN_OFFSET(x) (0x000 + (x * 0x8)) /* Enable channel group x */
#define NRF53_DPPI_TASK_CHGDIS_OFFSET(x) (0x004 + (x * 0x8)) /* Disable channel group x */
#define NRF53_DPPI_TASK_SUBCHGEN_OFFSET(x) (0x080 + (x * 0x8)) /* Subscribe configuration for task CHG.EN */
#define NRF53_DPPI_TASK_SUBCHGDIS_OFFSET(x) (0x084 + (x * 0x8)) /* Subscribe configuration for task CHG.DIS */
#define NRF53_DPPI_CHEN_OFFSET (0x500) /* Channel enable register */
#define NRF53_DPPI_CHENSET_OFFSET (0x504) /* Channel enable set register */
#define NRF53_DPPI_CHENCLR_OFFSET (0x508) /* Channel enable clear register*/
#define NRF53_DPPI_CHG_OFFSET(x) (0x800 + (x * 0x4)) /* Channel group x */
/* Register addresses for DPPI **********************************************/
#define NRF53_DPPI_CHEEP(x) (NRF53_DPPI_BASE + NRF53_DPPI_CHEEP_OFFSET(x))
#define NRF53_DPPI_CHTEP(x) (NRF53_DPPI_BASE + NRF53_DPPI_CHTEP_OFFSET(x))
#define NRF53_DPPI_SUBCHGEN(x) (NRF53_DPPI_BASE + NRF53_DPPI_SUBCHGEN_OFFSET(x))
#define NRF53_DPPI_SUBCHGDIS(x) (NRF53_DPPI_BASE + NRF53_DPPI_SUBCHGDIS_OFFSET(x))
#define NRF53_DPPI_CHEN (NRF53_DPPI_BASE + NRF53_DPPI_CHEN_OFFSET)
#define NRF53_DPPI_CHENSET (NRF53_DPPI_BASE + NRF53_DPPI_CHENSET_OFFSET)
#define NRF53_DPPI_CHENCLR (NRF53_DPPI_BASE + NRF53_DPPI_CHENCLR_OFFSET)
#define NRF53_DPPI_CHG(x) (NRF53_DPPI_BASE + NRF53_DPPI_CHG_OFFSET(x))
/* Register Bitfield Definitions for DPPI ***********************************/
#define DPPI_CHEN_CH(x) (1 << x) /* Enable or disable channel x */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_DPPI_H */

95
arch/arm/src/nrf53/hardware/nrf53_gpioe.h Normal file
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@ -0,0 +1,95 @@
/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_gpioe.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_GPIOTE_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_GPIOTE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets for GPIOTE **********************************************/
#define NRF53_GPIOTE_TASKS_OUT_OFFSET(x) (0x0000 + (0x04 * x)) /* TASKS_OUT[x] */
#define NRF53_GPIOTE_TASKS_SET_OFFSET(x) (0x0030 + (0x04 * x)) /* TASKS_SET[x] */
#define NRF53_GPIOTE_TASKS_CLR_OFFSET(x) (0x0060 + (0x04 * x)) /* TASKS_CLR[x] */
/* todo: subscribe */
#define NRF53_GPIOTE_EVENTS_IN_OFFSET(x) (0x0100 + (0x04 * x)) /* EVENTS_IN[x] */
#define NRF53_GPIOTE_EVENTS_PORT_OFFSET 0x017c /* EVENTS_PORT */
/* todo: publish */
#define NRF53_GPIOTE_INTENSET_OFFSET 0x0304 /* INTENSET */
#define NRF53_GPIOTE_INTENCLR_OFFSET 0x0308 /* INTENCLR */
#define NRF53_GPIOTE_CONFIG_OFFSET(x) (0x0510 + (0x04 * x)) /* CONFIG[x] */
/* Register addresses for GPIOTE ********************************************/
#define NRF53_GPIOTE_TASKS_OUT(x) (NRF53_GPIOTE_BASE + NRF53_GPIOTE_TASKS_OUT_OFFSET(x))
#define NRF53_GPIOTE_TASKS_SET(x) (NRF53_GPIOTE_BASE + NRF53_GPIOTE_TASKS_SET_OFFSET(x))
#define NRF53_GPIOTE_TASKS_CLR(x) (NRF53_GPIOTE_BASE + NRF53_GPIOTE_TASKS_CLR_OFFSET(x))
#define NRF53_GPIOTE_EVENTS_IN(x) (NRF53_GPIOTE_BASE + NRF53_GPIOTE_EVENTS_IN_OFFSET(x))
#define NRF53_GPIOTE_EVENTS_PORT (NRF53_GPIOTE_BASE + NRF53_GPIOTE_EVENTS_PORT_OFFSET)
#define NRF53_GPIOTE_INTENSET (NRF53_GPIOTE_BASE + NRF53_GPIOTE_INTENSET_OFFSET)
#define NRF53_GPIOTE_INTENCLR (NRF53_GPIOTE_BASE + NRF53_GPIOTE_INTENCLR_OFFSET)
#define NRF53_GPIOTE_CONFIG(x) (NRF53_GPIOTE_BASE + NRF53_GPIOTE_CONFIG_OFFSET(x))
/* Register offsets for GPIOTE **********************************************/
/* EVENT_IN Register */
#define GPIOTE_EVENT_IN_EVENT (1 << 0) /* Bit 0: Event generated from pin */
/* INTENSET/INTENCLR Register */
#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */
#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT)
# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK)
#define GPIOTE_INT_PORT_SHIFT 31 /* Bit 31: Enable interrupt for event PORT */
#define GPIOTE_INT_PORT (1 << GPIOTE_INT_PORT_SHIFT)
/* CONFIG Register */
#define GPIOTE_CONFIG_MODE_SHIFT 0 /* Bits 0-1: Mode */
#define GPIOTE_CONFIG_MODE_MASK (0x3 << GPIOTE_CONFIG_MODE_SHIFT)
# define GPIOTE_CONFIG_MODE_DIS (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 0: Disabled */
# define GPIOTE_CONFIG_MODE_EV (0x1 << GPIOTE_CONFIG_MODE_SHIFT) /* 1: Event */
# define GPIOTE_CONFIG_MODE_TS (0x3 << GPIOTE_CONFIG_MODE_SHIFT) /* 2: Task */
#define GPIOTE_CONFIG_PSEL_SHIFT (8) /* Bits 8-12: GPIO number */
#define GPIOTE_CONFIG_PSEL_MASK (0x1f << GPIOTE_CONFIG_PSEL_SHIFT)
#define GPIOTE_CONFIG_PORT_SHIFT (13) /* Bit 13: GPIO port */
#define GPIOTE_CONFIG_POL_SHIFT (16) /* Bits 16-17: Polarity */
#define GPIOTE_CONFIG_POL_MASK (0x3 << GPIOTE_CONFIG_POL_SHIFT)
# define GPIOTE_CONFIG_POL_NONE (0x0 << GPIOTE_CONFIG_POL_SHIFT) /* 0: None */
# define GPIOTE_CONFIG_POL_LTH (0x1 << GPIOTE_CONFIG_POL_SHIFT) /* 1: LoToHi */
# define GPIOTE_CONFIG_POL_HTL (0x2 << GPIOTE_CONFIG_POL_SHIFT) /* 2: HiToLo */
# define GPIOTE_CONFIG_POL_TG (0x3 << GPIOTE_CONFIG_POL_SHIFT) /* 3: Toggle */
#define GPIOTE_CONFIG_OUTINIT_SHIFT (20) /* Bit 20: Initial value */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_GPIOTE_H */

83
arch/arm/src/nrf53/hardware/nrf53_nvmc.h Normal file
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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_nvmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_NVMC_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_NVMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* NVMC Register Offsets ****************************************************/
/* Registers for the NVMC */
#define NRF53_NVMC_READY_OFFSET 0x400 /* Ready flag */
#define NRF53_NVMC_READYNEXT_OFFSET 0x408 /* Ready flag */
#define NRF53_NVMC_CONFIG_OFFSET 0x504 /* Configuration register */
#define NRF53_NVMC_ERASEALL_OFFSET 0x50c /* Register for erasing all non-volatile user memory */
#define NRF53_NVMC_ERASEPAGEPARTIALCFG_OFFSET 0x50c /* Register for partial erase configuration */
#define NRF53_NVMC_ICACHECNF_OFFSET 0x540 /* I-Code cache configuration register */
#define NRF53_NVMC_IHIT_OFFSET 0x548 /* I-Code cache hit counter. */
#define NRF53_NVMC_IMISS_OFFSET 0x54c /* I-Code cache miss counter */
#define NRF53_NVMC_CONFIGNS_OFFSET 0x584 /* Non-secure configuration register */
#define NRF53_NVMC_WRITEUICRNS_OFFSET 0x588 /* Non-secure APPROTECT enable register */
/* NVMC Register Addresses **************************************************/
#define NRF53_NVMC_READY (NRF53_NVMC_BASE + NRF53_NVMC_READY_OFFSET)
#define NRF53_NVMC_READYNEXT (NRF53_NVMC_BASE + NRF53_NVMC_READYNEXT_OFFSET)
#define NRF53_NVMC_CONFIG (NRF53_NVMC_BASE + NRF53_NVMC_CONFIG_OFFSET)
#define NRF53_NVMC_ERASEALL (NRF53_NVMC_BASE + NRF53_NVMC_ERASEALL_OFFSET)
#define NRF53_NVMC_ERASEPAGEPARTIALCFG (NRF53_NVMC_BASE + NRF53_NVMC_ERASEPAGEPARTIALCFG_OFFSET)
#define NRF53_NVMC_ICACHECNF (NRF53_NVMC_BASE + NRF53_NVMC_ICACHECNF_OFFSET)
#define NRF53_NVMC_IHIT (NRF53_NVMC_BASE + NRF53_NVMC_IHIT_OFFSET)
#define NRF53_NVMC_IMISS (NRF53_NVMC_BASE + NRF53_NVMC_IMISS_OFFSET)
#define NRF53_NVMC_CONFIGNS (NRF53_NVMC_BASE + NRF53_NVMC_CONFIGNS_OFFSET)
#define NRF53_NVMC_WRITEUICRNS (NRF53_NVMC_BASE + NRF53_NVMC_WRITEUICRNS_OFFSET)
/* NVMC Register Bitfield Definitions ***************************************/
/* READY Register */
#define NVMC_READY_READY (1 << 0) /* NVMC is ready */
/* CONFIG Register */
#define NVMC_CONFIG_SHIFT (0)
#define NVMC_CONFIG_MASK (3 << NVMC_CONFIG_SHIFT)
#define NVMC_CONFIG_REN (0 << NVMC_CONFIG_SHIFT) /* Read-only access */
#define NVMC_CONFIG_WEN (1 << NVMC_CONFIG_SHIFT) /* Write Enabled */
#define NVMC_CONFIG_EEN (2 << NVMC_CONFIG_SHIFT) /* Erase Enabled */
#define NVMC_CONFIG_PEEN (4 << NVMC_CONFIG_SHIFT) /* Partial erase enabled */
/* ICACHECNF Register */
#define NVMC_ICACHECNF_CACHEEN (1 << 0) /* Cache enable */
#define NVMC_ICACHECNF_CACHEPROFEN (1 << 8) /* Cache profiling enable */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_NVMC_H */

110
arch/arm/src/nrf53/hardware/nrf53_rtc.h Normal file
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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_RTC_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets for RTC *************************************************/
#define NRF53_RTC_TASKS_START_OFFSET 0x0000 /* Start RTC counter */
#define NRF53_RTC_TASKS_STOP_OFFSET 0x0004 /* Stop RTC counter */
#define NRF53_RTC_TASKS_CLEAR_OFFSET 0x0008 /* Clear RTC counter */
#define NRF53_RTC_TASKS_TRIGOVRFLW_OFFSET 0x000c /* Clear Set counter to 0xfffff0 */
/* TODO: 0x040 - 0x0c */
#define NRF53_RTC_EVENTS_TICK_OFFSET 0x0100 /* Event on counter increment */
#define NRF53_RTC_EVENTS_OVRFLW_OFFSET 0x0104 /* Event on counter overflow */
#define NRF53_RTC_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 0x04)) /* Compare event on CC[x] match */
/* TODO: 0x180 - 0x200 */
#define NRF53_RTC_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_RTC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_RTC_EVTEN_OFFSET 0x0340 /* Enable or disable event routing */
#define NRF53_RTC_EVTENSET_OFFSET 0x0344 /* Enable event routing */
#define NRF53_RTC_EVTENCLR_OFFSET 0x0348 /* Disable event routing */
#define NRF53_RTC_COUNTER_OFFSET 0x0504 /* Current counter value */
#define NRF53_RTC_PRESCALER_OFFSET 0x0508 /* 12 bit prescaler for counter frequency */
#define NRF53_RTC_CC_OFFSET(x) (0x0540 + ((x) * 0x04)) /* Compare register x */
/* Register offsets for RTC *************************************************/
/* TASKS_START Register */
#define RTC_TASKS_START (1 << 0) /* Bit 0: Start RTC counter */
/* TASKS_STOP Register */
#define RTC_TASKS_STOP (1 << 0) /* Bit 0: Stop RTC counter */
/* TASKS_CLEAR Register */
#define RTC_TASKS_CLEAR (1 << 0) /* Bit 0: Clear RTC counter */
/* TASKS_TRIGOVRFLW Register */
#define RTC_TASKS_TRIGOVRFLW (1 << 0) /* Bit 0: Set counter to 0xfffff0 */
/* EVENTS_TICK Register */
#define RTC_EVENTS_TICK (1 << 0) /* Bit 0: Event on counter increment */
/* EVENTS_OVRFLW Register */
#define RTC_EVENTS_OVRFLW (1 << 0) /* Bit 0: Event on counter overflow */
/* EVENTS_COMPARE Register */
#define RTC_EVENTS_COMPARE (1 << 0) /* Bit 0: Eompare event on CC[x] match */
/* INTENSET/INTENCLR Register */
#define RTC_INT_TICK (1 << 0) /* Bit 0: TICK interrupt*/
#define RTC_INT_OVRFLW (1 << 1) /* Bit 1: OVRFLW interrupt */
#define RTC_INT_COMPARE(x) (1 << (16 + (x))) /* Bit 16-19: COMPARE[x] interrupt */
/* EVTEN/EVTENSET/EVTSENCLR Register */
#define RTC_EVTEN_TICK (1 << 0) /* Bit 0: TICK event */
#define RTC_EVTEN_OVRFLW (1 << 1) /* Bit 1: OVRFLW event */
#define RTC_EVTEN_COMPARE(x) (1 << (16 + (x))) /* Bit 16-19: COMPARE[x] event */
/* COUNTER Register */
#define RTC_COUNTER_MASK (0x00ffffff) /* Bits 0-23: Counter value */
/* PRESCALER Register */
#define RTC_PRESCALER_MASK (0x00000fff) /* Bits 0-11: Prescaler value */
#define RTC_PRESCALER_MAX (0x00000fff)
/* CC Register */
#define RTC_CC_MASK (0x00ffffff) /* Bits 0-23: Compare register */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_RTC_H */

192
arch/arm/src/nrf53/hardware/nrf53_saadc.h Normal file
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/***************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_saadc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
***************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SAADC_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SAADC_H
/***************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/***************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Register offsets for SAADC **********************************************/
#define NRF53_SAADC_TASKS_START_OFFSET 0x0000 /* Start the SAADCM */
#define NRF53_SAADC_TASKS_SAMPLE_OFFSET 0x0004 /* Takes one SAADC sample */
#define NRF53_SAADC_TASKS_STOP_OFFSET 0x0008 /* Stop the SAADC */
#define NRF53_SAADC_TASKS_CALOFFSET_OFFSET 0x000c /* Starts offset auto-calibration */
/* TODO: 0x080 - 0x08c */
#define NRF53_SAADC_EVENTS_STARTED_OFFSET 0x0100 /* The SAADC has started */
#define NRF53_SAADC_EVENTS_END_OFFSET 0x0104 /* The SAADC has filled up the result buffer */
#define NRF53_SAADC_EVENTS_DONE_OFFSET 0x0108 /* A conversion task has been completed */
#define NRF53_SAADC_EVENTS_RESDONE_OFFSET 0x010c /* Result ready for transfer to RAM */
#define NRF53_SAADC_EVENTS_CALDONE_OFFSET 0x0110 /* Calibration is complete */
#define NRF53_SAADC_EVENTS_STOPPED_OFFSET 0x0114 /* The SAADC has stopped */
#define NRF53_SAADC_EVENTS_CHLIMH_OFFSET(x) (0x118 + ((x) * 0x8)) /* Limit high event for channel x */
#define NRF53_SAADC_EVENTS_CHLIML_OFFSET(x) (0x11c + ((x) * 0x8)) /* Limit low event for channel x */
/* TODO: 0x180 - 0x19c */
#define NRF53_SAADC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
#define NRF53_SAADC_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_SAADC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_SAADC_STATUS_OFFSET 0x0400 /* Status */
#define NRF53_SAADC_ENABLE_OFFSET 0x0500 /* Enable or disable SAADC */
#define NRF53_SAADC_CHPSELP_OFFSET(x) (0x510 + ((x) * 0x10)) /* Input positive pin for CH[x] */
#define NRF53_SAADC_CHPSELN_OFFSET(x) (0x514 + ((x) * 0x10)) /* Input negative pin for CH[x] */
#define NRF53_SAADC_CHCONFIG_OFFSET(x) (0x518 + ((x) * 0x10)) /* Input configuration for CH[x] */
#define NRF53_SAADC_CHLIMIT_OFFSET(x) (0x51c + ((x) * 0x10)) /* High/low limits for event monitoring of a CH[x] */
#define NRF53_SAADC_RESOLUTION_OFFSET 0x05f0 /* Resolution configuration */
#define NRF53_SAADC_OVERSAMPLE_OFFSET 0x05f4 /* Oversampling configuration */
#define NRF53_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continuous sample rate */
#define NRF53_SAADC_PTR_OFFSET 0x062c /* Data pointer */
#define NRF53_SAADC_MAXCNT_OFFSET 0x0630 /* Maximum number of 16-bit samples */
#define NRF53_SAADC_AMOUNT_OFFSET 0x0634 /* Number of 16-bit samples written to buffer */
/* Register Bitfield Definitions for SAADC *********************************/
/* INTEN/INTENSET/INTENCLR Register */
#define SAADC_INT_STARTED (1 << 0) /* Bit 0: Interrupt for event STARTED */
#define SAADC_INT_END (1 << 1) /* Bit 1: Interrupt for event END */
#define SAADC_INT_DONE (1 << 2) /* Bit 2: Interrupt for event DONE */
#define SAADC_INT_RESDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
#define SAADC_INT_CALDONE (1 << 4) /* Bit 4: Interrupt for event CALIBRATEDONE */
#define SAADC_INT_STOPPED (1 << 5) /* Bit 5: Interrupt for event STOPPED */
#define SAADC_INT_CHXLIMH(x) (1 << (x + 0x6)) /* Bit (x+6): Interrupt for event CHxLIMITH */
#define SAADC_INT_CHXLIML(x) (1 << (x + 0x7)) /* Bit (x+7): Interrupt for event CHxLIMITL */
/* STATUS Register */
#define SAADC_STATUS_READY (0) /* Bit 0: SAADC is ready */
#define SAADC_STATUS_BUSY (1 << 0) /* Bit 0: SAADC is busy */
/* ENABLE Register */
#define SAADC_ENABLE_DIS (0) /* Bit 0: Disable SAADC */
#define SAADC_ENABLE_EN (1 << 0) /* Bit 0: Enable SAADC */
/* CH[n] PSELx Register */
#define SAADC_CHPSEL_SHIFT (0) /* Bits 0-4: Input positive pin selection for CH[x] */
#define SAADC_CHPSEL_MASK (0xf << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_NC (0x0 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN0 (0x1 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN1 (0x2 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN2 (0x3 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN3 (0x4 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN4 (0x5 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN5 (0x6 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN6 (0x7 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_IN7 (0x8 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_VDD (0x9 << SAADC_CHPSEL_SHIFT)
# define SAADC_CHPSEL_VDDHDIV5 (0xd << SAADC_CHPSEL_SHIFT)
/* CH[n] CONFIG Register */
#define SAADC_CONFIG_RESP_SHIFT (0) /* Bits 0-2: Positive channel resistor control */
#define SAADC_CONFIG_RESP_MASK (0x3 << SAADC_CONFIG_RESP_SHIFT)
# define SAADC_CONFIG_RESP_NONE (0x0 << SAADC_CONFIG_RESP_SHIFT)
# define SAADC_CONFIG_RESP_PD (0x1 << SAADC_CONFIG_RESP_SHIFT)
# define SAADC_CONFIG_RESP_PU (0x2 << SAADC_CONFIG_RESP_SHIFT)
# define SAADC_CONFIG_RESP_VDD1P2 (0x3 << SAADC_CONFIG_RESP_SHIFT)
#define SAADC_CONFIG_RESN_SHIFT (4) /* Bits 4-5: Negative channel resistor control */
#define SAADC_CONFIG_RESN_MASK (0x3 << SAADC_CONFIG_RESN_SHIFT)
# define SAADC_CONFIG_RESN_NONE (0x0 << SAADC_CONFIG_RESN_SHIFT)
# define SAADC_CONFIG_RESN_PD (0x1 << SAADC_CONFIG_RESN_SHIFT)
# define SAADC_CONFIG_RESN_PU (0x2 << SAADC_CONFIG_RESN_SHIFT)
# define SAADC_CONFIG_RESN_VDD1P2 (0x3 << SAADC_CONFIG_RESN_SHIFT)
#define SAADC_CONFIG_GAIN_SHIFT (8) /* Bits 8-10: Gain control */
#define SAADC_CONFIG_GAIN_MASK (0x7 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_1P6 (0x0 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_1P5 (0x1 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_1P4 (0x2 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_1P3 (0x3 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_1P2 (0x4 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_1 (0x5 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_2 (0x6 << SAADC_CONFIG_GAIN_SHIFT)
# define SAADC_CONFIG_GAIN_4 (0x7 << SAADC_CONFIG_GAIN_SHIFT)
#define SAADC_CONFIG_REFSEL_INTERNAL (0 << 12) /* Bit 12: Internal reference (0.6V) */
#define SAADC_CONFIG_REFSEL_VDD1P4 (1 << 12) /* Bit 12: VDD/4 as reference */
#define SAADC_CONFIG_TACQ_SHIFT (16) /* Bits 16-18: Acquisition time */
#define SAADC_CONFIG_TACQ_MASK (0x7 << SAADC_CONFIG_TACQ_SHIFT)
# define SAADC_CONFIG_TACQ_3US (0x0 << SAADC_CONFIG_TACQ_SHIFT)
# define SAADC_CONFIG_TACQ_5US (0x1 << SAADC_CONFIG_TACQ_SHIFT)
# define SAADC_CONFIG_TACQ_10US (0x2 << SAADC_CONFIG_TACQ_SHIFT)
# define SAADC_CONFIG_TACQ_15US (0x3 << SAADC_CONFIG_TACQ_SHIFT)
# define SAADC_CONFIG_TACQ_20US (0x4 << SAADC_CONFIG_TACQ_SHIFT)
# define SAADC_CONFIG_TACQ_40US (0x5 << SAADC_CONFIG_TACQ_SHIFT)
#define SAADC_CONFIG_MODE_SE (0 << 20) /* Bit 20: Single-ended */
#define SAADC_CONFIG_MODE_DIFF (1 << 20) /* Bit 20: Differential */
#define SAADC_CONFIG_BURS_DIS (0 << 24) /* Bit 24: Burst mode is disabled */
#define SAADC_CONFIG_BURS_EN (1 << 24) /* Bit 24: Burst mode is enabled */
/* CH[n] LIMIT Register */
#define SAADC_CHLIMIT_LOW_SHIFT (0) /* Bits 0-15: Low level limit */
#define SAADC_CHLIMIT_LOW_MASK (0xffff << SAADC_CHLIMIT_LOW_SHIFT)
#define SAADC_CHLIMIT_HIGH_SHIFT (16) /* Bits 0-15: High level limit */
#define SAADC_CHLIMIT_HIGH_MASK (0xffff << SAADC_CHLIMIT_HIGH_SHIFT)
/* RESOLUTION Register */
#define SAADC_RESOLUTION_SHIFT (0) /* Bits 0-2: SAADC resolution */
#define SAADC_RESOLUTION_MASK (0xf << SAADC_RESOLUTION_SHIFT)
# define SAADC_RESOLUTION_8BIT (0x0 << SAADC_RESOLUTION_SHIFT)
# define SAADC_RESOLUTION_10BIT (0x1 << SAADC_RESOLUTION_SHIFT)
# define SAADC_RESOLUTION_12BIT (0x2 << SAADC_RESOLUTION_SHIFT)
# define SAADC_RESOLUTION_14BIT (0x3 << SAADC_RESOLUTION_SHIFT)
/* OVERSAMPLE Register */
#define SAADC_OVERSAMPLE_SHIFT (0) /* Bit 0-3: Oversample control */
#define SAADC_OVERSAMPLE_MASK (0xf << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_NONE (0x0 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_2X (0x1 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_4X (0x2 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_8X (0x3 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_16X (0x4 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_32X (0x5 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_64X (0x6 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_128X (0x7 << SAADC_OVERSAMPLE_SHIFT)
# define SAADC_OVERSAMPLE_256X (0x8 << SAADC_OVERSAMPLE_SHIFT)
/* SAMPLERATE Register */
#define SAADC_SAMPLERATE_CC_SHIFT (0) /* Bits 0-10: Capture and compare value */
#define SAADC_SAMPLERATE_CC_MASK (0x7ff << SAADC_SAMPLERATE_CC_SHIFT)
#define SAADC_SAMPLERATE_MODE_TASK (0 << 12) /* Bit 12: Rate is controlled from SAMPLE task */
#define SAADC_SAMPLERATE_MODE_TIMERS (1 << 12) /* Bit 12: Rate is controlled from local timer */
/* MAXCNT Register */
#define SAADC_MAXCNT_SHIFT (0) /* Bits 0-14: Maximum of 16-bit samples written to output buffer */
#define SAADC_MAXCNT_MASK (0x7fff)
/* AMOUNT Register */
#define SAADC_AMOUNT_SHIFT (0) /* Bits 0-14: Number of 16-bit samples written to output buffer */
#define SAADC_AMOUNT_MASK (0x7fff)
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SAADC_H */

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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPI_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets for SPI master (SPIM) ***********************************/
#define NRF53_SPIM_TASK_START_OFFSET (0x0010) /* Start SPI transaction */
#define NRF53_SPIM_TASK_STOP_OFFSET (0x0014) /* Stop SPI transaction */
#define NRF53_SPIM_TASK_SUSPEND_OFFSET (0x001c) /* Suspend SPI transaction */
#define NRF53_SPIM_TASK_RESUME_OFFSET (0x0020) /* Resume SPI transaction */
/* TODO: 0x090 - 0x0a0 */
#define NRF53_SPIM_EVENTS_STOPPED_OFFSET (0x0104) /* SPI transaction has stopped */
#define NRF53_SPIM_EVENTS_ENDRX_OFFSET (0x0110) /* End of RXD buffer reached */
#define NRF53_SPIM_EVENTS_END_OFFSET (0x0118) /* End of RXD buffer and TXD buffer reached */
#define NRF53_SPIM_EVENTS_ENDTX_OFFSET (0x0120) /* End of TXD buffer reached */
#define NRF53_SPIM_EVENTS_STARTED_OFFSET (0x014c) /* Transaction started */
/* TODO: 0x184 - 0x1cc */
#define NRF53_SPIM_SHORTS_OFFSET (0x0200) /* Shortcuts between local events and tasks */
#define NRF53_SPIM_INTENSET_OFFSET (0x0304) /* Enable interrupt */
#define NRF53_SPIM_INTENCLR_OFFSET (0x0308) /* Disable interrupt */
#define NRF53_SPIM_STALLSTAT_OFFSET (0x0400) /* Stall status for EasyDMA RAM accesses */
#define NRF53_SPIM_ENABLE_OFFSET (0x0500) /* Enable SPIM */
#define NRF53_SPIM_PSELSCK_OFFSET (0x0508) /* Pin select for SCK */
#define NRF53_SPIM_PSELMOSI_OFFSET (0x050c) /* Pin select for MOSI */
#define NRF53_SPIM_PSELMISO_OFFSET (0x0510) /* Pin select for MISO */
#define NRF53_SPIM_PSELCSN_OFFSET (0x0514) /* Pin select for CSN */
#define NRF53_SPIM_FREQUENCY_OFFSET (0x0524) /* SPI frequency. */
#define NRF53_SPIM_RXDPTR_OFFSET (0x0534) /* Data pointer */
#define NRF53_SPIM_RXDMAXCNT_OFFSET (0x0538) /* Maximum number of bytes in receive buffer */
#define NRF53_SPIM_RXDMAMOUNT_OFFSET (0x053c) /* Number of bytes transferred in the last transaction */
#define NRF53_SPIM_RXDLIST_OFFSET (0x0540) /* RXD EasyDMA list type */
#define NRF53_SPIM_TXDPTR_OFFSET (0x0544) /* Data pointer */
#define NRF53_SPIM_TXDMAXCNT_OFFSET (0x0548) /* Number of bytes in transmit buffer */
#define NRF53_SPIM_TXDAMOUNT_OFFSET (0x054c) /* Number of bytes transferred in the last transaction */
#define NRF53_SPIM_TXDLIST_OFFSET (0x0550) /* TXD EasyDMA list type */
#define NRF53_SPIM_CONFIG_OFFSET (0x0554) /* Configuration register */
#define NRF53_SPIM_RXDELAY_OFFSET (0x0560) /* Sample delay for input serial data on MISO */
#define NRF53_SPIM_CSNDUR_OFFSET (0x0564) /* IFTIMING.CSNDUR */
#define NRF53_SPIM_CSNPOL_OFFSET (0x0568) /* Polarity of CSN output */
#define NRF53_SPIM_PSELDCX_OFFSET (0x056c) /* Pin select for DCX signal */
#define NRF53_SPIM_DCXCNT_OFFSET (0x0570) /* DCX configuration */
#define NRF53_SPIM_ORC_OFFSET (0x05c0) /* ORC */
/* Register offsets for SPI slave (SPIS) ************************************/
/* TODO: 0x024 - 0x1a8 */
#define NRF53_SPIS_SHORTS_OFFSET (0x0200) /* Shortcuts between local events and tasks */
#define NRF53_SPIS_INTENSET_OFFSET (0x0304) /* Enable interrupt */
#define NRF53_SPIS_INTENCLR_OFFSET (0x0308) /* Disable interrupt */
#define NRF53_SPIS_SEMSTAT_OFFSET (0x0400) /* Semaphore status register */
#define NRF53_SPIS_STATUS_OFFSET (0x0440) /* Status from last transaction */
#define NRF53_SPIS_ENABLE_OFFSET (0x0500) /* Enable SPIS */
#define NRF53_SPIS_PSELSCK_OFFSET (0x0508) /* Pin select for SCK */
#define NRF53_SPIS_PSELMOSI_OFFSET (0x050c) /* Pin select for MOSI signal */
#define NRF53_SPIS_PSELMISO_OFFSET (0x0510) /* Pin select for MISO signal */
#define NRF53_SPIS_PSELCSN_OFFSET (0x0514) /* Pin select for CSN */
#define NRF53_SPIS_RXDPTR_OFFSET (0x0534) /* Data pointer */
#define NRF53_SPIS_RXDMAXCNT_OFFSET (0x0538) /* Maximum number of bytes in receive buffer */
#define NRF53_SPIS_RXDMAMOUNT_OFFSET (0x053c) /* Number of bytes transferred in the last transaction */
#define NRF53_SPIS_RXDLIST_OFFSET (0x0540) /* RXD EasyDMA list type */
#define NRF53_SPIS_TXDPTR_OFFSET (0x0544) /* Data pointer */
#define NRF53_SPIS_TXDMAXCNT_OFFSET (0x0548) /* Number of bytes in transmit buffer */
#define NRF53_SPIS_TXDAMOUNT_OFFSET (0x054c) /* Number of bytes transferred in the last transaction */
#define NRF53_SPIS_TXDLIST_OFFSET (0x0550) /* TXD EasyDMA list type */
#define NRF53_SPIS_CONFIG_OFFSET (0x0554) /* Configuration register */
#define NRF53_SPIS_DEF_OFFSET (0x055c) /* Default character */
#define NRF53_SPIS_ORC_OFFSET (0x05c0) /* Over-read character */
/* Register Bitfield Definitions for SPIM ***********************************/
/* TASKS_START Register */
#define SPIM_TASKS_START (1 << 0) /* Bit 0: Start SPI transaction */
/* TASKS_STOP Register */
#define SPIM_TASKS_STOP (1 << 0) /* Bit 0: Stop SPI transaction */
/* TASKS_SUSPEND Register */
#define SPIM_TASKS_SUSPEND (1 << 0) /* Bit 0: Suspend SPI transaction */
/* TASKS_RESUME Register */
#define SPIM_TASKS_RESUME (1 << 0) /* Bit 0: Resume SPI transaction */
/* EVENTS_STOPPED Register */
#define SPIM_EVENTS_STOPPED (1 << 0) /* Bit 0: SPI transaction has stopped */
/* EVENTS_ENDRX Register */
#define SPIM_EVENTS_ENDRX (1 << 0) /* Bit 0: End of RXD buffer reached */
/* EVENTS_END Register */
#define SPIM_EVENTS_END (1 << 0) /* Bit 0: End of RXD buffer and TXD buffer reached */
/* EVENTS_ENDTX Register */
#define SPIM_EVENTS_ENDTX (1 << 0) /* Bit 0: End of TXD buffer reached */
/* EVENTS_STARTED Register */
#define SPIM_EVENTS_STARTED (1 << 0) /* Bit 0: Transaction started */
/* SHORTS Register */
#define SPIM_SHORTS_ENDSTART (1 << 0) /* Bit 0: Shortcut between event END and task START */
/* INTENSET/INTENCLR Register */
#define SPIM_INT_STOPPED (1 << 1) /* Bit 1: Enable interrupt for STOPPED */
#define SPIM_INT_ENDRX (1 << 4) /* Bit 4: Enable interrupt for ENDRX */
#define SPIM_INT_END (1 << 6) /* Bit 6: Enable interrupt for END */
#define SPIM_INT_ENDTX (1 << 8) /* Bit 8: Enable interrupt for ENDTX */
#define SPIM_INT_STARTED (1 << 19) /* Bit 19: Enable interrupt for STARTED */
/* STALLLSTAT Register */
#define SPIM_STALLSTAT_RX (1 << 0) /* Bit 0: Stall status for EasyDMA RAM reads */
#define SPIM_STALLSTAT_TX (1 << 1) /* Bit 1: Stall status for EasyDMA RAM writes */
/* ENABLE Register */
#define SPIM_ENABLE_DIS (0) /* Disable SPIM */
#define SPIM_ENABLE_EN (0x7 << 0) /* Enable SPIM */
/* PSEL* Registers */
#define SPIM_PSEL_PIN_SHIFT (0) /* Bits 0-4: SCK pin number */
#define SPIM_PSEL_PIN_MASK (0x1f << SPIM_PSELSCK_PIN_SHIFT)
#define SPIM_PSEL_PORT_SHIFT (5) /* Bit 5: SCK port number */
#define SPIM_PSEL_PORT_MASK (0x1 << SPIM_PSELSCK_PORT_SHIFT)
#define SPIM_PSEL_CONNECTED (1 << 31) /* Bit 31: Connection */
#define SPIM_PSEL_RESET (0xffffffff)
/* FREQUENCY Register */
#define SPIM_FREQUENCY_125KBPS (0x02000000) /* 125 kbps */
#define SPIM_FREQUENCY_250KBPS (0x04000000) /* 250 kbps */
#define SPIM_FREQUENCY_500KBPS (0x08000000) /* 500 kbps */
#define SPIM_FREQUENCY_1MBPS (0x10000000) /* 1 Mbps */
#define SPIM_FREQUENCY_2MBPS (0x20000000) /* 2 Mbps */
#define SPIM_FREQUENCY_4MBPS (0x40000000) /* 4 Mbps */
#define SPIM_FREQUENCY_8MBPS (0x80000000) /* 8 Mbps */
#define SPIM_FREQUENCY_16MBPS (0x0A000000) /* 16 Mbps */
#define SPIM_FREQUENCY_32MBPS (0x14000000) /* 32 Mbps */
/* RXDMAXCNT Register */
#define SPIM_RXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in receive buffer */
#define SPIM_RXDMAXCNT_MASK (0xffff << SPIM_RXDMAXCNT_SHIFT)
/* RXDAMOUNT Register */
#define SPIM_RXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */
#define SPIM_RXDAMOUNT_MASK (0xffff << SPIM_RXDAMOUNT_SHIFT)
/* TXDMAXCNT Register */
#define SPIM_TXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in transmit buffer */
#define SPIM_TXDMAXCNT_MASK (0xffff << SPIM_TXDMAXCNT_MASK)
/* TXDAMOUNT Register */
#define SPIM_TXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */
#define SPIM_TXDAMOUNT_MASK (0xffff << SPIM_TXDAMOUNT_SHIFT)
/* CONFIG Register */
#define SPIM_CONFIG_ORDER (1 << 0) /* Bit 0: Bit order */
#define SPIM_CONFIG_CPHA (1 << 1) /* Bit 1: Serial clock phase */
#define SPIM_CONFIG_CPOL (1 << 2) /* Bit 2: Serial clock polarity */
/* PSELDCX Register */
#define SPIM_PSELDCX_PIN_SHIFT (0) /* Bits 0-4: DCX pin number */
#define SPIM_PSELDCX_PIN_MASK (0x1f << SPIM_PSELDCX_PIN_SHIFT)
#define SPIM_PSELDCX_PORT_SHIFT (5) /* Bit 5: SCK port number */
#define SPIM_PSELDCX_PORT_MASK (0x1 << SPIM_PSELDCX_PORT_SHIFT)
#define SPIM_PSELDCX_CONNECTED (1 << 31) /* Bit 31: Connection */
/* Register Bitfield Definitions for SPIS ***********************************/
/* TODO */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPI_H */

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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_temp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TEMP_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TEMP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define NRF53_TEMP_TASKS_START_OFFSET 0x0000 /* Start temperature measurement */
#define NRF53_TEMP_TASKS_STOP_OFFSET 0x0004 /* Stop temperature measurement */
#define NRF53_TEMP_SUBSCRIBE_START_OFFSET 0x0080 /* Subscribe configuration for task START */
#define NRF53_TEMP_SUBSCRIBE_STOP_OFFSET 0x0084 /* Subscribe configuration for task STOP */
#define NRF53_TEMP_EVENTS_DATARDY_OFFSET 0x0100 /* Temperature measurement complete, data ready */
#define NRF53_TEMP_PUBLISH_DATARDY_OFFSET 0x0100 /* Publish configuration for event DATARDY */
#define NRF53_TEMP_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_TEMP_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_TEMP_TEMP_OFFSET 0x0508 /* Temperature in degC */
#define NRF53_TEMP_A0_OFFSET 0x0520 /* Slope of 1st piece wise linear function */
#define NRF53_TEMP_A1_OFFSET 0x0524 /* Slope of 2nd piece wise linear function */
#define NRF53_TEMP_A2_OFFSET 0x0528 /* Slope of 3rd piece wise linear function */
#define NRF53_TEMP_A3_OFFSET 0x052C /* Slope of 4th piece wise linear function */
#define NRF53_TEMP_A4_OFFSET 0x0530 /* Slope of 5th piece wise linear function */
#define NRF53_TEMP_A5_OFFSET 0x0534 /* Slope of 6th piece wise linear function */
#define NRF53_TEMP_B0_OFFSET 0x0540 /* y-intercept of 1st piece wise linear function */
#define NRF53_TEMP_B1_OFFSET 0x0544 /* y-intercept of 2nd piece wise linear function */
#define NRF53_TEMP_B2_OFFSET 0x0548 /* y-intercept of 3rd piece wise linear function */
#define NRF53_TEMP_B3_OFFSET 0x054C /* y-intercept of 4th piece wise linear function */
#define NRF53_TEMP_B4_OFFSET 0x0550 /* y-intercept of 5th piece wise linear function */
#define NRF53_TEMP_B5_OFFSET 0x0554 /* y-intercept of 6th piece wise linear function */
#define NRF53_TEMP_T0_OFFSET 0x0560 /* End point of 1st piece wise linear function */
#define NRF53_TEMP_T1_OFFSET 0x0564 /* End point of 2nd piece wise linear function */
#define NRF53_TEMP_T2_OFFSET 0x0568 /* End point of 3rd piece wise linear function */
#define NRF53_TEMP_T3_OFFSET 0x056C /* End point of 4th piece wise linear function */
#define NRF53_TEMP_T4_OFFSET 0x0570 /* End point of 5th piece wise linear function */
/* Register definitions *****************************************************/
#define NRF53_TEMP_TASKS_START (NRF53_TEMP_BASE + NRF53_TEMP_TASKS_START_OFFSET)
#define NRF53_TEMP_TASKS_STOP (NRF53_TEMP_BASE + NRF53_TEMP_TASKS_STOP_OFFSET)
#define NRF53_TEMP_SUBSCRIBES_START (NRF53_TEMP_BASE + NRF53_TEMP_SUBSCRIBES_START_OFFSET)
#define NRF53_TEMP_SUBSCRIBES_STOP (NRF53_TEMP_BASE + NRF53_TEMP_SUBSCRIBES_STOP_OFFSET)
#define NRF53_TEMP_EVENTS_DATARDY (NRF53_TEMP_BASE + NRF53_TEMP_EVENTS_DATARDY_OFFSET)
#define NRF53_TEMP_INTENSET (NRF53_TEMP_BASE + NRF53_TEMP_INTENSET_OFFSET)
#define NRF53_TEMP_INTENCLR (NRF53_TEMP_BASE + NRF53_TEMP_INTENCLR_OFFSET)
#define NRF53_TEMP_TEMP (NRF53_TEMP_BASE + NRF53_TEMP_TEMP_OFFSET)
#define NRF53_TEMP_A0 (NRF53_TEMP_BASE + NRF53_TEMP_A0_OFFSET)
#define NRF53_TEMP_A1 (NRF53_TEMP_BASE + NRF53_TEMP_A1_OFFSET)
#define NRF53_TEMP_A2 (NRF53_TEMP_BASE + NRF53_TEMP_A2_OFFSET)
#define NRF53_TEMP_A3 (NRF53_TEMP_BASE + NRF53_TEMP_A3_OFFSET)
#define NRF53_TEMP_A4 (NRF53_TEMP_BASE + NRF53_TEMP_A4_OFFSET)
#define NRF53_TEMP_A5 (NRF53_TEMP_BASE + NRF53_TEMP_A5_OFFSET)
#define NRF53_TEMP_B0 (NRF53_TEMP_BASE + NRF53_TEMP_B0_OFFSET)
#define NRF53_TEMP_B1 (NRF53_TEMP_BASE + NRF53_TEMP_B1_OFFSET)
#define NRF53_TEMP_B2 (NRF53_TEMP_BASE + NRF53_TEMP_B2_OFFSET)
#define NRF53_TEMP_B3 (NRF53_TEMP_BASE + NRF53_TEMP_B3_OFFSET)
#define NRF53_TEMP_B4 (NRF53_TEMP_BASE + NRF53_TEMP_B4_OFFSET)
#define NRF53_TEMP_B5 (NRF53_TEMP_BASE + NRF53_TEMP_B5_OFFSET)
#define NRF53_TEMP_T0 (NRF53_TEMP_BASE + NRF53_TEMP_T0_OFFSET)
#define NRF53_TEMP_T1 (NRF53_TEMP_BASE + NRF53_TEMP_T1_OFFSET)
#define NRF53_TEMP_T2 (NRF53_TEMP_BASE + NRF53_TEMP_T2_OFFSET)
#define NRF53_TEMP_T3 (NRF53_TEMP_BASE + NRF53_TEMP_T3_OFFSET)
#define NRF53_TEMP_T4 (NRF53_TEMP_BASE + NRF53_TEMP_T4_OFFSET)
/* Register bit definitions *************************************************/
#define NRF53_TEMP_INTENSET_DATARDY (1 << 0) /* Read: Enabled */
#define NRF53_TEMP_INTENCLR_DATARDY (1 << 0) /* Read: Enabled */
#endif // __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TEMP_H

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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_tim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TIM_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TIM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TIMER constants **********************************************************/
#define TIMER_BASE_FERQUENCY (16000000)
/* Register offsets for TIM *************************************************/
#define NRF53_TIM_TASKS_START_OFFSET 0x0000 /* Start Timer */
#define NRF53_TIM_TASKS_STOP_OFFSET 0x0004 /* Stop Timer */
#define NRF53_TIM_TASKS_COUNT_OFFSET 0x0008 /* Increment Timer */
#define NRF53_TIM_TASKS_CLEAR_OFFSET 0x000c /* Clear time */
#define NRF53_TIM_TASKS_SHUTDOWN_OFFSET 0x0010 /* Shutdown Timer */
#define NRF53_TIM_TASKS_CAPTURE_OFFSET(x) (0x0040 + ((x) * 4)) /* Capture Timer value to CC[x] */
#define NRF53_TIM_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 4)) /* Compare event on CC[x] */
/* TODO: 0x080-0x1c0 */
#define NRF53_TIM_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
#define NRF53_TIM_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
#define NRF53_TIM_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_TIM_INTCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_TIM_MODE_OFFSET 0x0504 /* Timer mode selection */
#define NRF53_TIM_BITMODE_OFFSET 0x0508 /* Configure the number of bits used by the Timer */
#define NRF53_TIM_PRESCALER_OFFSET 0x0510 /* Timer prescaler register */
#define NRF53_TIM_CC_OFFSET(x) (0x0540 + ((x) * 4)) /* Capture/Compare register x */
#define NRF53_TIM_ONESHOT_OFFSET(x) (0x0580 + ((x) * 4)) /* Enable one-shot operation for Capture/Compare channel x */
/* Register offsets for TIM *************************************************/
/* TASKS_START Register */
#define TIM_TASKS_START (1 << 0) /* Bit 0: Start Timer */
/* TASKS_STOP Register */
#define TIM_TASKS_STOP (1 << 0) /* Bit 0: Stop Timer */
/* TASKS_COUNT Register */
#define TIM_TASKS_COUNT (1 << 0) /* Bit 0: Increment Timer */
/* TASKS_CLEAR Register */
#define TIM_TASKS_CLEAR (1 << 0) /* Bit 0: Clear Timer */
/* SHORTS Register */
#define TIM_SHORTS_COMPARE_CLEAR(x) (1 << (x)) /* Bits 0-5: */
#define TIM_SHORTS_COMPARE_STOP(x) (1 << (x + 8)) /* Bits 8-13 */
/* INTENSET/INTENCLR Register */
#define TIM_INT_COMPARE(x) (1 << (x + 16)) /* Bits 16-21 */
/* MODE Register */
#define TIM_MODE_SHIFT (0) /* Bits 0-1: Timer mode */
#define TIM_MODE_MASK (0x3 << TIM_MODE_SHIFT)
# define TIM_MODE_TIMER (0x0 << TIM_MODE_SHIFT) /* 0: Timer mode */
# define TIM_MODE_COUNTER (0x1 << TIM_MODE_SHIFT) /* 1: Counter mode */
# define TIM_MODE_LPCOUNTER (0x2 << TIM_MODE_SHIFT) /* 2: Low Power Counter mode */
/* BITMODE Register */
#define TIM_BITMODE_SHIFT (0) /* Bits 0-1: Timer bit width */
#define TIM_BITMODE_MASK (0x3 << TIM_BITMODE_SHIFT)
# define TIM_BITMODE_16B (0x0 << TIM_BITMODE_SHIFT) /* 0: 16 bit */
# define TIM_BITMODE_8B (0x1 << TIM_BITMODE_SHIFT) /* 1: 8 bit */
# define TIM_BITMODE_24B (0x2 << TIM_BITMODE_SHIFT) /* 2: 24 bit */
# define TIM_BITMODE_32B (0x3 << TIM_BITMODE_SHIFT) /* 3: 32 bit */
/* PRESCALER Register */
#define TIM_PRESCALER_SHIFT (0) /* Bits 0-3: Prescaler value */
#define TIM_PRESCALER_MAX (9)
#define TIM_PRESCALER_MASK (TIM_PRESCALER_MAX << TIM_PRESCALER_SHIFT)
/* ONESHOT Register */
#define TIM_ONESHOT_EN (1 << 0) /* Bit 0: Enable one-shot operation */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TIM_H */

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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_twi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TWI_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TWI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets for TWI master (TWIM) ***********************************/
#define NRF53_TWIM_TASKS_STARTRX_OFFSET 0x0000 /* Start TWIM receive sequence */
#define NRF53_TWIM_TASKS_STARTTX_OFFSET 0x0008 /* Start TWIM transmit sequence */
#define NRF53_TWIM_TASKS_STOP_OFFSET 0x0014 /* Stop TWIM transaction */
#define NRF53_TWIM_TASKS_SUSPEND_OFFSET 0x001c /* Suspend TWIM transaction */
#define NRF53_TWIM_TASKS_RESUME_OFFSET 0x0020 /* Resume TWIM transaction */
/* TODO: 0x080 - 0x0a0 */
#define NRF53_TWIM_EVENTS_STOPPED_OFFSET 0x0104 /* TWIM stopped */
#define NRF53_TWIM_EVENTS_ERROR_OFFSET 0x0124 /* TWIM error */
#define NRF53_TWIM_EVENTS_SUSPENDED_OFFSET 0x0148 /* Last byte has been sent out after the SUSPEND task has been issued */
#define NRF53_TWIM_EVENTS_RXSTARTED_OFFSET 0x014c /* Receive sequence started */
#define NRF53_TWIM_EVENTS_TXSTARTED_OFFSET 0x0150 /* Transmit sequence started */
#define NRF53_TWIM_EVENTS_LASTRX_OFFSET 0x015c /* Byte boundary, starting to receive the last byte */
#define NRF53_TWIM_EVENTS_LASTTX_OFFSET 0x0160 /* Byte boundary, starting to transmit the last byte */
/* TODO: 0x184 - 0x1e0 */
#define NRF53_TWIM_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
#define NRF53_TWIM_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
#define NRF53_TWIM_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_TWIM_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_TWIM_ERRORSRC_OFFSET 0x04c4 /* Error source */
#define NRF53_TWIM_ENABLE_OFFSET 0x0500 /* Enable TWIMS */
#define NRF53_TWIM_PSELSCL_OFFSET 0x0508 /* Pin select for SCL signal */
#define NRF53_TWIM_PSELSDA_OFFSET 0x050c /* Pin select for SDA signal */
#define NRF53_TWIM_FREQUENCY_OFFSET 0x0524 /* TWIM frequency */
#define NRF53_TWIM_RXDPTR_OFFSET 0x0534 /* RXD Data pointer */
#define NRF53_TWIM_RXDMAXCNT_OFFSET 0x0538 /* Maximum number of bytes in RXD buffer */
#define NRF53_TWIM_RXDAMOUNT_OFFSET 0x053c /* Number of bytes transferred in the last RXD transaction */
#define NRF53_TWIM_RXDLIST_OFFSET 0x0540 /* RX EasyDMA list type */
#define NRF53_TWIM_TXDPTR_OFFSET 0x0544 /* TXD Data pointer */
#define NRF53_TWIM_TXMAXCNT_OFFSET 0x0548 /* Maximum number of bytes in TXD buffer */
#define NRF53_TWIM_TXAMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last TXD transaction */
#define NRF53_TWIM_TXLIST_OFFSET 0x0550 /* TX EasyDMA list type */
#define NRF53_TWIM_ADDRESS_OFFSET 0x0588 /* TWIM address */
/* Register offsets for TWI slave (TWIS) ************************************/
#define NRF53_TWIS_TASKS_STOP_OFFSET 0x0014 /* Stop TWIS transaction */
#define NRF53_TWIS_TASKS_SUSPEND_OFFSET 0x001c /* Suspend TWIS transaction */
#define NRF53_TWIS_TASKS_RESUME_OFFSET 0x0020 /* Resume TWIS transaction */
#define NRF53_TWIS_TASKS_PREPARERX_OFFSET 0x0030 /* Prepare the TWIS slave to respond to a write command */
#define NRF53_TWIS_TASKS_PREPARETX_OFFSET 0x0034 /* Prepare the TWIS slave to respond to a read command */
#define NRF53_TWIS_EVENTS_STOPPED_OFFSET 0x0104 /* TWIS stopped */
#define NRF53_TWIS_EVENTS_ERROR_OFFSET 0x0124 /* TWIS error */
#define NRF53_TWIS_EVENTS_RXSTARTED_OFFSET 0x014c /* Receive sequence started */
#define NRF53_TWIS_EVENTS_TXSTARTED_OFFSET 0x0150 /* Transmit sequence started */
#define NRF53_TWIS_EVENTS_WRITE_OFFSET 0x0164 /* Write command received */
#define NRF53_TWIS_EVENTS_READ_OFFSET 0x0168 /* Read command received */
#define NRF53_TWIS_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
#define NRF53_TWIS_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
#define NRF53_TWIS_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_TWIS_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_TWIS_ERRORSRC_OFFSET 0x04d0 /* Error source */
#define NRF53_TWIS_MATCH_OFFSET 0x04d4 /* Status register indicating which address had a match */
#define NRF53_TWIS_ENABLE_OFFSET 0x0500 /* Enable TWISS */
#define NRF53_TWIS_PSELSCL_OFFSET 0x0508 /* Pin select for SCL signal */
#define NRF53_TWIS_PSELSDA_OFFSET 0x050c /* Pin select for SDA signal */
#define NRF53_TWIS_RXDPTR_OFFSET 0x0534 /* RXD Data pointer */
#define NRF53_TWIS_RXDMAXCNT_OFFSET 0x0538 /* Maximum number of bytes in RXD buffer */
#define NRF53_TWIS_RXDAMOUNT_OFFSET 0x053c /* Number of bytes transferred in the last RXD transaction */
#define NRF53_TWIS_RXDLIST_OFFSET 0x0540 /* RX EasyDMA list type */
#define NRF53_TWIS_TXDPTR_OFFSET 0x0544 /* TXD Data pointer */
#define NRF53_TWIS_TXMAXCNT_OFFSET 0x0548 /* Maximum number of bytes in TXD buffer */
#define NRF53_TWIS_TXAMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last TXD transaction */
#define NRF53_TWIS_TXLIST_OFFSET 0x0550 /* TX EasyDMA list type */
#define NRF53_TWIS_ADDRESS0_OFFSET 0x0588 /* TWIS address 0 */
#define NRF53_TWIS_ADDRESS1_OFFSET 0x058c /* TWIS address 1 */
#define NRF53_TWIS_CONFIG_OFFSET 0x0594 /* Configuration register for the address match mechanism */
#define NRF53_TWIS_ORC_OFFSET 0x05c0 /* Over-read character */
/* Register Bitfield Definitions for TWIM ***********************************/
/* SHORTS Register */
#define TWIM_SHORTS_LASTTX_STARTRX (1 << 7) /* Bit 7: Shortcut between event LASTTX and task STARTRX */
#define TWIM_SHORTS_LASTTX_SUSPEND (1 << 8) /* Bit 8: Shortcut between event LASTTX and task SUSPEND */
#define TWIM_SHORTS_LASTTX_STOP (1 << 9) /* Bit 9: Shortcut between event LASTTX and task STOP */
#define TWIM_SHORTS_LASTRX_STARTTX (1 << 10) /* Bit 10: Shortcut between event LASTRX and task STARTTX */
#define TWIM_SHORTS_LASTRX_SUSPEND (1 << 11) /* Bit 11: Shortcut between event LASTRX and task SUSPEND */
#define TWIM_SHORTS_LASTRX_STOP (1 << 12) /* Bit 12: Shortcut between event LASTRX and task STOP */
/* INTEN/INTENSET/INTENCLR Register */
#define TWIM_INT_STOPPED (1 << 1) /* Bit 1: Interrupt for event STOPPED */
#define TWIM_INT_ERROR (1 << 9) /* Bit 9: Interrupt for event ERROR */
#define TWIM_INT_SUSPENDED (1 << 18) /* Bit 18: Interrupt for event SUSPENDED */
#define TWIM_INT_RXSTARTED (1 << 19) /* Bit 19: Interrupt for event RXSTARTED */
#define TWIM_INT_TXSTARTED (1 << 20) /* Bit 20: Interrupt for event TXSTARTED */
#define TWIM_INT_LASTRX (1 << 23) /* Bit 23: Interrupt for event LASTRX */
#define TWIM_INT_LASTTX (1 << 24) /* Bit 24: Interrupt for event LASTTX */
/* ERRORSRC Register */
#define TWIM_ERRORSRC_OVERRUN (1 << 0) /* Bit 0: Overrun error */
#define TWIM_ERRORSRC_ANACK (1 << 1) /* Bit 1: NACK received after sending the address */
#define TWIM_ERRORSRC_DNACK (1 << 2) /* Bit 2: NACK received after sending a data byte */
/* ENABLE Register */
#define TWIM_ENABLE_DIS (0) /* Disable TWIM */
#define TWIM_ENABLE_EN (0x6 << 0) /* Disable TWIM */
/* PSELSCL Register */
#define TWIM_PSELSCL_PIN_SHIFT (0) /* Bits 0-4: SCL pin number */
#define TWIM_PSELSCL_PIN_MASK (0x1f << TWIM_PSELSCL_PIN_SHIFT)
#define TWIM_PSELSCL_PORT_SHIFT (5) /* Bit 5: SCL port number */
#define TWIM_PSELSCL_PORT_MASK (0x1 << TWIM_PSELSCL_PORT_SHIFT)
#define TWIM_PSELSCL_CONNECTED (1 << 31) /* Bit 31: Connection */
#define TWIM_PSELSCL_RESET (0xffffffff)
/* PSELSDA Register */
#define TWIM_PSELSDA_PIN_SHIFT (0) /* Bits 0-4: SDA pin number */
#define TWIM_PSELSDA_PIN_MASK (0x1f << TWIM_PSELSDA_PIN_SHIFT)
#define TWIM_PSELSDA_PORT_SHIFT (5) /* Bit 5: SDA port number */
#define TWIM_PSELSDA_PORT_MASK (0x1 << TWIM_PSELSDA_PORT_SHIFT)
#define TWIM_PSELSDA_CONNECTED (1 << 31) /* Bit 31: Connection */
#define TWIM_PSELSDA_RESET (0xffffffff)
/* FREQUENCY Register */
#define TWIM_FREQUENCY_100KBPS (0x01980000) /* 100 kbps */
#define TWIM_FREQUENCY_250KBPS (0x04000000) /* 250 kbps */
#define TWIM_FREQUENCY_400KBPS (0x06400000) /* 400 kbps */
#define TWIM_FREQUENCY_1000KBPS (0x0ff00000) /* 1000 kbps */
/* RXDMAXCNT Register */
#define TWIM_RXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in receive buffer */
#define TWIM_RXDMAXCNT_MASK (0xffff << TWIM_RXDMAXCNT_SHIFT)
/* RXDAMOUNT Register */
#define TWIM_RXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */
#define TWIM_RXDAMOUNT_MASK (0xffff << TWIM_RXDAMOUNT_SHIFT)
/* TXDMAXCNT Register */
#define TWIM_TXDMAXCNT_SHIFT (0) /* Bits 0-15: Maximum number of bytes in transmit buffer */
#define TWIM_TXDMAXCNT_MASK (0xffff << TWIM_TXDMAXCNT_SHIFT)
/* TXDAMOUNT Register */
#define TWIM_TXDAMOUNT_SHIFT (0) /* Bits 0-15: Number of bytes transferred in the last transaction */
#define TWIM_TXDAMOUNT_MASK (0xffff << TWIM_TXDAMOUNT_SHIFT)
/* ADDRESS Register */
#define TWIM_ADDRESS_SHIFT (0) /* Bits 0-6: Address used in the TWI transfer */
#define TWIM_ADDRESS_MASK (0x7f << TWIM_ADDRESS_SHIFT)
/* Register Bitfield Definitions for TWIS ***********************************/
/* TODO */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TWI_H */

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/****************************************************************************
* arch/arm/src/nrf53/hardware/nrf53_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_WDT_H
#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_WDT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf53_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* WDT Register Offsets *****************************************************/
#define NRF53_WDT_TASKS_START_OFFSET 0x0000 /* Start the watchdog */
#define NRF53_WDT_TASKS_STOP_OFFSET 0x0004 /* Stop the watchdog */
#define NRF53_WDT_SUBSCRIBE_START_OFFSET 0x0080 /* Subscribe configuration for task START */
#define NRF53_WDT_SUBSCRIBE_STOP_OFFSET 0x0084 /* Subscribe configuration for task STOP */
#define NRF53_WDT_EVENTS_TIMEOUT_OFFSET 0x0100 /* Watchdog timeout */
#define NRF53_WDT_EVENTS_STOPPED_OFFSET 0x0104 /* Watchdog stopped */
#define NRF53_WDT_PUBLISH_TIMEOUT_OFFSET 0x0180 /* Publish configuration for event TIMEOUT */
#define NRF53_WDT_PUBLISH_STOPPED_OFFSET 0x0184 /* Publish configuration for event STOPPED */
#define NRF53_WDT_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF53_WDT_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF53_WDT_NMIENSET_OFFSET 0x0324 /* Enable interrupt */
#define NRF53_WDT_NMIENCLR_OFFSET 0x0328 /* Disable interrupt */
#define NRF53_WDT_RUNSTATUS_OFFSET 0x0400 /* Run status */
#define NRF53_WDT_REQSTATUS_OFFSET 0x0404 /* Request status */
#define NRF53_WDT_CRV_OFFSET 0x0504 /* Counter reload value */
#define NRF53_WDT_RREN_OFFSET 0x0508 /* Enable register for reload request registers */
#define NRF53_WDT_CONFIG_OFFSET 0x050c /* Configuration register */
#define NRF53_WDT_RR0_OFFSET 0x0600 /* Reload request 0 */
#define NRF53_WDT_RR1_OFFSET 0x0604 /* Reload request 1 */
#define NRF53_WDT_RR2_OFFSET 0x0608 /* Reload request 2 */
#define NRF53_WDT_RR3_OFFSET 0x060c /* Reload request 3 */
#define NRF53_WDT_RR4_OFFSET 0x0610 /* Reload request 4 */
#define NRF53_WDT_RR5_OFFSET 0x0614 /* Reload request 5 */
#define NRF53_WDT_RR6_OFFSET 0x0618 /* Reload request 6 */
#define NRF53_WDT_RR7_OFFSET 0x061c /* Reload request 7 */
/* WDT Register Addresses ***************************************************/
#define NRF53_WDT_TASKS_START (NRF53_WDT_BASE + NRF53_WDT_TASKS_START_OFFSET)
#define NRF53_WDT_TASKS_STOP (NRF53_WDT_BASE + NRF53_WDT_TASKS_STOP_OFFSET)
#define NRF53_WDT_SUBSCRIBE_START (NRF53_WDT_BASE + NRF53_WDT_SUBSCRIBE_START_OFFSET)
#define NRF53_WDT_SUBSCRIBE_STOP (NRF53_WDT_BASE + NRF53_WDT_SUBSCRIBE_STOP_OFFSET)
#define NRF53_WDT_EVENTS_TIMEOUT (NRF53_WDT_BASE + NRF53_WDT_EVENTS_TIMEOUT_OFFSET)
#define NRF53_WDT_EVENTS_STOPPED (NRF53_WDT_BASE + NRF53_WDT_EVENTS_STOPPED_OFFSET)
#define NRF53_WDT_INTENSET (NRF53_WDT_BASE + NRF53_WDT_INTENSET_OFFSET)
#define NRF53_WDT_INTENCLR (NRF53_WDT_BASE + NRF53_WDT_INTENCLR_OFFSET)
#define NRF53_WDT_NMIENSET (NRF53_WDT_BASE + NRF53_WDT_NMIENSET_OFFSET)
#define NRF53_WDT_NMIENCLR (NRF53_WDT_BASE + NRF53_WDT_NMIENCLR_OFFSET)
#define NRF53_WDT_RUNSTATUS (NRF53_WDT_BASE + NRF53_WDT_RUNSTATUS_OFFSET)
#define NRF53_WDT_REQSTATUS (NRF53_WDT_BASE + NRF53_WDT_REQSTATUS_OFFSET)
#define NRF53_WDT_CRV (NRF53_WDT_BASE + NRF53_WDT_CRV_OFFSET)
#define NRF53_WDT_RREN (NRF53_WDT_BASE + NRF53_WDT_RREN_OFFSET)
#define NRF53_WDT_CONFIG (NRF53_WDT_BASE + NRF53_WDT_CONFIG_OFFSET)
#define NRF53_WDT_RR0 (NRF53_WDT_BASE + NRF53_WDT_RR0_OFFSET)
#define NRF53_WDT_RR1 (NRF53_WDT_BASE + NRF53_WDT_RR1_OFFSET)
#define NRF53_WDT_RR2 (NRF53_WDT_BASE + NRF53_WDT_RR2_OFFSET)
#define NRF53_WDT_RR3 (NRF53_WDT_BASE + NRF53_WDT_RR3_OFFSET)
#define NRF53_WDT_RR4 (NRF53_WDT_BASE + NRF53_WDT_RR4_OFFSET)
#define NRF53_WDT_RR5 (NRF53_WDT_BASE + NRF53_WDT_RR5_OFFSET)
#define NRF53_WDT_RR6 (NRF53_WDT_BASE + NRF53_WDT_RR6_OFFSET)
#define NRF53_WDT_RR7 (NRF53_WDT_BASE + NRF53_WDT_RR7_OFFSET)
/* WDT Register Bitfield Definitions ****************************************/
/* INTENSET/INTENCLR Register */
#define WDT_INT_TIMEOUT (1 << 0) /* Bit 0: TIMEOUT */
/* REQSTATUS[x] Register */
#define WDT_REQSTATUS_RR(x) (1 << (x)) /* Bits 0-7: Request status for RR[i] register */
/* RREN[x] Register */
#define WDT_RREN_RR(x) (1 << (x)) /* Bits 0-7: Enable or disable RR[i] register */
/* CONFIG Register */
#define WDT_CONFIG_SLEEP (1 << 0) /* Bit 0: */
#define WDT_CONFIG_HALT (1 << 3) /* Bit 3: */
/* RR[x] Register */
#define WDT_RR_VALUE (0x6E524635UL) /* Fixed value, don't modify it */
#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_WDT_H */