Add PIC32 exception handling macros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3629 42af7a65-404d-4744-a932-0658087f49c3
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arch/mips/src/mips32/mips32-excptmacros.h
Executable file
410
arch/mips/src/mips32/mips32-excptmacros.h
Executable file
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/********************************************************************************************
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* arch/mips/src/mips32/mips32-excptmacros.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_EXCPTMACROS_H
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#define __ARCH_MIPS_SRC_MIPS32_MIPS32_EXCPTMACROS_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/mips32/cp0.h>
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#ifdef __ASSEMBLY__
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/********************************************************************************************
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* Global Symbols
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********************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.global g_stackbase
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.global g_nestlevel
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#endif
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/********************************************************************************************
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* Assembly Language Macros
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********************************************************************************************/
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/********************************************************************************************
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* General Usage Example:
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*
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* my_exception:
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* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
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* move a0, sp - Pass register save structure as the parameter 1
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* USE_INTSTACK, t0, t1, t2 - Switch to the interrupt stack
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* jal handler - Handle the exception IN=old regs OUT=new regs
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* di - Disable interrupts
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* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
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* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
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*
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********************************************************************************************/
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/********************************************************************************************
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* Name: EXCPT_PROLOGUE
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*
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* Description:
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* Provides the "prologue" logic that should appear at the beginning of every exception
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* handler.
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*
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* On Entry:
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* sp - Points to the top of the stack
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* tmp - Is a register the can be modified for scratch usage (after it has been saved)
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* k0 and k1 - Since we are in an exception handler, these are available for use
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*
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* At completion:
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* Register state is saved on the stack; All registers are available for usage except sp
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* and k1:
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*
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* - sp points the beginning of the register save area
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* - k1 holds the value of the STATUS register
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*
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* The following registers are modified: k0, k1, sp, a0
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*
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********************************************************************************************/
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.macro EXCPT_PROLOGUE, tmp
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/* Get the SP from the previous shadow set */
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#if 0
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rdpgpr sp, sp
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#endif
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/* "When entering the interrupt handler routine, the interrupt controller must first
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* save the current priority and exception PC counter from Interrupt Priority (IPL)
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* bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
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*/
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mfc0 k0, MIPS32_CP0_CAUSE
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mfc0 k1, MIPS32_CP0_EPC
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/* Isolate the pending interrupt level in bits 0-5 of k0 */
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srl k0, k0, CP0_CAUSE_IP_SHIFT
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/* Create the register context stack frame large enough to hold the entire register save
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* array.
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*/
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addiu sp, sp, -XCPTCONTEXT_SIZE
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/* Save the EPC and STATUS in the register context array */
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sw k1, REG_EPC(sp)
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mfc0 k1, MIPS32_CP0_STATUS
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sw k1, REG_STATUS(sp)
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/* Then insert pending interrupt level as the current mask level in the CP0 status
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* register. Also clear bits 1-4 in new value of the status register:
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*
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* Bit 1: Exception Level
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* Bit 2: Error Level
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* Bit 3: (not used in PIC32MX)
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* Bit 4: Operating mode == USER
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*/
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ins k1, \tmp, CP0_STATUS_IPL_SHIFT, 6
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ins k1, zero, 1, 4
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/* And Enable interrupts */
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mtc0 k1, MIPS32_CP0_STATUS
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/* Save floating point registers */
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mfhi k0
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sw k0, REG_MFHI(sp)
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mflo k0
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sw k0, REG_MFLO(sp)
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/* Save general purpose registers */
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/* $1: at_reg, assembler temporary */
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sw $1, REG_AT(sp)
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/* $2-$3 = v0-v1: Return value registers */
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sw v0, REG_V0(sp)
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sw v1, REG_V1(sp)
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/* $4-$7 = a0-a3: Argument registers */
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sw a0, REG_A0(sp)
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sw a1, REG_A1(sp)
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sw a2, REG_A2(sp)
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sw a3, REG_A3(sp)
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/* $8-$15 = t0-t7: Volatile registers */
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sw t0, REG_T0(sp)
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sw t1, REG_T1(sp)
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sw t2, REG_T2(sp)
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sw t3, REG_T3(sp)
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sw t4, REG_T4(sp)
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sw t5, REG_T5(sp)
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sw t6, REG_T6(sp)
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sw t7, REG_T7(sp)
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/* $16-$23 = s0-s7: Static registers */
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sw s0, REG_S0(sp)
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sw s1, REG_S1(sp)
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sw s2, REG_S2(sp)
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sw s3, REG_S3(sp)
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sw s4, REG_S4(sp)
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sw s5, REG_S5(sp)
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sw s6, REG_S6(sp)
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sw s7, REG_S7(sp)
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/* $24-25 = t8-t9: More Volatile registers */
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sw t8, REG_T8(sp)
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sw t9, REG_T9(sp)
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/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need to be
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* saved.
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*
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* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
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* thread values for the GP.
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*/
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#ifdef MIPS32_SAVE_GP
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sw gp, REG_GP(sp)
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#endif
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/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
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sw s8, REG_S8(sp)
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/* $31 = ra: Return address */
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sw ra, REG_RA(sp)
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/* $29 = sp: The value of the stack pointer on return from the exception. a0 is
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* used as a temporary
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*/
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addiu \tmp, sp, XCPTCONTEXT_SIZE
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sw \tmp, REG_SP(sp)
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.endm
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/********************************************************************************************
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* Name: EXCPT_EPILOGUE
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*
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* Description:
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* Provides the "epilogue" logic that should appear at the end of every exception handler.
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*
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* On input:
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* regs - points to the register save structure. NOTE: This *may not* be an address
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* lying in a stack! It might be an address in a TCB!
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* Interrupts are disabled (via 'di')
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*
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* On completion:
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* All registers restored
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* eret is executed to return from the exception
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*
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********************************************************************************************/
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.macro EXCPT_EXIT, regs
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/* Since interrupts are disabled via di can now use k0 and k1 again. Use k1 as the
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* pointer to the register save array.
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*/
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move k1, \regs
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/* Restore the floating point register state */
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lw k0, REG_MTLO(k1)
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mtlo k0
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lw k0, REG_MTHI(k1)
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mthi k0
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/* Restore general purpose registers */
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/* $1: at_reg, assembler temporary */
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lw $1, REG_AT(k1)
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/* $2-$3 = v0-v1: Return value registers */
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lw v0, REG_V0(k1)
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lw v1, REG_V1(k1)
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/* $4-$7 = a0-a3: Argument registers */
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lw a0, REG_A0(k1)
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lw a1, REG_A1(k1)
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lw a2, REG_A2(k1)
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lw a3, REG_A3(k1)
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/* $8-$15 = t0-t7: Volatile registers */
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lw t0, REG_T0(k1)
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lw t1, REG_T1(k1)
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lw t2, REG_T2(k1)
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lw t3, REG_T3(k1)
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lw t4, REG_T4(k1)
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lw t5, REG_T5(k1)
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lw t6, REG_T6(k1)
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lw t7, REG_T7(k1)
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/* $16-$23 = s0-s7: Static registers */
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lw s0, REG_S0(k1)
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lw s1, REG_S1(k1)
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lw s2, REG_S2(k1)
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lw s3, REG_S3(k1)
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lw s4, REG_S4(k1)
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lw s5, REG_S5(k1)
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lw s6, REG_S6(k1)
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lw s7, REG_S7(k1)
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/* $24-25 = t8-t9: More Volatile registers */
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lw t8, REG_T8(k1)
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lw t9, REG_T9(k1)
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/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need to be
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* saved.
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*
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* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
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* thread values for the GP.
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*/
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#ifdef MIPS32_SAVE_GP
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lw gp, REG_GP(k1)
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#endif
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/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
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lw s8, REG_S8(k1)
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/* $31 = ra: Return address */
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lw ra, REG_RA(k1)
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/* Finally, restore CP status and the EPC */
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lw k0, REG_STATUS(k1)
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lw k1, REG_EPC(k1)
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mtc0 k0, MIPS32_CP0_STATUS
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ehb
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mtc0 k1, MIPS32_CP0_EPC
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eret
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nop
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.endm
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/********************************************************************************************
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* Name: USE_INTSTACK
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*
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* Description:
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* Switch to the interrupt stack (if enabled in the configuration).
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*
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* On Entry:
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* sp - Current value of the user stack pointer
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* tmp1, tmp2, and tmp3 are registers that can be used temporarily.
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* All interrupts should still be disabled.
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*
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* At completion:
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* If the nesting level is 0, then (1) the user stack pointer is saved at the base of the
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* interrupt stack and sp points to the interrupt stack.
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* The values of tmp1, tmp2, tmp3, and sp have been altered
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*
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********************************************************************************************/
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.macro USE_INTSTACK, tmp1, tmp2, tmp3
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* Check the nesting level. If there are no nested interrupts, then we can
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* claim the interrupt stack.
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*/
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la \tmp1, g_nestlevel
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lw \tmp2, (\tmp1)
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bne 1f
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nop
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/* Use the interrupt stack, pushing the user stack pointer onto the interrupt
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* stack first.
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*/
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la \tmp3, g_intstack
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sw sp, (\tmp3)
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move sp, \tmp3
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1:
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/* Increment the interrupt nesting level */
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addiu \tmp2, \tmp2, 1
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sw \tmp2, 0(\tmp1)
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#endif
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.endm
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/********************************************************************************************
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* Name: RESTORE_STACK
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*
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* Description:
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* Restore the user stack. Not really.. actually only decrements the nesting level. We
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* always get the new stack pointer for the register save array.
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*
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* On Entry:
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* tmp1 and tmp2 are registers that can be used temporarily.
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* All interrupts must be disabled.
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*
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* At completion:
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* Current nesting level is decremented
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* The values of tmp1 and tmp2 have been altered
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*
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********************************************************************************************/
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||||||
|
.macro RESTORE_STACK, tmp1, tmp2
|
||||||
|
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||||
|
|
||||||
|
/* Decrement the nesting level */
|
||||||
|
|
||||||
|
la \tmp1, g_nestlevel
|
||||||
|
lw \tmp2, (\tmp1)
|
||||||
|
addiu \tmp2, \tmp2, -1
|
||||||
|
sw \tmp2, 0(\tmp1)
|
||||||
|
#endif
|
||||||
|
.endm
|
||||||
|
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_EXCPTMACROS_H */
|
||||||
@ -54,6 +54,20 @@
|
|||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
|
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||||
|
|
||||||
|
/* Enable only software interrupts */
|
||||||
|
|
||||||
|
# define INITIAL_STATUS (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_IM_SWINTS)
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
/* Enable all interrupts */
|
||||||
|
|
||||||
|
# define INITIAL_STATUS (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_IM_ALL)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Data
|
* Private Data
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@ -83,13 +97,16 @@
|
|||||||
void up_initial_state(_TCB *tcb)
|
void up_initial_state(_TCB *tcb)
|
||||||
{
|
{
|
||||||
struct xcptcontext *xcp = &tcb->xcp;
|
struct xcptcontext *xcp = &tcb->xcp;
|
||||||
irqstate_t status;
|
|
||||||
|
|
||||||
/* Initialize the initial exception register context structure */
|
/* Initialize the initial exception register context structure */
|
||||||
|
|
||||||
memset(xcp, 0, sizeof(struct xcptcontext));
|
memset(xcp, 0, sizeof(struct xcptcontext));
|
||||||
|
|
||||||
/* Save the initial stack pointer */
|
/* Save the initial stack pointer. Hmmm.. the stack is set to the very
|
||||||
|
* beginning of the stack region. Some functions may want to store data on
|
||||||
|
* the caller's stack and it might be good to reserve some space. However,
|
||||||
|
* only the start function would do that and we have control over that one
|
||||||
|
*/
|
||||||
|
|
||||||
xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
|
xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
|
||||||
|
|
||||||
@ -118,13 +135,6 @@ void up_initial_state(_TCB *tcb)
|
|||||||
|
|
||||||
/* Enable or disable interrupts, based on user configuration */
|
/* Enable or disable interrupts, based on user configuration */
|
||||||
|
|
||||||
status = cp0_getstatus();
|
xcp->regs[REG_STATUS] = INITIAL_STATUS;
|
||||||
# ifdef CONFIG_SUPPRESS_INTERRUPTS
|
|
||||||
status &= ~CP0_STATUS_IM_MASK; /* Disable all interrupts */
|
|
||||||
status |= CP0_STATUS_IM_SWINTS; /* Make sure that S/W interrupts enabled */
|
|
||||||
#else
|
|
||||||
status |= CP0_STATUS_IM_ALL; /* Enable all interrupts */
|
|
||||||
# endif
|
|
||||||
xcp->regs[REG_STATUS] = status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -60,6 +60,11 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Definitions
|
* Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
/* Configuration ************************************************************/
|
||||||
|
|
||||||
|
#ifdef CONFIG_PIC32MX_MVEC
|
||||||
|
# error "Multi-vectors not supported"
|
||||||
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Data
|
* Public Data
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user