Add MEBI header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3052 42af7a65-404d-4744-a932-0658087f49c3
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arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h
Executable file
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arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MEBIV3_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MEBIV3_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_MEBI_PORTA_OFFSET 0x0000 /* Port A Data Register */
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#define HCS12_MEBI_PORTB_OFFSET 0x0001 /* Port B Data Register */
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#define HCS12_MEBI_DDRA_OFFSET 0x0002 /* Data Direction Register A */
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#define HCS12_MEBI_DDRB_OFFSET 0x0003 /* Data Direction Register B */
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#define HCS12_MEBI_PORTE_OFFSET 0x0008 /* Port E Data Register */
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#define HCS12_MEBI_DDRE_OFFSET 0x0009 /* Data Direction Register E */
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#define HCS12_MEBI_PEAR_OFFSET 0x000a /* Port E Assignment Register */
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#define HCS12_MEBI_MODE_OFFSET 0x000b /* Mode Register */
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#define HCS12_MEBI_PUCR_OFFSET 0x000c /* Pull Control Register */
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#define HCS12_MEBI_RDRIV_OFFSET 0x000d /* Reduced Drive Register */
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#define HCS12_MEBI_EBICTL_OFFSET 0x000e /* External Bus Interface Control Register */
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#define HCS12_MEBI_IRQCR_OFFSET 0x001e /* IRQ Control Register */
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#define HCS12_MEBI_PORTK_OFFSET 0x0032 /* Port K Data Register */
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#define HCS12_MEBI_DDRK_OFFSET 0x0033 /* Data Direction Register K */
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/* Register Addresses ***************************************************************/
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#define HCS12_MEBI_PORTA (HCS12_CORE1_BASE+HCS12_MEBI_PORTA_OFFSET)
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#define HCS12_MEBI_PORTB (HCS12_CORE1_BASE+HCS12_MEBI_PORTB_OFFSET)
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#define HCS12_MEBI_DDRA (HCS12_CORE1_BASE+HCS12_MEBI_DDRA_OFFSET)
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#define HCS12_MEBI_DDRB (HCS12_CORE1_BASE+HCS12_MEBI_DDRB_OFFSET)
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#define HCS12_MEBI_PORTE (HCS12_CORE1_BASE+HCS12_MEBI_PORTE_OFFSET)
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#define HCS12_MEBI_DDRE (HCS12_CORE1_BASE+HCS12_MEBI_DDRE_OFFSET)
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#define HCS12_MEBI_PEAR (HCS12_CORE1_BASE+HCS12_MEBI_PEAR_OFFSET)
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#define HCS12_MEBI_MODE (HCS12_CORE1_BASE+HCS12_MEBI_MODE_OFFSET)
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#define HCS12_MEBI_PUCR (HCS12_CORE1_BASE+HCS12_MEBI_PUCR_OFFSET)
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#define HCS12_MEBI_RDRIV (HCS12_CORE1_BASE+HCS12_MEBI_RDRIV_OFFSET)
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#define HCS12_MEBI_EBICTL (HCS12_CORE1_BASE+HCS12_MEBI_EBICTL_OFFSET)
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#define HCS12_MEBI_IRQCR (HCS12_CORE1_BASE+HCS12_MEBI_IRQCR_OFFSET)
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#define HCS12_MEBI_PORTK (HCS12_CORE1_BASE+HCS12_MEBI_PORTK_OFFSET)
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#define HCS12_MEBI_DDRK (HCS12_CORE1_BASE+HCS12_MEBI_DDRK_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* Port A Data Register Bit-Field Definitions */
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/* Port B Data Register Bit-Field Definitions */
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/* Data Direction Register A Bit-Field Definitions */
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/* Data Direction Register B Bit-Field Definitions */
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/* Port E Data Register Bit-Field Definitions */
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/* Data Direction Register E Bit-Field Definitions */
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/* Port K Data Register Bit-Field Definitions */
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/* Data Direction Register K Bit-Field Definitions */
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#define MEBI_PIN(n) (1 << (n))
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#define MEBI_PIN0 (1 << 0)
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#define MEBI_PIN1 (1 << 1)
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#define MEBI_PIN2 (1 << 2)
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#define MEBI_PIN3 (1 << 3)
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#define MEBI_PIN4 (1 << 4)
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#define MEBI_PIN5 (1 << 5)
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#define MEBI_PIN6 (1 << 6)
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#define MEBI_PIN7 (1 << 7)
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/* Port E Assignment Register Bit-Field Definitions */
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#define MEBI_PEAR_RDWE (1 << 2) /* Bit 2: Read/Write Enable */
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#define MEBI_PEAR_LSTRE (1 << 3) /* Bit 3: Low Strobe (~LSTRB) Enable */
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#define MEBI_PEAR_NECLK (1 << 4) /* Bit 4: No External E Clock */
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#define MEBI_PEAR_PIPOE (1 << 5) /* Bit 5: Pipe Status Signal Output Enable */
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#define MEBI_PEAR_NOACCE (1 << 7) /* Bit 7: CPU No Access Output Enable */
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/* Mode Register Bit-Field Definitions */
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#define MEBI_MODE_EME (1 << 0) /* Bit 0: Emulate Port E */
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#define MEBI_MODE_EMK (1 << 1) /* Bit 1: Emulate Port K */
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#define MEBI_MODE_IVIS (1 << 3) /* Bit 3: Internal Visibility */
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#define MEBI_MODE_MOD_SHIFT (5) /* Bits 5-7: Mode Select */
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#define MEBI_MODE_MOD_MASK (7 << MEBI_MODE_MOD_SHIFT)
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# define MEBI_MODE_MODA (1 << MEBI_MODE_MOD_SHIFT)
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# define MEBI_MODE_MODB (2 << MEBI_MODE_MOD_SHIFT)
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# define MEBI_MODE_MODC (4 << MEBI_MODE_MOD_SHIFT)
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/* Pull Control Register Bit-Field Definitions */
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#define MEBI_PUCR_PUPAE (1 << 0) /* Bit 0: Pull resistors Port A Enable */
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#define MEBI_PUCR_PUPBE (1 << 1) /* Bit 1: Pull resistors Port B Enable */
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#define MEBI_PUCR_PUPEE (1 << 4) /* Bit 4: Pull resistors Port E Enable */
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#define MEBI_PUCR_PUPKE (1 << 7) /* Bit 7: Pull resistors Port K Enable */
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/* Reduced Drive Register Bit-Field Definitions */
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#define MEBI_RDRIV_RDPA (1 << 0) /* Bit 0: Reduced Drive of Port A */
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#define MEBI_RDRIV_RDPB (1 << 1) /* Bit 1: Reduced Drive of Port B */
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#define MEBI_RDRIV_RDPE (1 << 4) /* Bit 4: Reduced Drive of Port E */
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#define MEBI_RDRIV_RDRK (1 << 7) /* Bit 7: Reduced Drive of Port K */
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/* External Bus Interface Control Register Bit-Field Definitions */
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#define MEBI_EBICTL_ESTR (1 << 0) /* Bit 0: E Clock Stretches */
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/* IRQ Control Register Bit-Field Definitions */
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#define MEBI_IRQCR_IRQEN (1 << 6) /* Bit 6: External IRQ Enable */
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#define MEBI_IRQCR_IRQE (1 << 7) /* Bit 7: IRQ Select Edge Sensitive Only */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MEBIV3_H */
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/* Register Bit-Field Definitions ***************************************************/
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/* Internal RAM Position Register */
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/* Internal RAM Position Register Bit-Field Definitions */
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#define MMC_INITRM_RAMHAL (1 << 0) /* Bit 0: RAM High-Align */
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#define MMC_INITRM_RAM_SHIFT (3) /* Bits 3-7: Internal RAM Map Position */
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#define MMC_INITRM_RAM_MASK (0x1f << MMC_INITRM_RAM_SHIFT)
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#define MMC_INITRM_RAM(addr) (((addr) >> (11-MMC_INITRM_RAM_SHIFT)) & MMC_INITRM_RAM_MASK)
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/* Internal Registers Position Register */
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/* Internal Registers Position Register Bit-Field Definitions */
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#define MMC_INITRG_REG_SHIFT (3) /* Bits 3-6: Internal RAM Map Position */
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#define MMC_INITRG_REG_MASK (0x0f << MMC_INITRG_REG_SHIFT)
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#define MMC_INITRG_REG(addr) (((addr) >> (11-MMC_INITRG_REG_SHIFT)) & MMC_INITRG_REG_SHIFT)
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/* Internal EEPROM Position Register */
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/* Internal EEPROM Position Register Bit-Field Definitions */
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#define MMC_INITEE_EEON (1 << 0) /* Bit 0: Enable EEPROM */
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#define MMC_INITEE_EE_SHIFT (3) /* Bits 3-7: Internal EEPROM Map Position */
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#define MMC_INITEE_EE_MASK (0x1f << MMC_INITEE_EE_SHIFT)
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#define MMC_INITEE_EE(addr) (((addr) >> (11-MMC_INITRG_REG_SHIFT)) & MMC_INITRG_REG_SHIFT)
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/* Miscellaneous System Control Register */
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/* Miscellaneous System Control Register Bit-Field Definitions */
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#define MMC_MISC_ROMON (1 << 0) /* Bit 0: Enable FLASH EEPROM or ROM */
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#define MMC_MISC_ROMHM (1 << 1) /* Bit 1: FLASH EEPROM or ROM Only in Second Half of Memory Map */
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# define MISC_EXSTR_CLKS2 (2 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS3 (3 << MMC_MISC_EXSTR_SHIFT)
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/* Reserved Test Register 0/1 -- Not documented */
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/* Reserved Test Register 0/1 Bit-Field Definitions -- Not documented */
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/* Memory Size Register 0 */
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/* Memory Size Register 0 Bit-Field Definitions */
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#define MMC_MEMSIZ0_RAMSW_SHIFT (0) /* Bits 0-2: Allocated System RAM Memory Space */
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#define MMC_MEMSIZ0_RAMSW_MASK (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_EEPSW_5KB (3 << MMC_MEMSIZ0_EEPSW_MASK)
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#define MMC_MEMSIZ0_REGSW (1 << 7) /* Bits 7: Allocated System Register Space */
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/* Memory Size Register 1 */
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/* Memory Size Register 1 Bit-Field Definitions */
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#define MMC_MEMSIZ1_PAGSW_SHIFT (0) /* Bits 0-1: Allocated System RAM Memory Space */
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#define MMC_MEMSIZ1_PAGSW_MASK (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_ROMSW_48KB (2 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_64KB (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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/* Program Page Index Register */
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/* Program Page Index Register Bit-Field Definitions */
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#define MMC_PPAGE_PIX_SHIFT (0) /* Bits 0-5 Program Page Index Bits 5–0 */
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#define MMC_PPAGE_PIX_MASK (0x3f << MMC_PPAGE_PIX_SHIFT)
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