diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index 2547bf33a6..f0b398ebb9 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -61,6 +61,7 @@ #include "chip.h" #include "stm32.h" +#include "stm32_rcc.h" #include "stm32_can.h" #if defined(CONFIG_CAN) && \ @@ -297,7 +298,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - caninfo("[repeats %d more times]\n", count - 3); + caninfo("[repeats %" PRIu32 " more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -309,7 +310,7 @@ static uint32_t stm32can_vgetreg(uint32_t addr) /* Show the register value read */ - caninfo("%08x->%08x\n", addr, val); + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); return val; } @@ -358,7 +359,7 @@ static void stm32can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ - caninfo("%08x<-%08x\n", addr, value); + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); /* Write the value */ @@ -420,16 +421,16 @@ static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv, /* CAN control and status registers */ - caninfo(" MCR: %08x MSR: %08x TSR: %08x\n", + caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_MCR_OFFSET), getreg32(priv->base + STM32_CAN_MSR_OFFSET), getreg32(priv->base + STM32_CAN_TSR_OFFSET)); - caninfo(" RF0R: %08x RF1R: %08x\n", + caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_RF0R_OFFSET), getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); - caninfo(" IER: %08x ESR: %08x BTR: %08x\n", + caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_IER_OFFSET), getreg32(priv->base + STM32_CAN_ESR_OFFSET), getreg32(priv->base + STM32_CAN_BTR_OFFSET)); @@ -465,31 +466,36 @@ static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv, /* CAN mailbox registers (3 TX and 2 RX) */ - caninfo(" TI0R: %08x TDT0R: %08x TDL0R: %08x TDH0R: %08x\n", + caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" + PRIx32 " TDH0R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_TI0R_OFFSET), getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); - caninfo(" TI1R: %08x TDT1R: %08x TDL1R: %08x TDH1R: %08x\n", + caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" + PRIx32 " TDH1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_TI1R_OFFSET), getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); - caninfo(" TI2R: %08x TDT2R: %08x TDL2R: %08x TDH2R: %08x\n", + caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" + PRIx32 " TDH2R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_TI2R_OFFSET), getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); - caninfo(" RI0R: %08x RDT0R: %08x RDL0R: %08x RDH0R: %08x\n", + caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" + PRIx32 " RDH0R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_RI0R_OFFSET), getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); - caninfo(" RI1R: %08x RDT1R: %08x RDL1R: %08x RDH1R: %08x\n", + caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" + PRIx32 " RDH1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_RI1R_OFFSET), getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), @@ -526,7 +532,8 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, caninfo("Filter Registers:\n"); } - caninfo(" FMR: %08x FM1R: %08x FS1R: %08x FFA1R: %08x FA1R: %08x\n", + caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" + PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", getreg32(priv->base + STM32_CAN_FMR_OFFSET), getreg32(priv->base + STM32_CAN_FM1R_OFFSET), getreg32(priv->base + STM32_CAN_FS1R_OFFSET), @@ -535,7 +542,7 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, for (i = 0; i < CAN_NFILTERS; i++) { - caninfo(" F%dR1: %08x F%dR2: %08x\n", + caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); } @@ -564,7 +571,7 @@ static void stm32can_reset(FAR struct can_dev_s *dev) uint32_t regbit = 0; irqstate_t flags; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ @@ -626,7 +633,8 @@ static int stm32can_setup(FAR struct can_dev_s *dev) FAR struct stm32_can_s *priv = dev->cd_priv; int ret; - caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n", + caninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 "\n", priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); /* CAN cell initialization */ @@ -634,7 +642,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = stm32can_cellinit(priv); if (ret < 0) { - canerr("ERROR: CAN%d cell initialization failed: %d\n", + canerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", priv->port, ret); return ret; } @@ -647,7 +655,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = stm32can_filterinit(priv); if (ret < 0) { - canerr("ERROR: CAN%d filter initialization failed: %d\n", + canerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", priv->port, ret); return ret; } @@ -661,7 +669,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, dev); if (ret < 0) { - canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)", + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", priv->port, priv->canrx[0]); return ret; } @@ -669,7 +677,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, dev); if (ret < 0) { - canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)", + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", priv->port, priv->canrx[1]); return ret; } @@ -677,7 +685,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->cantx, stm32can_txinterrupt, dev); if (ret < 0) { - canerr("ERROR: Failed to attach CAN%d TX IRQ (%d)", + canerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", priv->port, priv->cantx); return ret; } @@ -712,7 +720,7 @@ static void stm32can_shutdown(FAR struct can_dev_s *dev) { FAR struct stm32_can_s *priv = dev->cd_priv; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Disable the RX FIFO 0/1 and TX interrupts */ @@ -750,7 +758,7 @@ static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable) FAR struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; - caninfo("CAN%d enable: %d\n", priv->port, enable); + caninfo("CAN%" PRIu8 " enable: %d\n", priv->port, enable); /* Enable/disable the FIFO 0/1 message pending interrupt */ @@ -786,7 +794,7 @@ static void stm32can_txint(FAR struct can_dev_s *dev, bool enable) FAR struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; - caninfo("CAN%d enable: %d\n", priv->port, enable); + caninfo("CAN%" PRIu8 " enable: %d\n", priv->port, enable); /* Support only disabling the transmit mailbox interrupt */ @@ -925,7 +933,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } - caninfo("TS1: %d TS2: %d BRP: %" PRId32 "\n", + caninfo("TS1: %"PRIu8 " TS2: %" PRIu8 " BRP: %" PRIu32 "\n", bt->bt_tseg1, bt->bt_tseg2, brp); /* Configure bit timing. */ @@ -1223,7 +1231,7 @@ static int stm32can_send(FAR struct can_dev_s *dev, int dlc; int txmb; - caninfo("CAN%d ID: %" PRId32 " DLC: %d\n", + caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); /* Select one empty transmit mailbox */ @@ -1268,14 +1276,17 @@ static int stm32can_send(FAR struct can_dev_s *dev, DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11)); regval |= msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT; } + #else regval |= (((uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & - CAN_TIR_STID_MASK); + CAN_TIR_STID_MASK); + +#endif #ifdef CONFIG_CAN_USE_RTR regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); #endif -#endif + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the DLC */ @@ -1382,7 +1393,7 @@ static bool stm32can_txready(FAR struct can_dev_s *dev) /* Return true if any mailbox is available */ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); return stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) || stm32can_txmb2empty(regval); @@ -1414,7 +1425,7 @@ static bool stm32can_txempty(FAR struct can_dev_s *dev) /* Return true if all mailboxes are available */ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); return stm32can_txmb0empty(regval) && stm32can_txmb1empty(regval) && stm32can_txmb2empty(regval); @@ -1720,8 +1731,8 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) uint32_t ts1; uint32_t ts2; - caninfo("CAN%d PCLK1: %ld baud: %" PRId32 "\n", - priv->port, STM32_PCLK1_FREQUENCY, priv->baud); + caninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", + priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud); /* Try to get CAN_BIT_QUANTA quanta in one bit_time. * @@ -1773,8 +1784,8 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } - caninfo("TS1: %" PRId32 " TS2: %" PRId32 " BRP: %" PRId32 "\n", - ts1, ts2, brp); + caninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", + ts1, ts2, brp); /* Configure bit timing. This also does the following, less obvious * things. Unless loopback mode is enabled, it: @@ -1819,7 +1830,7 @@ static int stm32can_enterinitmode(FAR struct stm32_can_s *priv) uint32_t regval; volatile uint32_t timeout; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Enter initialization mode */ @@ -1893,9 +1904,8 @@ static int stm32can_exitinitmode(FAR struct stm32_can_s *priv) if (timeout < 1) { - canerr("ERROR: Timed out waiting to " - "exit initialization mode: %08" PRIx32 "\n", - regval); + canerr("ERROR: Timed out waiting to exit initialization mode: %08" + PRIx32 "\n", regval); return -ETIMEDOUT; } @@ -1921,7 +1931,7 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv) uint32_t regval; int ret; - caninfo("CAN%d\n", priv->port); + caninfo("CAN%" PRIu8 "\n", priv->port); /* Exit from sleep mode */ @@ -2004,7 +2014,7 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv) uint32_t regval; uint32_t bitmask; - caninfo("CAN%d filter: %d\n", priv->port, priv->filter); + caninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); /* Get the bitmask associated with the filter used by this CAN block */ @@ -2241,7 +2251,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port) { FAR struct can_dev_s *dev = NULL; - caninfo("CAN%d\n", port); + caninfo("CAN%" PRIu8 "\n", port); /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided * by stm32_clockconfig() early in the reset sequence. diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig index b44c5ce18a..50cfc0131e 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig @@ -26,16 +26,14 @@ CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_DTCM=y CONFIG_ARMV7M_ICACHE=y -CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y CONFIG_CAN_USE_RTR=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y CONFIG_CLOCK_MONOTONIC=y CONFIG_DEV_GPIO=y CONFIG_DRVR_READAHEAD=y +CONFIG_ETH0_PHY_LAN8742A=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y @@ -47,6 +45,26 @@ CONFIG_LIBM=y CONFIG_MM_REGIONS=2 CONFIG_MODULE=y CONFIG_MQ_MAXMSGSIZE=256 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DRIPADDR=0xc0a8b201 +CONFIG_NETINIT_IPADDR=0xc0a8b2b2 +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 @@ -85,7 +103,15 @@ CONFIG_STM32F7_CAN_TSEG2=6 CONFIG_STM32F7_DMA1=y CONFIG_STM32F7_DMA2=y CONFIG_STM32F7_DMACAPABLE=y -CONFIG_STM32F7_OTGFS=y +CONFIG_STM32F7_ETHMAC=y +CONFIG_STM32F7_PHYADDR=0 +CONFIG_STM32F7_PHYSR=31 +CONFIG_STM32F7_PHYSR_100FD=0x0018 +CONFIG_STM32F7_PHYSR_100HD=0x0008 +CONFIG_STM32F7_PHYSR_10FD=0x0014 +CONFIG_STM32F7_PHYSR_10HD=0x0004 +CONFIG_STM32F7_PHYSR_ALTCONFIG=y +CONFIG_STM32F7_PHYSR_ALTMODE=0x001c CONFIG_STM32F7_PWM_MULTICHAN=y CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y CONFIG_STM32F7_TIM1=y @@ -102,11 +128,12 @@ CONFIG_STM32F7_TIM3_CHANNEL2=y CONFIG_STM32F7_TIM3_CHANNEL3=y CONFIG_STM32F7_TIM3_CHANNEL4=y CONFIG_STM32F7_TIM3_PWM=y +CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_TIME64=y CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_BAUD=1200000 -CONFIG_USBDEV=y +CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USERLED=y CONFIG_USERLED_LOWER=y CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c index 9e5b82230f..e765a73365 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c @@ -65,7 +65,7 @@ /* The number of ADC channels in the conversion list */ -#define ADC1_NCHANNELS 1 +#define ADC1_NCHANNELS 3 /**************************************************************************** * Private Data @@ -79,7 +79,7 @@ #ifdef CONFIG_STM32F7_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { - 3 + 3, 10, 13 }; /* Configurations of pins used byte each ADC channels @@ -93,7 +93,9 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = static const uint32_t g_pinlist[ADC1_NCHANNELS] = { - GPIO_ADC1_IN3 + GPIO_ADC1_IN3, + GPIO_ADC1_IN10, + GPIO_ADC1_IN13 }; #endif