diff --git a/arch/arm/src/sama5/sam_pio.c b/arch/arm/src/sama5/sam_pio.c
index a259a345dd..9c40b50740 100644
--- a/arch/arm/src/sama5/sam_pio.c
+++ b/arch/arm/src/sama5/sam_pio.c
@@ -61,6 +61,11 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+/* Macros to convert a pin to a vanilla input */
+
+#define PIO_INPUT_BITS (PIO_INPUT | PIO_CFG_DEFAULT)
+#define MK_INPUT(p)    (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | PIO_INPUT_BITS)
+
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -335,7 +340,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
   /* Enable/disable the Schmitt trigger */
 
   regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
-  if ((cfgset & PIO_CFG_PULLDOWN) != 0)
+  if ((cfgset & PIO_CFG_SCHMITT) != 0)
     {
       regval |= pin;
     }
@@ -370,6 +375,11 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
   putreg32(regval, base + offset);
 #endif
 
+  /* Clear some output only bits.  Mostly this just simplifies debug. */
+
+  putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
+  putreg32(pin, base + SAM_PIO_CODR_OFFSET);
+
   /* Configure the pin as an input and enable the PIO function */
 
   putreg32(pin, base + SAM_PIO_ODR_OFFSET);
@@ -630,7 +640,11 @@ int sam_configpio(pio_pinset_t cfgset)
 
   putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
 
-  /* Handle the pin configuration according to pin type */
+  /* Put the pin in an intial state -- a vanilla input pint */
+
+  (void)sam_configinput(base, pin, MK_INPUT(cfgset));
+
+  /* Then handle the real pin configuration according to pin type */
 
   switch (cfgset & PIO_MODE_MASK)
     {
diff --git a/arch/arm/src/sama5/sam_pio.h b/arch/arm/src/sama5/sam_pio.h
index a090a156ba..f3d08bbd07 100644
--- a/arch/arm/src/sama5/sam_pio.h
+++ b/arch/arm/src/sama5/sam_pio.h
@@ -98,11 +98,11 @@
 #define PIO_CFG_SHIFT             (15)        /* Bits 15-19: PIO configuration bits */
 #define PIO_CFG_MASK              (31 << PIO_CFG_SHIFT)
 #  define PIO_CFG_DEFAULT         (0  << PIO_CFG_SHIFT) /* Default, no attribute */
-#  define PIO_CFG_PULLUP          (1  << PIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
-#  define PIO_CFG_PULLDOWN        (2  << PIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
-#  define PIO_CFG_DEGLITCH        (4  << PIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
-#  define PIO_CFG_OPENDRAIN       (8  << PIO_CFG_SHIFT) /* Bit 13: Open drain */
-#  define PIO_CFG_SCHMITT         (16 << PIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
+#  define PIO_CFG_PULLUP          (1  << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
+#  define PIO_CFG_PULLDOWN        (2  << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
+#  define PIO_CFG_DEGLITCH        (4  << PIO_CFG_SHIFT) /* Bit 17: Internal glitch filter */
+#  define PIO_CFG_OPENDRAIN       (8  << PIO_CFG_SHIFT) /* Bit 18: Open drain */
+#  define PIO_CFG_SCHMITT         (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
 
 /* Drive Strength:
  *