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xtensa:esp32s3: setup software interrupt as swi interrupt.

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Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
This commit is contained in:
zhuyanlin 2022-02-18 14:18:42 +08:00 committed by Abdelatif Guettouche
parent bf40d70df9
commit fc9791c269
4 changed files with 25 additions and 7 deletions
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4
arch/xtensa/include/esp32s3/core-isa.h
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@ -359,6 +359,8 @@
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
#define XCHAL_SYSCALL_LEVEL 2
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
@ -474,11 +476,13 @@
#define XTHAL_TIMER_UNCONFIGURED -1
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_SOFTWARE0_INTERRUPT 7 /* software interrupt 0 */
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
#define XCHAL_PROFILING_INTERRUPT 11
#define XCHAL_SOFTWARE1_INTERRUPT 29 /* software interrupt 1 */
/* Interrupt numbers for levels at which only one interrupt is configured: */

5
arch/xtensa/include/esp32s3/irq.h
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@ -185,9 +185,10 @@
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 4 /* First peripheral IRQ number */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.

2
arch/xtensa/src/esp32s3/Make.defs
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@ -39,7 +39,7 @@ CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c xtensa_swint.c
# Configuration-dependent common XTENSA files

21
arch/xtensa/src/esp32s3/esp32s3_irq.c
View File

@ -334,6 +334,10 @@ void up_irqinitialize(void)
g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32S3_CPUINT_SOFTWARE1);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32S3_CPUINT_SOFTWARE1);
/* Initialize CPU interrupts */
esp32s3_cpuint_initialize();
@ -343,6 +347,14 @@ void up_irqinitialize(void)
up_irq_enable();
#endif
/* Attach the software interrupt */
irq_attach(XTENSA_IRQ_SWINT, (xcpt_t)xtensa_swint, NULL);
/* Enable the software CPU interrupt. */
up_enable_irq(XTENSA_IRQ_SWINT);
}
/****************************************************************************
@ -484,12 +496,13 @@ int esp32s3_cpuint_initialize(void)
* ESP32S3_CPUINT_PROFILING 11 Not yet defined
* ESP32S3_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1
* ESP32S3_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2
* ESP32S3_CPUINT_SOFTWARE1 29 Not yet defined
* ESP32S2_CPUINT_SOFTWARE1 29 XTENSA_IRQ_SWINT 4
*/
intmap[ESP32S3_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0);
intmap[ESP32S3_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1);
intmap[ESP32S3_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2);
intmap[ESP32S3_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0);
intmap[ESP32S3_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1);
intmap[ESP32S3_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2);
intmap[ESP32S3_CPUINT_SOFTWARE1] = CPUINT_ASSIGN(XTENSA_IRQ_SWINT);
return OK;
}