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There are some small problems in LPC43xx RS485 mode configuration. In particular: 1. UART0,2,3 do not have DTR pins (different from UART1), so, Kconfig needs to be adjusted. 2. lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't enable pin output for UART0,2,3. 3. should be option to reverse DIR control pin output polarity. 4. lpc43xx/chip/lpc43_uart.h doesn't have USART3 definitions. NOTE: I didn't modified and didn't tested USART1, as it has different hardware. From Vytautas Lukenskas.

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This commit is contained in:
Vytautas Lukenskas 2016-09-30 07:45:39 -06:00 committed by Gregory Nutt
parent 937a83d9e4
commit fd1de92016
5 changed files with 119 additions and 24 deletions
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31
arch/arm/src/lpc43xx/Kconfig
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@ -638,11 +638,16 @@ config USART0_RS485MODE
---help---
Enable RS-485 interface on USART0.
config USART0_RS485_DTRDIR
bool "USART0 DTR for DIR"
if USART0_RS485_MODE
config USART0_RS485DIROIN
bool "Invert direction control pin polarity"
default n
---help---
Use the USART DTR pin for the DIR pin
If disabled, control pin will be driven to logic 0 when the
transmitter has data to be sent. It will be driven to logic 1 after
the last bit of data has been transmitted.
endif # USART0_RS485MODE
endif # LPC43_USART0
@ -670,11 +675,15 @@ config USART2_RS485MODE
---help---
Enable RS-485 interface on USART2.
config USART2_RS485_DTRDIR
bool "USART2 DTR for DIR"
if USART2_RS485MODE
config USART0_RS485DIROIN
bool "Invert direction control pin polarity"
default n
---help---
Use the USART DTR pin for the DIR pin
If disabled, control pin will be driven to logic 0 when the transmitter has data to be sent.
It will be driven to logic 1 after the last bit of data has been transmitted.
endif # USART2_RS485MODE
endif # LPC43_USART2
@ -686,11 +695,15 @@ config USART3_RS485MODE
---help---
Enable RS-485 interface on USART3.
config USART3_RS485_DTRDIR
bool "USART3 DTR for DIR"
if USART3_RS485MODE
config USART3_RS485DIROIN
bool "Invert direction control pin polarity"
default n
---help---
Use the USART DTR pin for the DIR pin
If disabled, control pin will be driven to logic 0 when the transmitter has data to be sent.
It will be driven to logic 1 after the last bit of data has been transmitted.
endif # USART3_RS485MODE
endif # LPC43_USART3
endmenu # RS-485 Configuration

22
arch/arm/src/lpc43xx/chip/lpc43_uart.h
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@ -168,6 +168,28 @@
#define LPC43_USART2_SYNCCTRL (LPC43_USART2_BASE+LPC43_USART_SYNCCTRL_OFFSET)
#define LPC43_USART2_TER (LPC43_USART2_BASE+LPC43_USART_TER_OFFSET)
#define LPC43_USART3_RBR (LPC43_USART3_BASE+LPC43_UART_RBR_OFFSET)
#define LPC43_USART3_THR (LPC43_USART3_BASE+LPC43_UART_THR_OFFSET)
#define LPC43_USART3_DLL (LPC43_USART3_BASE+LPC43_UART_DLL_OFFSET)
#define LPC43_USART3_DLM (LPC43_USART3_BASE+LPC43_UART_DLM_OFFSET)
#define LPC43_USART3_IER (LPC43_USART3_BASE+LPC43_UART_IER_OFFSET)
#define LPC43_USART3_IIR (LPC43_USART3_BASE+LPC43_UART_IIR_OFFSET)
#define LPC43_USART3_FCR (LPC43_USART3_BASE+LPC43_UART_FCR_OFFSET)
#define LPC43_USART3_LCR (LPC43_USART3_BASE+LPC43_UART_LCR_OFFSET)
#define LPC43_USART3_LSR (LPC43_USART3_BASE+LPC43_UART_LSR_OFFSET)
#define LPC43_USART3_SCR (LPC43_USART3_BASE+LPC43_UART_SCR_OFFSET)
#define LPC43_USART3_ACR (LPC43_USART3_BASE+LPC43_UART_ACR_OFFSET)
#define LPC43_USART3_ICR (LPC43_USART3_BASE+LPC43_USART_ICR_OFFSET)
#define LPC43_USART3_FDR (LPC43_USART3_BASE+LPC43_UART_FDR_OFFSET)
#define LPC43_USART3_OSR (LPC43_USART3_BASE+LPC43_USART_OSR_OFFSET)
#define LPC43_USART3_HDEM (LPC43_USART3_BASE+LPC43_USART_HDEN_OFFSET)
#define LPC43_USART3_SCICTRL (LPC43_USART3_BASE+LPC43_USART_SCICTRL_OFFSET)
#define LPC43_USART3_RS485CTRL (LPC43_USART3_BASE+LPC43_UART_RS485CTRL_OFFSET)
#define LPC43_USART3_ADRMATCH (LPC43_USART3_BASE+LPC43_UART_ADRMATCH_OFFSET)
#define LPC43_USART3_RS485DLY (LPC43_USART3_BASE+LPC43_UART_RS485DLY_OFFSET)
#define LPC43_USART3_SYNCCTRL (LPC43_USART3_BASE+LPC43_USART_SYNCCTRL_OFFSET)
#define LPC43_USART3_TER (LPC43_USART3_BASE+LPC43_USART_TER_OFFSET)
/* Register bit definitions *****************************************************************/
/* RBR (DLAB =0) Receiver Buffer Register */

3
arch/arm/src/lpc43xx/lpc43_config.h
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@ -73,7 +73,6 @@
#ifndef CONFIG_LPC43_USART0
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART0_RS485MODE
# undef CONFIG_USART0_RS485_DTRDIR
#endif
#ifndef CONFIG_LPC43_UART1
@ -85,13 +84,11 @@
#ifndef CONFIG_LPC43_USART2
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART2_RS485MODE
# undef CONFIG_USART2_RS485_DTRDIR
#endif
#ifndef CONFIG_LPC43_USART3
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART3_RS485MODE
# undef CONFIG_USART3_RS485_DTRDIR
#endif
/* Is there a serial console? There should be at most one defined. It could be on

9
arch/arm/src/lpc43xx/lpc43_serial.c
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@ -169,9 +169,6 @@ static struct up_dev_s g_uart0priv =
.parity = CONFIG_USART0_PARITY,
.bits = CONFIG_USART0_BITS,
.stopbits2 = CONFIG_USART0_2STOP,
#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR)
.dtrdir = true,
#endif
};
static uart_dev_t g_uart0port =
@ -239,9 +236,6 @@ static struct up_dev_s g_uart2priv =
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR)
.dtrdir = true,
#endif
};
static uart_dev_t g_uart2port =
@ -274,9 +268,6 @@ static struct up_dev_s g_uart3priv =
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR)
.dtrdir = true,
#endif
};
static uart_dev_t g_uart3port =

78
arch/arm/src/lpc43xx/lpc43_uart.c
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@ -364,7 +364,31 @@ void lpc43_usart0_setup(void)
#ifdef CONFIG_USART0_RS485MODE
lpc43_pin_config(PINCONF_U0_DIR);
#endif
/* Enable direction output pin */
regval = getreg32(LPC43_USART0_RS485CTRL);
regval |= UART_RS485CTRL_DCTRL;
putreg32(regval, LPC43_USART0_RS485CTRL);
#ifdef CONFIG_USART0_RS485DIROIN
/* Invert direction control output pin polarity */
regval = getreg32(LPC43_USART0_RS485CTRL);
regval |= UART_RS485CTRL_OINV;
putreg32(regval, LPC43_USART0_RS485CTRL);
#else
/* Do not invert direction countrol output pin polarity */
regval = getreg32(LPC43_USART0_RS485CTRL);
regval &= ~(UART_RS485CTRL_OINV);
putreg32(regval, LPC43_USART0_RS485CTRL);
#endif /* CONFIG_USART0_RS485DIROIN */
#endif /* CONFIG_USART0_RS485MODE */
leave_critical_section(flags);
};
@ -467,7 +491,31 @@ void lpc43_usart2_setup(void)
#ifdef CONFIG_USART2_RS485MODE
lpc43_pin_config(PINCONF_U2_DIR);
#endif
/* Enable direction output pin */
regval = getreg32(LPC43_USART2_RS485CTRL);
regval |= UART_RS485CTRL_DCTRL;
putreg32(regval, LPC43_USART2_RS485CTRL);
#ifdef CONFIG_USART2_RS485DIROIN
/* Invert direction control output pin polarity */
regval = getreg32(LPC43_USART2_RS485CTRL);
regval |= UART_RS485CTRL_OINV;
putreg32(regval, LPC43_USART2_RS485CTRL);
#else
/* Do not invert direction countrol output pin polarity */
regval = getreg32(LPC43_USART2_RS485CTRL);
regval &= ~(UART_RS485CTRL_OINV);
putreg32(regval, LPC43_USART2_RS485CTRL);
#endif /* CONFIG_USART2_RS485DIROIN */
#endif /* CONFIG_USART2_RS485MODE */
leave_critical_section(flags);
};
@ -516,7 +564,31 @@ void lpc43_usart3_setup(void)
#ifdef CONFIG_USART3_RS485MODE
lpc43_pin_config(PINCONF_U3_DIR);
#endif
/* Enable direction output pin */
regval = getreg32(LPC43_USART3_RS485CTRL);
regval |= UART_RS485CTRL_DCTRL;
putreg32(regval, LPC43_USART3_RS485CTRL);
#ifdef CONFIG_USART3_RS485DIROIN
/* Invert direction control output pin polarity */
regval = getreg32(LPC43_USART3_RS485CTRL);
regval |= UART_RS485CTRL_OINV;
putreg32(regval, LPC43_USART3_RS485CTRL);
#else
/* Do not invert direction countrol output pin polarity */
regval = getreg32(LPC43_USART3_RS485CTRL);
regval &= ~(UART_RS485CTRL_OINV);
putreg32(regval, LPC43_USART3_RS485CTRL);
#endif /* CONFIG_USART3_RS485DIROIN */
#endif /* CONFIG_USART3_RS485MODE */
leave_critical_section(flags);
};