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STM32F33: Add ADC support

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This commit is contained in:
raiden00pl 2017-03-18 16:34:24 +01:00
parent 49e4e62aab
commit fd42900dcc
1 changed files with 44 additions and 25 deletions
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69
arch/arm/src/stm32/stm32_adc.c
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@ -6,6 +6,7 @@
* Authors: Gregory Nutt <gnutt@nuttx.org> * Authors: Gregory Nutt <gnutt@nuttx.org>
* Diego Sanchez <dsanchez@nx-engineering.com> * Diego Sanchez <dsanchez@nx-engineering.com>
* Paul Alexander Patience <paul-a.patience@polymtl.ca> * Paul Alexander Patience <paul-a.patience@polymtl.ca>
* Mateusz Szafoni <raiden00@railab.me>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -77,11 +78,12 @@
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
/* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */ /* This implementation is for the STM32 F1, F2, F3, F4 and STM32L15XX only */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
/* At the moment there is no proper implementation for timers external /* At the moment there is no proper implementation for timers external
* trigger in STM32L15XX May be added latter * trigger in STM32L15XX May be added latter
@ -91,6 +93,14 @@
# warning "There is no proper implementation for TIMER TRIGGERS at the moment" # warning "There is no proper implementation for TIMER TRIGGERS at the moment"
#endif #endif
/* At the moment there is no proper implementation for HRTIMER external
* trigger in STM32F33XX
*/
#if defined(ADC_HAVE_HRTIMER) && defined(CONFIG_STM32_STM32F33XX)
# warning "There is no proper implementation for HRTIMER TRIGGERS at the moment"
#endif
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
@ -108,6 +118,10 @@
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST # define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
# define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST # define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST
# define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST # define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST
#elif defined(CONFIG_STM32_STM32F33XX)
# define STM32_RCC_RSTR STM32_RCC_AHBRSTR
# define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
#elif defined(CONFIG_STM32_STM32F37XX) #elif defined(CONFIG_STM32_STM32F37XX)
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR # define STM32_RCC_RSTR STM32_RCC_APB2RSTR
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST # define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
@ -124,7 +138,7 @@
/* ADC interrupts ***********************************************************/ /* ADC interrupts ***********************************************************/
#ifdef CONFIG_STM32_STM32F30XX #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET # define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET
# define ADC_DMAREG_DMA ADC_CFGR_DMAEN # define ADC_DMAREG_DMA ADC_CFGR_DMAEN
# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET # define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET
@ -226,7 +240,7 @@
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
#elif defined(CONFIG_STM32_STM32F30XX) #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
# if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1) # if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1)
# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 # define ADC_SMPR_DEFAULT ADC_SMPR_61p5
# else /* Slow down sampling frequency */ # else /* Slow down sampling frequency */
@ -338,8 +352,8 @@ struct stm32_dev_s
/* ADC Register access */ /* ADC Register access */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32L15XX) defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits); uint32_t setbits);
#endif #endif
@ -606,8 +620,8 @@ static struct adc_dev_s g_adcdev4 =
****************************************************************************/ ****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32L15XX) defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits) uint32_t setbits)
{ {
@ -1242,7 +1256,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
adc_enable(priv, true); adc_enable(priv, true);
} }
#elif defined(CONFIG_STM32_STM32F30XX) #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
{ {
uint32_t regval; uint32_t regval;
@ -1520,7 +1534,7 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv,
* *
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_STM32_STM32F30XX #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
{ {
uint32_t regval; uint32_t regval;
@ -1699,8 +1713,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
* Name: adc_bind * Name: adc_bind
* *
* Description: * Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This * Bind the upper-half driver callbacks to the lower-half implementation.
* must be called early in order to receive ADC event notifications. * This must be called early in order to receive ADC event notifications.
* *
****************************************************************************/ ****************************************************************************/
@ -1718,8 +1732,8 @@ static int adc_bind(FAR struct adc_dev_s *dev,
* Name: adc_reset * Name: adc_reset
* *
* Description: * Description:
* Reset the ADC device. Called early to initialize the hardware. This * Reset the ADC device. Called early to initialize the hardware.
* is called, before adc_setup() and on error conditions. * This is called, before adc_setup() and on error conditions.
* *
* Input Parameters: * Input Parameters:
* *
@ -1751,7 +1765,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#endif #endif
#ifdef CONFIG_STM32_STM32F30XX #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
/* Turn off the ADC so we can write the RCC bits */ /* Turn off the ADC so we can write the RCC bits */
@ -1767,7 +1781,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_rccreset(priv, false); adc_rccreset(priv, false);
#ifdef CONFIG_STM32_STM32F30XX #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
/* Set voltage regular enable to intermediate state */ /* Set voltage regular enable to intermediate state */
@ -1822,7 +1836,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
#endif #endif
#ifdef CONFIG_STM32_STM32F30XX #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
/* Enable the analog watchdog */ /* Enable the analog watchdog */
@ -1870,7 +1884,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
#else /* ifdef CONFIG_STM32_STM32F30XX */ #else /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM33XX */
/* Enable the analog watchdog */ /* Enable the analog watchdog */
@ -1968,7 +1982,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* ADC CCR configuration */ /* ADC CCR configuration */
#if defined(CONFIG_STM32_STM32F30XX) #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG |
ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN |
ADC_CCR_TSEN | ADC_CCR_VBATEN; ADC_CCR_TSEN | ADC_CCR_VBATEN;
@ -1979,10 +1993,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
{ {
stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits); stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits);
} }
#ifndef CONFIG_STM32_STM32F33XX
else else
{ {
stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits); stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits);
} }
#endif
#elif defined(CONFIG_STM32_STM32F20XX) || \ #elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX) defined(CONFIG_STM32_STM32L15XX)
@ -2050,7 +2066,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
leave_critical_section(flags); leave_critical_section(flags);
#ifdef CONFIG_STM32_STM32F30XX #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n", ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n",
adc_getreg(priv, STM32_ADC_ISR_OFFSET), adc_getreg(priv, STM32_ADC_ISR_OFFSET),
adc_getreg(priv, STM32_ADC_CR_OFFSET), adc_getreg(priv, STM32_ADC_CR_OFFSET),
@ -2067,7 +2083,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
#if defined(CONFIG_STM32_STM32F30XX) #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
#elif defined(CONFIG_STM32_STM32L15XX) #elif defined(CONFIG_STM32_STM32L15XX)
ainfo("SQR4: 0x%08x SQR5: 0x%08x\n", ainfo("SQR4: 0x%08x SQR5: 0x%08x\n",
@ -2075,15 +2091,17 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); adc_getreg(priv, STM32_ADC_SQR5_OFFSET));
#endif #endif
#if defined(CONFIG_STM32_STM32F30XX) #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE)
{ {
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR)); ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR));
} }
#ifndef CONFIG_STM32_STM32F33XX
else else
{ {
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR)); ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR));
} }
#endif
#elif defined(CONFIG_STM32_STM32F20XX) || \ #elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX) defined(CONFIG_STM32_STM32L15XX)
@ -3085,8 +3103,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
} }
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX ||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX || * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX ||
* CONFIG_STM32_STM32F40XX || CONFIG_STM32_STM32L15XX * CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F40XX ||
* CONFIG_STM32_STM32L15XX
*/ */
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
* CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4